JP2008052504A - Discrete fourier transform device and discrete fourier inverse transform device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a discrete Fourier transform device and a discrete Fourier inverse transform device in which transform operation quantity is reduced and an arithmetic circuit is simplified. <P>SOLUTION: The discrete Fourier transform device is provided with: a first operation means for executing the product operation of each of N (N is a positive integer) input data and each of N rotation factors selected in prescribed order; a second operation means for adding N data obtained by the first operation means; a third operation means for executing product operation of data obtained by reversely arranging the order of data from the second data up to the N-th data out of N input data and each of the N rotation factors; a fourth operation means for adding N data obtained by the third operation means; a storage means for storing output data from the fourth operation means; and a control means for driving the first operation means up to the fourth operation means twice or more, and when the number of data stored in the storage means reaches N data, arranging the N data in the prescribed order and outputting the arranged data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a discrete Fourier transform apparatus and a discrete Fourier inverse transform apparatus that reduce the circuit scale of discrete Fourier transform in wireless communication or the like.

Conventionally, as a method of converting a discrete signal on a time axis into a discrete signal on a frequency axis, a fast Fourier transform (hereinafter referred to as FFT) that efficiently performs a discrete Fourier transform (hereinafter referred to as DFT: Discrete Fourier Transform) operation. (Fourier Transform) is used. The FFT converts N = 2 ^G pieces of data (G is a positive integer) on the time axis into data on N frequency axes.

  When the number of data to be subjected to FFT calculation (the value of N above) increases, the circuit scale of the FFT calculation increases and the delay time due to the calculation increases. As a countermeasure, two input data string storage units are provided, and while the input data stored in one storage unit is subjected to an FFT operation, the next input data string is stored in the other storage unit and alternately. The input means is switched and input data is continuously calculated by one FFT operation means. Further, there is a method of reducing the storage capacity of the FFT calculation result by storing the partial data of the common FFT calculation result in the same storage means by using the objectivity of the FFT calculation result (Patent Document 1).

In addition, for the number of data other than ^2G, there is a method of sequentially converting based on the DFT basics.

As a method for converting a discrete signal on the frequency axis into a discrete signal on the time axis, a fast Fourier inverse transform (hereinafter referred to as IFFT) that efficiently performs an inverse discrete Fourier transform (hereinafter referred to as IDFT: Inverse Discrete Fourier Transform) operation. : Inverse Fast Fourier Transform). The IFFT converts N = 2 ^G pieces of data on the frequency axis (G is a positive integer) into N pieces of data on the time axis.
JP-A-6-35951

The DFT based on the FFT operation described above can be applied when the number of data N on the time axis is 2 ^G (G is a positive integer), but cannot be used when the number of data is other than 2 ^G.

  Further, problems in the method of sequentially converting based on the basics of DFT will be described.

  A DFT that converts the nth data value x (n) of data on N time axes (N is a positive integer) to the kth data value X (k) of data on N frequency axes. The basic formula is shown in Formula (1).

ただし、ｎ＝０、１、２、・・・、（Ｎ−１）、ｋ＝０、１、２、・・・、（Ｎ−１）である。

However, n = 0, 1, 2,..., (N−1), k = 0, 1, 2,.

  W is a factor that gives an angular rotation of −2π / N that is obtained by dividing a unit circle of the complex plane into N equal parts, and is called a twiddle factor and is expressed by the equation (2).

以下、Ｗのｍ乗（ｍは、０、１、２、・・・（Ｎ−１））をＷ^ｍと記し、Ｗ^ｍは角度が（−２π／Ｎ）×ｍ回転する回転因子を表す。
（２）式の関係により、Ｗ^ｍは複素数である。
（１）式をマトリクスで表すと（３）式となる。

Hereinafter, W to the m-th power (m is 0, 1, 2,... (N−1)) is denoted as W ^m, and W ^m represents a twiddle factor that rotates the angle by (−2π / N) × m. .
(2) W ^m is a complex number due to the relationship of the equation.
When the expression (1) is expressed in a matrix, the expression (3) is obtained.

データ数Ｎ＝７個の場合について（Ｎが２^Ｇでは表されない数）、従来方法によるＤＦＴ演算を説明する。

In the case of the number of data N = 7 (N is a number not represented by ^2G ), the DFT operation by the conventional method will be described.

  Equation (3) becomes Equation (4) when N = 7.

なお、（４）式右辺回転因子マトリクスの第３行の第５列の回転因子はＷ^８とすべきであるが、回転因子Ｗ^８は角度が（−２π／７）×８＝−２π−（２π／７）×１でＷ^１と同値であるからＷ^１で表現し、同様に第６列の回転因子Ｗ^１０はＷ^３と同値であり、第７列の回転因子Ｗ^１２はＷ^５と同値であるからそれぞれＷ^３とＷ^５で表現する。

Incidentally, (4) and the right side twiddle factors in the third row fifth column of the twiddle factor matrix should be between ^{W 8,} the rotation factor ^{W 8} is angle (-2π / 7) × 8 = -2π- (2 [pi / 7) in × 1 represented by ^{W 1} and ^{W 1} because it is equivalent, similarly sixth column rotation factor ^{W 10} of a ^{W 3} equivalent to the rotation factor ^{W 12} of the seventh column ^{W 5} Are represented by W ³ and W ⁵ respectively.

Similarly, the fourth, fifth, sixth, and seventh rows of the twiddle factor matrix on the right side of the equation (4) are all expressed by the twiddle factors W ^{0 to} W ⁶ .

In addition, the input data string in the second term on the right side of equation (4), x ₀ , x ₁ ,..., X ₆ is a sample value on the time axis and is a real number. Since each element W ^m is a complex number due to the relationship of equation (2), the product and addition operations on the right side of equation (4) are complex number operations.

  A specific example of a conventional DFT calculation method will be described.

  FIG. 1 shows a configuration example of a DFT arithmetic unit that performs the arithmetic operation of the equation (4) according to the conventional technique.

  In FIG. 1, 101 is a DFT arithmetic unit, 102 is a twiddle factor storage memory, 103 is a twiddle factor selection processing A section, 104 is a twiddle factor selection processing B section, 105 is an input data storage register section, 106 is a complex multiplication A section, Reference numeral 107 denotes a complex multiplication B section, 108 denotes a complex addition A section, 109 denotes a complex addition B section, 110 denotes an output data storage register section, and 111 denotes a control section.

  FIG. 2 shows a time chart for calculating the DFT of seven data according to the prior art by the equation (4).

In FIG. 2, D201 is an input clock, D202 is an input data string, D203 is a data string of the twiddle factor process A part for the first calculation, D204 is a data string of the twiddle factor process B part for the first calculation, and D205 is the first calculation. data string of complex multiplication a and the output X ₀ of the operation and the operation result of complex addition _a, D206 data column of arithmetic first complex multiplication B and output X ₁ of the operation and the operation result of complex addition _B, D207 Is the data string of the twiddle factor process A part of the second calculation, D208 is the data string of the twiddle factor process B part of the second calculation, D209 is the data string of the second complex multiplication A and the calculation and calculation of the complex addition A the resulting output X _2, D210 data column of arithmetic second complex multiplication B and, calculation and calculation result of the output X ₃ complex additions _B, D211 arithmetic third rotation factor treatment a portion of the data , D 212 is operational third rotation factor treatment B of the data sequence, D213 is data string of operations third complex multiplication A and the calculation and the calculation result of complex additions A output X _4, D 214 are operational third complex Data string of multiplication B, calculation X of complex addition B and output X ₅ and D 215 are data strings of the twiddle factor processing A part for the fourth calculation, D 216 are data string of complex multiplication A for the fourth calculation and complex shows the output X ₆ of the operation and the arithmetic result of the addition a, respectively.

  The DFT operation according to the prior art will be described with reference to the configuration diagram of FIG. 1 focusing on the DFT time chart of FIG.

X ₀ , x ₁ ,..., X ₆ of the input data string D 202 of the time-axis samples input to the DFT arithmetic unit 101 are temporarily stored in the input data storage register unit 105. The clock D201 input in combination with the input data string D202 of the time-axis sample is distributed to each unit in the DFT arithmetic unit 101 via the control unit 111.

The input data string temporarily stored in the input data storage register unit 105 is sequentially read out in synchronization with the clock D201 to become D202, and each element x ₀ , x ₁ ,. to form a x _6.

As the first DFT operation, the calculation of the element X _{0 in} the first row on the left side in the equation (4) is performed by the twiddle factor selection processing A unit 103, the complex operation A unit 106, and the complex addition A unit 108. the operation of the elements _{X 1,} twiddle factor selection processing unit B 104, the complex operation B 107 performs the complex adder B 109 calculates two _{X 0} and _{X 1} simultaneously in parallel.

For DFT calculation for obtaining the X _0, the rotation factor selection process A 103, (4) for generating the right-hand side first line of the first term W matrix, stored in a twiddle factor storage memory 102 ^{W 0} Is designated as a read D203. The complex multiplication A unit 106 sequentially performs complex multiplication of x ₀ , x ₁ ,..., X _{6 of} the input data string D202 temporarily stored in the input data storage register unit 105 with each term of D203 according to the clock D201. performed, seven sections D205 multiplication results X ₀ are complex addition in the complex adder a portion 108 is obtained and stored in the output data storage register unit 110.

For DFT calculation for obtaining the X _1, twiddle factor selection processing B 104 (4) for generating a right second line of the first term W matrix, stored in a twiddle factor storage memory 102 ^{W 0} , W ¹ , W ² ,... W ⁶ are sequentially designated and read according to the clock D201 to obtain seven data strings D204.

In the complex multiplication B unit 107, complex multiplication of each term of x ₀ , x ₁ ,..., X ₆ of the input data string D202 and each term of D204 is sequentially performed according to the clock D201, and seven multiplication results are obtained. section D206 is _{X 1} is the complex addition is obtained at the complex adder B 109, is stored in the output data storage register unit 110.

Next, as the _second calculation, the calculation of the element X2 in the third row on the left side in the equation (4) is performed by the twiddle factor selection processing A unit, the complex calculation A unit, and the complex addition A unit. ₃ is performed by the twiddle factor selection processing unit B, complex operation unit B, and complex addition unit B, and _two of X ₂ and X ₃ are calculated simultaneously in parallel.

For DFT calculation for obtaining the X _2, the rotation factor selection process A 103, (4) to generate the right side third row of the first term W matrix, stored in a twiddle factor storage memory 102 ^{W 0} , W ² , W ⁴ ,... W ⁵ are sequentially designated and read according to the clock D 201 to obtain seven data strings D 207.

In the complex multiplication A section 106, complex multiplication of each term of x ₀ , x ₁ ,..., X ₆ of the input data string D202 and each term of D207 is sequentially performed according to the clock D201, and seven multiplication results are obtained. section D209 is _{X 2} are the complex addition is obtained at the complex adder a unit 108, is stored in the output data storage register unit 110.

For DFT calculation for obtaining the X _3, twiddle factor selection processing B 104 (4) to generate the right-hand side line 4 of Paragraph 1 W matrix, stored in a twiddle factor storage memory 102 ^{W 0} , W ³ , W ⁶ ,... W ⁴ are sequentially designated and read in accordance with the clock D201 to obtain seven data strings D208.

In the complex multiplication B unit 107, complex multiplication of each term of x ₀ , x ₁ ,..., X ₆ of the input data string D202 and each term of D208 is sequentially performed according to the clock D201, and seven multiplication results are obtained. section D210 is _{X 1} is the complex addition is obtained at the complex adder B 109, is stored in the output data storage register unit 110.

Similarly, X ₄ and X ₅ are calculated in parallel in the third DFT calculation, and the remaining X ₆ is calculated in the fourth calculation and stored in the output data storage register unit 110.

The DFT operation result stored in the output data storage register unit 110 is a series of data on the frequency axis when storage of the data strings X ₀ , X ₁ , X ₂ , X ₃ , X ₄ , X ₅ , X ₆ is completed. It is arranged as a column and output to the outside.

  The control unit 111 distributes the input clock to each unit, instructs the operation start time to each unit, receives notification of the operation end time in each unit, and controls the DFT arithmetic unit 101 as a whole.

  Since this method performs two operations simultaneously in parallel, there is an advantage that the DFT operation speed is increased. However, the rearrangement of the twiddle factor matrix needs to be performed over all rows of the twiddle factor matrix. Since the number of rows in the twiddle factor matrix is equal to the number of data N, the number of wirings in the twiddle factor selection processing section A 103 and the twiddle factor selection section B 104 increases as N increases. There is a problem that the processing time increases due to the length.

Further, the discrete signals _{X 0,} X 1 on the frequency axis, _..., inverse discrete Fourier the _{X N-1,} to convert the time discrete signal _{x 0,} x 1 on the shaft, _..., to the _{x N-1} The conversion (IDFT) needs to be performed over all rows of the reciprocal matrix of the twiddle factor, and there is a problem that the wiring between the circuits is crowded and the processing time increases due to the wiring length.

  Accordingly, one of the objects of the present invention is to provide a discrete Fourier transform device and a discrete Fourier inverse transform device that reduce the amount of transform computation and simplify the computation circuit.

  The present invention is not limited to the above-described object, and the effects derived from the respective configurations shown in the best mode for carrying out the invention to be described later and which cannot be obtained by conventional techniques are another object of the present invention. Can be positioned as

(1) In the present invention, first storage means for storing N (N is a positive integer) input data, second storage means for storing N twiddle factors, and the first storage means The product of each of the N pieces of input data read out in sequence from each of the N pieces of twiddle factor data read out in a predetermined order from the second storage means, and the addition of the products A first calculating unit, a rearranging unit for rearranging the N-th input data of the first storage unit in reverse order from the second to the Nth, and reading in order from the rearranging unit; A product of each of the N input data that has been output and each of the N pieces of twiddle factor data read in a predetermined order from the second storage means, and a second operation for adding the products Means and data obtained by the first computing means and the second computing means are stored. When the number of data stored in the third storage unit reaches N, the storage unit 3 and the first and second calculation units are operated a plurality of times in parallel. A discrete Fourier transform device characterized by comprising control means for arranging and outputting in order is used.
(2) When the first and second calculation means use the first row in a twiddle factor matrix composed of N rows and N columns of discrete Fourier transform as the twiddle factor data, the first to Nth columns. Are sequentially read out and one of the first or second calculation means performs the calculation, and when the number of input data N is an odd number, the second row to the (N−1) / 2 + 1th row in the twiddle factor matrix When the number of input data N is an even number, the first column to the Nth column are sequentially read and used in common for the calculation by the first and second calculation means. When using the second row to the (N / 2) th row in the twiddle factor matrix, the first column to the Nth column are sequentially read and used in common for the calculation by the first and second calculation means. To (N / 2) +1 line It uses a discrete Fourier transform apparatus of claim 1, wherein the performing operations with one of the first or second calculating means reads from the first column to the N columns when used.
(3) In the present invention, first storage means for storing N (N is a positive integer) input data, second storage means for storing N twiddle factors, and the first storage means Each of the N pieces of input data read in order from the second storage means and each of the reciprocal data of the N twiddle factors read out from the second storage means in a predetermined order, and A first computing means for performing addition, a rearranging means for rearranging the N input data of the first storage means in reverse order from the second to the Nth, and the rearranging means The product of each of the N input data read in order and the data of the reciprocal of the N twiddle factors read in a predetermined order from the second storage means, and the addition of the products A second arithmetic means for performing the processing, the data obtained by the first arithmetic means and the second arithmetic means. The third storage means for storing the data by multiplying by 1 / N and the operations of the first and second calculation means in parallel multiple times, and the number of data stored in the third storage means is N A discrete Fourier inverse transform device characterized by comprising control means for arranging and outputting the N pieces of data in a predetermined order when the number reaches the number is used.

  Preferably, when the first and second calculation means use the first row in the matrix of reciprocals of twiddle factors composed of N rows and N columns of discrete Fourier transform as the reciprocal data of the twiddle factors, the first column To the Nth column in order, one of the first or second calculation means performs the calculation, and when the number of input data N is an odd number, the second row in the matrix of the reciprocal number of the twiddle factor ( When (N-1) / 2 + 1 rows are used, the first column to the Nth column are sequentially read and used in common for the calculations by the first and second calculation means, and the number of input data N When the number is even, when the second to (N / 2) th rows are used in the reciprocal matrix of the twiddle factors, the first and second columns are sequentially read out from the first column to the Nth column, respectively. Commonly used for calculation by calculation means 4. An operation is performed, and when the (N / 2) + 1th row is used, the first to Nth columns are read and the operation is performed by one of the first or second operation means. The discrete Fourier inverse transform device described is used.

  According to the present invention, it is possible to provide a DFT arithmetic device and an IDFT arithmetic device in which the DFT arithmetic amount is reduced and the DFT arithmetic circuit is simplified.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Example 1)
In the first embodiment, the DFT operation is performed when the number of samples on the time axis of the input data string is seven.

  FIG. 3 shows the configuration of the DFT operation apparatus, FIG. 4 shows the twiddle factor storage memory table, FIG. 5 shows the operation of the input data rearrangement processing unit, and FIG. 6 shows the DFT operation time chart.

  3, 301 is a DFT arithmetic unit, 302 is a twiddle factor storage memory, 303 is a twiddle factor selection processing unit, 304 is an input data storage register unit, 305 is an input data rearrangement processing unit, 306 is a complex multiplication A unit, 307 Is a complex multiplication B section, 308 is a complex addition A section, 309 is a complex addition B section, 310 is an output data storage register section, and 311 is a control section.

  In FIG. 4, D401 indicates an address number of the twiddle factor storage table, and D402 indicates twiddle factor data.

  In FIG. 5, D501 indicates the input data order of the input data storage register unit, and D502 indicates the input data order of the input data rearrangement processing unit output.

In FIG. 6, D601 is an input clock, D602 is an input data string, D603 is a data string in which the input data string is rearranged, D604 is a data string of a twiddle factor processing unit for the first calculation, and D605 is a complex multiplication for the first calculation. A data string of A, and calculation output of the complex addition A and the output X ₀ , D 606 are the data string of the second twiddle factor processing unit, D 607 are the data string of the second complex multiplication A and the complex addition A data sequence and outputs X ₆ of the operation and the operation result of complex addition _B, D609 data row of rotating factor treatment of operational third operation as a result of the operation output X _1, D608 arithmetic second complex multiplication B of , D610 is data string of operations third complex multiplication a and output X _2, D611 calculation and calculation result of complex additions a data sequence of operations third complex multiplication B and complex Calculation output X ₅ of the operation with the operation result of _B, D612 arithmetic fourth rotation factor processing unit of the data sequence, D613 is data string of calculation fourth complex multiplication A and the calculation and the calculation result of complex additions A output X ₃ and D 614 respectively indicate the data string of the complex multiplication B for the fourth calculation, and the output X ₄ of the calculation of the complex addition B and the calculation result.

  In the formula (4) showing the basics of DFT, the second row of the twiddle factor W matrix becomes equal to the seventh row by reversing the column order of the second to seventh columns. The third row is equal to the sixth row when the column order of the second to seventh columns is reversed, and the fourth row of the twiddle factor W matrix is fifth when the column order of the second to seventh columns is reversed. Take advantage of the property of being equal to a row.

In the first embodiment, x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ , x ₆ of the input data string D602 are arranged as they are in the first embodiment, and the second row of the W matrix is utilized. D606 calculates a product / addition of W ⁰ , W ¹ , W ² , W ³ , W ⁴ , W ⁵ , and W ⁶ to obtain an output X ₁ , and an arrangement of the column order after the second item of the input data string The change is made according to FIG. 5, and x ₀ , x ₆ , x ₅ , x ₄ , x ₃ , x ₂ , x _{1 of} D 602, and W ⁰ , W ¹ , W ¹ of the second row D 606 of the same W matrix as described above. ² , W ³ , W ⁴ , W ⁵ , W ⁶ are used in common, and a product / addition operation and a sequence for obtaining X ₆ are operated in parallel.

Similarly, the output X ₂ and the output X ₅ use the W ⁰ , W ² , W ⁴ , W ⁶ , W ¹ , W ³ , and W ⁵ of the third row D609 of the W matrix in common, and perform a product / addition operation. It can be calculated by parallel operation of series.

Similarly, the output X ₃ and the output X ₄ use the W ⁰ , W ³ , W ⁶ , W ² , W ⁵ , W ¹ , W ⁴ in the fourth row D 612 of the W matrix in common, and perform product / addition operations. It can be calculated by parallel operation of series.

The input data string in the second term on the right side of equation (4), x ₀ , x ₁ ,..., X ₆ are sample values on the time axis and are real numbers. Since the element W ^m is a complex number due to the relationship of the expression (2), the product of the right-hand side and the addition operation are complex number operations.

  The DFT operation of the first embodiment will be described with reference to FIGS. 3, 4, 5, and 6, focusing on the DFT time chart of FIG.

The time-axis sample data strings x ₀ , x ₁ ,..., X ₆ input to the DFT arithmetic unit 301 are temporarily stored as D 602 in the input data storage register unit 304. The clock D601 input in combination with the sample data on the time axis is distributed to each unit in the DFT arithmetic unit 301 via the control unit 311.

The input data string D602 temporarily stored in the input data storage register unit 304 is sequentially read out in synchronization with the clock D601, and each element x ₀ , x ₁ ,. ₆ is formed.

As the first DFT operation, for W ^{0 in the} first row on the left side in equation (4), there are no other rows in which all six columns are the same W ⁰ , so only the first row of the W matrix is used. The twiddle factor selection processing unit 303, the complex operation A unit 306, and the complex addition A unit 308 perform X ₀ DFT operation.

For DFT calculation for obtaining the X _0, the rotation factor selection processing section 303, (4) right side of the equation for generating the first row of the first term W matrix of ^{W 0} stored in a twiddle factor storage memory 102 An address is designated and read out as D604. In the complex multiplication A unit 306, complex multiplication of each term x ₀ , x ₁ ,..., X ₆ and D604 of the input data string D602 temporarily stored in the input data storage register unit 304 is performed according to the clock D601. sequentially performed, seven sections D605 multiplication results X ₀ are complex addition in the complex adder a 308 is obtained and stored in the output data storage register unit 310.

Next, as the operation second, (4) W uses the second row of the matrix to a common, (4) performing the left side second row X ₁ and the DFT calculation of X ₆ in the sixth row simultaneously in parallel.

For DFT calculation for obtaining the X _1, twiddle factor selection processing section 303, (4) for generating a right second line of the first term W matrix, ^W 0 stored in a twiddle factor storage memory 302, The addresses of W ¹ , W ² ,... W ⁶ are sequentially designated and read according to the clock D601 to obtain seven data strings D606 of W. In the complex multiplication A unit 306, complex multiplication of each term of the input data string D602 and each term of W of D606 is sequentially performed according to the clock D601, and the seven terms D607 of the multiplication result are complexed in the complex addition A unit 306. X ₁ is obtained by addition and is stored in the output data storage register unit 310.

For DFT calculation for obtaining the X _6, the rotation factor selecting section 303 uses the seven data string D606 having the same W as when operation of the _{X 1} in common.

DFT calculation for obtaining the X ₆ is (4) and line 7 W matrix equation right side is a first column of the product of x matrix, line 7 W matrix after the second column of the second row The column order is reversed.

Hence, DFT operation for obtaining the X ₆ is a second row of W matrix is equal to the product and the addition of each element of those interchanged up and down by 5 the second and subsequent rows of the row order of x matrix.

Each term of the input data string _{D602, x 0, x 1,} ···, x 6 is the input sorting unit 305, _{x 0} after the second column of the column order D602 front and rear turnover input data sequence D603 , X ₆ , x ₅ ,..., X ₁ .

The complex multiplier B 307, is sequentially performed according to the clock D601 complex multiplication of each term of the terms and D606 of D603, 7 pieces of section D608 of the multiplication result is _{X 6} is complex addition in the complex adder B 309 is obtained, It is stored in the output data storage register unit 110.

In the same manner, X ₂ and X ₅ are calculated in parallel in the third DFT calculation, and X ₃ and X ₄ are calculated in parallel in the _fourth calculation and stored in the output data storage register unit 110.

Output data storage register unit 110 DFT calculation results stored in, when storing data _{X 0, X 1, X 6} , X 2, X 5, X 3, X 4 is _{completed, X 0, X 1, X} 2 , X ₃ , X ₄ , X ₅ , X ₆ are arranged in this order and output to the outside as a series of data strings on the frequency axis.

  The control unit 311 distributes the input clock to each unit, instructs the operation start time to each unit, receives notification of the operation end time in each unit, and controls the entire DFT arithmetic unit 301.

  As shown in FIG. 6, the number of rearrangements of the twiddle factor W matrix in the DFT operation in the first embodiment is four times, which is about 1 / compared to the number of rearrangements seven times of the twiddle factor W matrix in the conventional example shown in FIG. 2. Furthermore, the twiddle factor selection processing unit according to the first embodiment has a feature that it can be configured by one for two of the conventional examples.

Further, the input rearrangement processing unit 305 in the configuration diagram 3 of the first embodiment is a new one not shown in the configuration diagram 1 of the conventional example, but the rearrangement of the input data is fixed and the hardware is fixed. Since it is performed by connection, the signal processing delay time is negligibly small.
(Example 2)
In the second embodiment, an inverse discrete Fourier transform (hereinafter referred to as IDFT: Inverse Discrete Fourier Transform) is performed for a case where the number of samples on the frequency axis of the input data sequence is seven.

In the IDFT according to the second embodiment, the input data string is the sample data string X ₀ , X ₁ ,... X ₆ on the frequency axis, and the output data is the sample data string x ₀ , x ₁ ,. · x _6, and the relationship between the input and output as compared with the DFT shown in example 1 is reversed.

Further, the twiddle factor in the IDFT is an inverse number W ^{−1 with} respect to W in the case of DFT, and the matrix is a matrix composed of elements of W ^−m (hereinafter referred to as W ⁻¹ matrix).

Further, the product of the sample data string X ₀ , X ₁ ,... X ₆ on the frequency axis and the data string of the W ⁻¹ matrix and the addition result are multiplied by (1 / N), and the data on the time axis The columns x ₀ , x ₁ ,... X ₆ are obtained. N is the number of data, and N = 7 in the second embodiment.

  This basic relationship is expressed by equation (5).

（５）式はマトリクスで表すとN＝７の場合（６）式となる。

When the expression (5) is expressed in a matrix, the expression (6) is obtained when N = 7.

図７にＩＤＦＴ演算装置構成、図８に回転因子の逆数格納メモリテーブル、図９にＩＤＦＴ演算タイムチャートをそれぞれ示す。

FIG. 7 shows the configuration of the IDFT arithmetic unit, FIG. 8 shows the reciprocal storage table of the twiddle factor, and FIG.

  In FIG. 7, the same components as those in FIG. As specific to the second embodiment, reference numeral 701 denotes an IDFT arithmetic unit, 702 denotes a reciprocal storage memory of a twiddle factor, 703 denotes an output data storage register unit, and 704 denotes a control unit.

The input rearrangement processing unit 305 in FIG. 7 performs the rearrangement of the order of the input data strings x ₀ , x ₁ ,..., X ₆ on the time axis in FIG. In the second embodiment, the rearrangement of the order of the input data strings X ₀ , X ₁ ,..., X ₆ on the frequency axis is performed by the same method with reference to FIG.

  In FIG. 8, D801 represents the address number of the reciprocal storage table of twiddle factors, and D802 represents twiddle factor data.

In FIG. 9, D901 is the input clock, D902 is the input data string, D903 is the data string in which the input data string is rearranged, D904 is the data string of the first twiddle factor processing unit, and D905 is the first complex multiplication. A data string of A and the output of the complex addition A and the result x ₀ , D906 are the data string of the second twiddle factor processing unit, D907 is the data string of the second complex multiplication A and the complex addition A data stream and the output x ₆ in operation and the operation result of complex addition _B, D 909 is the data row of rotating factor treatment of operational third operation the output x ₁ of the operation _result, D908 arithmetic second complex multiplication B of , D910 is data string of operations third complex multiplication a and the output x _2, D911 calculation and calculation result of complex additions a data sequence of operations third complex multiplication B and complex Calculation output x ₅ of the operation with the operation result of _B, D912 arithmetic fourth rotation factor processing unit of the data sequence, D913 is data string of calculation fourth complex multiplication A and the calculation and the calculation result of complex additions A output x ₃ and D 914 respectively indicate the data string of the complex multiplication B for the fourth calculation, and the output x ₄ of the calculation of the complex addition B and the calculation result.

In the formula (6) showing the basics of IDFT, the present invention is equivalent to the seventh row by reversing the column order of the second row to the seventh column of the second row of the twiddle factor W ⁻¹ matrix. When the column order of ˜7 columns is reversed, the property becomes equal to the sixth row, and when the column order of the second to seventh columns of the fourth row is reversed, the property becomes equal to the fifth row.

In the second embodiment, X ₀ , X ₁ , X ₂ , X ₃ , X ₄ , X ₅ , X ₆ of the input data string D902 are arranged as they are in the second embodiment, and two rows of the W ⁻¹ matrix are used. ^W eyes ^{D906 0, W -1, W -2} , W -3, W -4, W -5, and sequence to obtain the output _{x 1} calculates the product-sum of the ^{W -6,} the input data sequence 2 The column order is rearranged after the items, and X ₀ , X ₆ , X ₅ , X ₄ , X ₃ , X ₂ , X ₁ of D 903 and W ⁰ of the second row D 906 of the same W ⁻¹ matrix as described above. , W ⁻¹ , W ⁻² , W ⁻³ , W ⁻⁴ , W ⁻⁵ , and W ⁻⁶ are used in common, and the product / addition operation and the sequence for obtaining x ₆ are operated in parallel.

Similarly, the output x ₂ and the output x ₅ commonly use the third row W ⁰ , W ⁻² , W ⁻⁴ , W ⁻⁶ , W ⁻¹ , W ⁻³ , and W ⁻⁵ of the W− ¹ matrix. , It can be calculated by parallel operation of the series of product / addition operation.

Output _{x 4} and the output _{x 3} in the same ^manner, the common ^{W -1 W} 0 of the matrix of 4 row ^{D909, W -3, W -6,} W -2, W -5, W -1, W -4 It can be used for parallel operation of series of product / addition operations.

In addition, the input data string in the second term on the right side of equation (6), X ₀ , X ₁ ,..., X ₆ are sample values on the frequency axis, which are complex numbers having amplitude and phase. Each element W ^-m of the term W ^-1 matrix is a complex number because it is the reciprocal of W according to equation (2), and the product of the right-hand side and the addition are complex numbers.

  The IDFT calculation of the second embodiment will be described with reference to FIGS. 7, 8, and 9, focusing on the DFT time chart of FIG.

X ₀ , X ₁ ,..., X ₆ of the frequency axis sample input data D 902 input to the IDFT arithmetic unit 701 are temporarily stored in the input data storage register unit 304. The clock D901 input in combination with the sample data on the time axis is distributed to each unit in the IDFT arithmetic unit 901 via the control unit 704.

The input data string temporarily stored in the input data storage register unit 304 is sequentially read out in synchronization with the clock D901 to become D902, and each element X ₀ , X ₁ ,. to form an X _6.

As IDFT computation first, (6) for the ^{W 0} on the left side first row in the equation, since the rows 6 columns all have the same ^{W 0} line is not in the other, the _{X 0} only one row DFT Perform the operation. A DFT operation is performed by the twiddle factor selection processing unit 303, the complex operation A unit 306, the complex addition A unit 308, and the output data storage register unit 703 (including 1/7 times the operation).

For the IDFT calculation for obtaining x ₀ , the twiddle factor selection processing unit 303 generates the first row of the first term W ⁻¹ matrix on the right side of the equation (4), so that the W stored in the twiddle factor storage memory 702 is stored. The address ⁰ is designated and read D904. In the complex multiplication A unit 306, the complex multiplication of each term of the input data string D902, x ₀ , x ₁ ,..., X ₆ and D904 of the input data string D902 temporarily stored in the input data storage register unit 304 is performed by the clock D901. sequentially performed in accordance with, seven sections D905 multiplication results are complex addition in the complex adder a 308, is 1/7 times the output data storage register unit 703 are stored as output data x _0.

Next, as the operation second, (6) use the ^{W -1} second row of the matrix of commonly performed simultaneously in parallel the IDFT computation of equation (6) left side second row _{x 1} and 6 row _{x 6} .

For IDFT calculation for obtaining the x _1, twiddle factor selection processing section 303, (4) for generating a right second line of the first term W matrix, stored in the inverse storage memory 702 of the rotation factors W The addresses of ⁰ , W ⁻¹ , W ⁻² ,... W ⁻⁶ are sequentially designated and read according to the clock D901 to obtain seven data strings D906 of W− ¹ . In the complex multiplication A unit 306, complex multiplication of each term of the input data string D902 and each term of W- ¹ of D906 is sequentially performed according to the clock D901, and the seven terms D907 of the multiplication result are the complex addition A unit 306. in the complex adder is stored is 1/7 times the output data storage register unit 703 as output data x _1.

For IDFT calculation for obtaining the x _6, the rotation factor selecting section 303 uses the seven data string D906 having the same ^{W -1} as when operation of the _{x 1} in common.

The IDFT calculation for obtaining x ₆ is the product of the seventh row of the W ⁻¹ matrix and the first column of the x matrix on the right side of equation (6), but the seventh row of the W ⁻¹ matrix is the second row 2. The order of the columns after the column is reversed.

Hence, DFT operation to obtain the x ₆ is, W ^-1 and the second row of the matrix is equal to the product and the addition of each element of those interchanged up and down the second row and subsequent rows order x matrix.

Each item of the input data string D902, X ₀ , X ₁ ,..., X ₆ , in the input rearrangement processing unit 305, the column order after the second column of D902 is replaced by X ₀ , X ₆ , X ₅ ,..., X ₁ .

The complex multiplication B unit 307 sequentially performs complex multiplication of each term of D903 and each term of D906 according to the clock D901, and the seven terms of the multiplication result are complex-added by the complex addition B unit 309, and the output data storage register unit 703 in the 1/7 times it is stored as output data _{x 6.}

Similarly, x ₂ and x ₅ are calculated in parallel in the third DFT calculation, and x ₃ and x ₄ are calculated in parallel in the _fourth calculation and stored in the output data storage register unit 703 as output data.

The IDFT calculation results stored in the output data storage register unit 703 are stored in the data x ₀ , x ₁ , x ₆ , x ₂ , x ₅ , x ₃ , x _{4 when} storage of the data x ₀ , x ₁ , x _{2 is completed.} , X ₃ , x ₄ , x ₅ , x ₆ are arranged in this order, and are output to the outside as a series of data strings on the time axis.

  The control unit 704 distributes the input clock to each unit, instructs the operation start time to each unit, receives notification of the operation end time in each unit, and controls the entire IDFT arithmetic unit 701.

As shown in FIG. 9, the number of rearrangements of the twiddle factor W- ¹ matrix in the IDFT calculation in the second embodiment is four times, which is about the number of rearrangements of the twiddle factor W matrix in the conventional example shown in FIG. 1/2. Furthermore, the twiddle factor selection processing unit according to the second embodiment has a feature that can be configured by one for two of the conventional examples.

The input rearrangement processing unit 305 in the configuration diagram of the second embodiment shown in FIG. 7 is a new one not shown in the configuration diagram of the conventional example, but the rearrangement of input data is fixed and the hardware is fixed. Since it is performed by connection, the signal processing delay time is negligibly small.
(Appendix 1)
First storage means for storing N (N is a positive integer) input data;
Second storage means for storing N twiddle factors;
A product of each of the N input data sequentially read from the first storage means and each of the N twiddle factor data read in a predetermined order from the second storage means; First computing means for adding the products;
Reordering means for reversing the order from the second to the Nth order for the N input data of the first storage means;
The product of each of the N input data read out in order from the rearrangement means and each of the N pieces of twiddle factor data read out in a predetermined order from the second storage means, and the product A second computing means for adding
Third storage means for storing data obtained by the first calculation means and the second calculation means;
When the number of data stored in the third storage means reaches N pieces, the N pieces of data are arranged in a predetermined order and output. Control means for causing
A discrete Fourier transform device comprising:
(Appendix 2)
The first and second computing means are:
When the first row in the twiddle factor matrix composed of N rows and N columns of discrete Fourier transform is used as the twiddle factor data, the first column to the Nth column are read in order and one of the first or second calculation means. Perform the operation with
When the number of input data N is an odd number, when the 2nd to (N-1) / 2 + 1th rows in the twiddle factor matrix are used, the first to Nth columns are sequentially read, respectively. And the arithmetic operation using the second arithmetic means in common,
When the number of input data N is an even number, when the second to (N / 2) th rows are used in the twiddle factor matrix, the first to Nth columns are read in order, respectively. When the (N / 2) + 1th row is used, the first column to the Nth column are read, and one of the first or second calculation units is used for calculation. I do,
The discrete Fourier transform device according to supplementary note 1, wherein:
(Appendix 3)
First storage means for storing N (N is a positive integer) input data;
Second storage means for storing reciprocals of N twiddle factors;
Each of the N pieces of input data read in order from the first storage means and each of the reciprocal data of the N twiddle factors read in a predetermined order from the second storage means A first computing means for adding the product and the product;
Reordering means for reversing the order from the second to the Nth order for the N input data of the first storage means;
A product of each of the N input data read in sequence from the rearranging means and each of the reciprocal data of the N twiddle factors read in a predetermined order from the second storage means; Second calculating means for adding the products;
Third storage means for storing 1 / N times the data obtained by the first calculation means and the second calculation means;
When the number of data stored in the third storage means reaches N pieces, the N pieces of data are arranged in a predetermined order and output. Control means for causing
A discrete Fourier inverse transform device characterized by comprising:
(Appendix 4)
The first and second computing means are:
When the first row in the inverse matrix of twiddle factors consisting of N rows and N columns of the discrete Fourier transform is used as the reciprocal data of the twiddle factors, the first to Nth columns are sequentially read out from the first to Nth columns. Perform computation on one of the two computing means,
When the number of input data N is an odd number, when the 2nd to (N-1) / 2 + 1th rows in the matrix of the reciprocal number of the twiddle factor are used, the first to Nth columns are sequentially read. Performing computation using the first and second computing means in common,
When the number of input data N is an even number, when the second to (N / 2) th rows in the reciprocal matrix of the twiddle factors are used, the first to Nth columns are read in order, respectively. When the (N / 2) + 1th row is used, the first to Nth columns are read out when the (N / 2) + 1th row is used. On the other hand,
4. The discrete Fourier inverse transform device according to appendix 3, wherein

It is a figure which shows a DFT arithmetic unit structure (conventional example). It is a figure which shows a DFT calculation time chart (conventional example). It is a figure which shows DFT arithmetic unit structure (Example 1). It is a figure which shows a twiddle factor storage memory table (Example 1). It is a figure which shows the function (Example 1) of an input data rearrangement process part. It is a figure which shows the DFT calculation time chart (Example 1). It is a figure which shows IDFT arithmetic unit structure (Example 2). It is a figure which shows the reciprocal number storage memory table (Example 2) of a twiddle factor. It is a figure which shows IDFT calculation time chart (Example 2).

Explanation of symbols

101 DFT Arithmetic Unit 102 Rotation Factor Storage Memory 103 Rotation Factor Selection Processing A Unit 104 Rotation Factor Selection Processing B Unit 105 Input Data Storage Register Unit 106 Complex Multiplication A Unit 107 Complex Addition A Unit 109 Complex Addition B Unit 110 Output Data Storage Register Unit 111 Control Unit 301 DFT Operation Unit 302 Rotation Factor Storage Memory 303 Rotation Factor Selection Processing Unit 304 Input Data Storage Register Unit 305 Input Data Rearrangement Processing Unit 306 Complex Multiplication A Unit 307 Complex Multiplication B Unit 308 is Complex Addition B Unit 310 Output Data Storage register unit 311 Control unit 701 IDFT arithmetic unit 702 Rotation factor reciprocal storage memory 703 Output data storage register unit 704 Control unit

Claims (3)

First storage means for storing N (N is a positive integer) input data;
Second storage means for storing N twiddle factors;
A product of each of the N input data sequentially read from the first storage means and each of the N twiddle factor data read in a predetermined order from the second storage means; First computing means for adding the products;
Reordering means for reversing the order from the second to the Nth order for the N input data of the first storage means;
The product of each of the N input data read out in order from the rearrangement means and each of the N pieces of twiddle factor data read out in a predetermined order from the second storage means, and the product A second computing means for adding
Third storage means for storing data obtained by the first calculation means and the second calculation means;
When the number of data stored in the third storage means reaches N pieces, the N pieces of data are arranged in a predetermined order and output. Control means for causing
A discrete Fourier transform device comprising: The first and second computing means are:
When the first row in the twiddle factor matrix composed of N rows and N columns of discrete Fourier transform is used as the twiddle factor data, the first column to the Nth column are read in order and one of the first or second calculation means. Perform the operation with
When the number of input data N is an odd number, when the 2nd to (N-1) / 2 + 1th rows in the twiddle factor matrix are used, the first to Nth columns are sequentially read, respectively. And the arithmetic operation using the second arithmetic means in common,
When the number of input data N is an even number, when the second to (N / 2) th rows are used in the twiddle factor matrix, the first to Nth columns are read in order, respectively. When the (N / 2) + 1th row is used, the first column to the Nth column are read, and one of the first or second calculation units is used for calculation. I do,
The discrete Fourier transform apparatus according to claim 1. First storage means for storing N (N is a positive integer) input data;
Second storage means for storing reciprocals of N twiddle factors;
Each of the N pieces of input data read in order from the first storage means and each of the reciprocal data of the N twiddle factors read in a predetermined order from the second storage means A first computing means for adding the product and the product;
Reordering means for reversing the order from the second to the Nth order for the N input data of the first storage means;
A product of each of the N input data read in sequence from the rearranging means and each of the reciprocal data of the N twiddle factors read in a predetermined order from the second storage means; Second calculating means for adding the products;
Third storage means for storing 1 / N times the data obtained by the first calculation means and the second calculation means;
When the number of data stored in the third storage means reaches N pieces, the N pieces of data are arranged in a predetermined order and output. Control means for causing
A discrete Fourier inverse transform device characterized by comprising:

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