JP2008052478A - Clock stop detection circuit and clock stop detection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock stop detection circuit and clock stop detection method that does not require any external component of an IC to be inspected and is capable of suppressing increase in component mounting area and product price. <P>SOLUTION: In the clock stop detection circuit, an IC 7 comprises: an emergency internal register 2 for storing data to output during clock stop; a register selection flip-flop 4 for selecting either an internal register 1 or the emergency register 2 based on whether a clock is in operation or in a stop state upon occurrence of a register read request signal (a); and an output data switching circuit 5 for outputting a value of the register selected by the register selection flip-flop 4 to a general purpose bus 6. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock stop detection circuit and a clock stop detection method for detecting a stop of an internal clock of an IC.

FIG. 2 is a block diagram of a clock stop circuit showing the first prior art.
In FIG. 2, 111 is an IC to be inspected, 112 is a mono multivibrator, 113 is a resistor, 114 is a capacitor, and 115 is a clock stop monitoring circuit.
Hereinafter, the configuration and operation of the clock stop circuit according to the first prior art will be described with reference to FIG.
In the conventional clock stop detection circuit, the mono multivibrator 112 is installed outside the IC 111 to be inspected, and the internal clock of the IC 111 to be inspected or a signal generated by the same clock is generated continuously when normal. The mono multivibrator 112 is activated by using this, and when the abnormality occurs, the signal is stopped, so that the output of the mono multivibrator 112 is inverted after the time constant by the resistor 113 and the capacitor 114, thereby the IC 111 to be inspected. (See, for example, Patent Document 1).

FIG. 3 is a block diagram of a clock stop circuit showing the second prior art.
In FIG. 3, 121 is an IC to be inspected, 122 is a flip-flop, and 123 is a clock stop monitoring circuit.
Hereinafter, the configuration and operation of the clock stop circuit according to the second prior art will be described with reference to FIG.
A flip-flop 122 is installed outside the IC 121 to be inspected, and the flip-flop 122 is set from the outside. However, when an abnormality occurs, the above-mentioned signal is stopped and the flip-flop 122 remains set, thereby detecting the clock stop of the IC 121 to be inspected.

Thus, the conventional clock stop detection circuit detects the clock stop by installing components and wiring outside the IC to be inspected.
Japanese Patent Laid-Open No. 10-283058 (FIG. 2)

However, the clock stop detection circuit according to the prior art has a problem that the component mounting area increases and the product price increases because components and wiring are installed outside the IC to be inspected.
The present invention has been made in view of such problems, and does not require an external component of an IC to be inspected, and can suppress an increase in component mounting area and an increase in product price. An object of the present invention is to provide a clock stop detection method.

  In order to solve the above problem, the invention according to claim 1 includes an internal clock generation circuit that generates a clock, an internal register, and a general-purpose bus, and the value of the internal register is determined by an external internal register read request signal. In the IC clock stop detection circuit for outputting to the general-purpose bus, the IC includes an internal register for abnormal time storing data to be output when the clock is stopped, and the internal register read request signal when the internal register read request signal is generated. A register selection flip-flop that selects either the internal register or the abnormality register based on whether the clock is operating or stopped, and the value of the register selected by the register selection flip-flop And an output data switching circuit for outputting to the general-purpose bus.

  The invention according to claim 2 further includes an internal clock generation circuit that generates a clock, an internal register, and a general-purpose bus, and the value of the internal register is transferred to the general-purpose bus by an external internal register read request signal. In the clock stop detection method of the IC to be output, the step of storing the data to be output when the clock is stopped in the error register, and whether the clock is operating or stopped when the internal register read request signal is generated And selecting one of the internal register and the abnormal-time register on the basis of the state, and outputting the value of the selected register to the general-purpose bus.

  According to the first aspect of the present invention, it is possible to obtain a clock stop detection circuit that can delete external parts and wirings that have been conventionally required, reduce the component mounting area, and suppress an increase in product price. it can.

  According to the second aspect of the present invention, there is obtained a clock stop detection method capable of deleting external components and wirings that have been conventionally required, reducing the component mounting area, and suppressing an increase in product price. be able to.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a clock stop detection circuit showing the present invention.
In FIG. 1, 1 is an internal register, 2 is an error register, 3 is an internal clock generation circuit, 4 is a register selection flip-flop, 5 is an output data switching circuit, 6 is a general-purpose bus, and 7 is an IC to be tested. , 8 are clock stop monitoring circuits. Further, a is an internal register read request signal.
The clock stop detection circuit of the present invention is different from the prior art in that when an internal register read request is generated from the outside, the internal register 1 or an abnormality is detected depending on whether the internal clock signal of the IC 7 to be inspected is operating or stopped. The IC 7 includes a register selection flip-flop 4 for selecting the time register 2 and an output data switching circuit 5 for outputting the value of the register selected by the register selection flip-flop 4 to the general-purpose bus 6. Is a point.
Hereinafter, the operation of the clock stop detection circuit of the present invention will be described with reference to FIG.
When the internal register read request signal a is not generated, the CLR input of the register selection flip-flop 4 is valid, so that the Q output of the register selection flip-flop 4 becomes low and the general-purpose bus 6 has The value of the error register 2 is output. However, since the clock stop monitoring circuit 8 does not read the general-purpose bus 6 at this time, the contents output to the general-purpose bus 6 have no meaning.
When the internal clock is operating, when the internal register read request signal a is generated, the CLR input of the register selection flip-flop 4 becomes invalid, and the Q output of the register selection flip-flop 4 becomes high by the internal clock, The value of the internal register 1 is output to the general-purpose bus 6.
When the internal clock is stopped, even if the internal register read request signal a is generated and the CLR input of the register selection flip-flop 4 becomes invalid, the clock is not input, so the Q output of the register selection flip-flop 4 is It remains low and the value of the error register 2 is output to the general-purpose bus 6. Thus, the external clock stop monitoring circuit 8 can recognize that the internal clock of the IC 7 to be inspected has stopped.
The internal register read request signal “a” and the general-purpose bus 6 are already built in the IC 7, and even if a clock stop detection circuit is added, it is not necessary to prepare a dedicated wiring outside the IC 7.

  The present invention is suitable for a motion field network, and in particular, high reliability can be realized at low cost by being incorporated in an ASIC.

Configuration diagram of a clock stop detection circuit showing the present invention Configuration of clock stop circuit showing the first prior art Configuration diagram of clock stop circuit showing second prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Internal register 2 Abnormality register 3 Internal clock generation circuit 4 Flip-flop for register selection 5 Output data switching circuit 6 General-purpose bus 7, 111, 121 IC to be inspected
112 Mono multivibrator 113 Resistor 114 Capacitor 8, 115, 123 Clock stop monitoring circuit 122 Flip-flop a Internal register read request signal

Claims (2)

It has an internal clock generation circuit (3) for generating a clock, an internal register (1), and a general-purpose bus (6). The value of the internal register (1) is set by an external internal register read request signal (a). In the clock stop detection circuit of the IC (7) that outputs to the general-purpose bus (6),
The IC (7)
An internal register for abnormal time (2) for storing data to be output when the clock is stopped;
A register that selects either the internal register (1) or the abnormal time register (2) based on whether the clock is operating or stopped when the internal register read request signal (a) is generated A selection flip-flop (4);
An output data switching circuit (5) for outputting the value of the register selected by the register selection flip-flop (4) to the general-purpose bus (6). It has an internal clock generation circuit (3) for generating a clock, an internal register (1), and a general-purpose bus (6). The value of the internal register (1) is set by an external internal register read request signal (a). In the clock stop detection method of the IC (7) that outputs to the general-purpose bus (6),
Storing data to be output when the clock is stopped in the error register (2);
Selecting either the internal register (1) or the error register (2) based on whether the clock is operating or stopped when the internal register read request signal (a) is generated When,
And outputting the value of the selected register to the general-purpose bus (6).

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