JP2008047882A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow individual identifiers to be easily given to individual semiconductor devices capable of wireless communications. <P>SOLUTION: The present invention is related to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a thin film transistor; a first interlayer insulating film that is provided over the thin film transistor; a first electrode that is provided over the first interlayer insulating film and is electrically connected to one of a source region and a drain region; a second electrode that is electrically connected to the other of the source region and the drain region; a second interlayer insulating film that is formed over the first interlayer insulating film, the first electrode, and the second electrode; a first wiring portion that is provided over the second interlayer insulating film and is electrically connected to one of the first electrode and the second electrode; and a second wiring portion that is provided over the second interlayer insulating film and is not electrically connected to the other of the first electrode and the second electrode. The second wiring portion is not electrically connected to the other of the first electrode and the second electrode by a separation region formed in the second interlayer insulating film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of communicating by non-contact means such as wireless communication and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device formed on an insulating substrate such as glass or plastic and a method for manufacturing the same.

  With the development of computer technology and the improvement of image recognition technology, information recognition methods using media such as barcodes have become widespread and are used for product data recognition and the like. In the future, it is expected that a larger amount of information recognition will be required. On the other hand, in the case of information recognition by bar code, there are drawbacks that the bar code reader requires contact with the bar code and that the amount of information that can be recorded on the bar code is small. Capacity increase is desired.

  In response to such demands, semiconductor devices (also referred to as ID chips, IC chips, IC tags, ID tags, wireless chips, and RFID) capable of wireless communication using ICs have been developed in recent years. In such a semiconductor device, information stored in a memory circuit in the IC is read using non-contact means, generally wireless means. The practical use of such a semiconductor device makes it possible to simplify product distribution, reduce costs, and ensure high security.

  An outline of an individual authentication system using a semiconductor device capable of wireless communication using the IC will be described with reference to FIGS. 2, 3, and 4A to 4B. FIG. 2 is a diagram showing an overview of an individual authentication system for the purpose of recognizing bag individual information without contact.

  A semiconductor device 221 that stores specific individual information is attached to or embedded in a bag 224. A signal is transmitted to the semiconductor device 221 from an antenna unit 222 electrically connected to an interrogator (also referred to as a reader / writer) 223. When the signal is received, the semiconductor device 221 transmits individual information held by the semiconductor device to the antenna unit 222. The antenna unit 222 sends the transmitted individual information to the interrogator 223, and the interrogator 223 determines the individual information. In this way, the interrogator 223 can recognize the individual information of the bag 224. Further, by using this system, it is possible to carry out logistics management, aggregation, removal of counterfeit products, and the like.

  As such a semiconductor device, for example, there is one having a configuration shown in FIG. Such a semiconductor device 200 includes an antenna circuit 201, a rectifier circuit 202, a stable power supply circuit 203, an amplifier 208, a demodulation circuit 213, a logic circuit 209, a memory control circuit 212, a memory circuit 211, a logic circuit 207, an amplifier 206, and a modulation circuit 205. have.

  For example, the antenna circuit 201 includes an antenna coil 241 and a capacitor 242 (see FIG. 4A). For example, the rectifier circuit 202 includes diodes 243 and 244 and a capacitor 245 (see FIG. 4B).

  The operation of a semiconductor device capable of wireless communication using such an IC will be described below. The radio signal received by the antenna circuit 201 is half-wave rectified by the diodes 243 and 244 and smoothed by the capacitor 245. Since the smoothed voltage includes a plurality of ripples, the voltage is stabilized by the stable power supply circuit 203, and the stabilized voltage is converted into the demodulation circuit 213, the modulation circuit 205, the amplifier 206, the logic circuit 207, the amplifier 208, The data is supplied to the logic circuit 209, the memory circuit 211, and the memory control circuit 212.

  On the other hand, a signal received by the antenna circuit 201 is input to the logic circuit 209 through the amplifier 208 as a clock signal. The signal input from the antenna coil 241 is demodulated by the demodulation circuit 213 and input to the logic circuit 209 as data.

  In the logic circuit 209, the input data is decoded. Since the interrogator 223 encodes and transmits the data, the logic circuit 209 decodes the data. The decoded data is sent to the memory control circuit 212, and information stored in the memory circuit 211 is read out accordingly.

  The memory circuit 211 needs to be a nonvolatile memory circuit that can be held even when the power is turned off, and a ROM (Read Only Memory) or the like is used (see Patent Document 1).

Signals transmitted and received include 125 kHz, 13.56 MHz, 915 MHz, 2.45 GHz, and the like, and standards are set by ISO and the like. Standards are also set for the modulation / demodulation methods in transmission and reception.
Japanese Patent No. 3578057

  In order to manufacture a semiconductor device capable of wireless communication using the IC as described above, it was necessary to form a nonvolatile memory circuit, for example, a mask ROM as described above.

  However, since a mask ROM (hereinafter also simply referred to as “ROM”) cannot perform data writing except during manufacture of the semiconductor device, data is also created at the same time as the mask ROM is produced during manufacture of the semiconductor device.

  Unique data such as an ID number of each semiconductor device is stored in the ROM. Unique data such as an ID number is different for each semiconductor device. However, since a ROM is generally manufactured using photolithography, a photomask must be made each time in order to make unique data such as an ID number different in each semiconductor device. Therefore, if unique data such as different ID numbers are created, both the production cost and the creation work are burdened.

  The ID number is a number for identifying an individual semiconductor device, and is different for each individual semiconductor device.

  Accordingly, the present invention provides a semiconductor device capable of wireless communication using an IC, in which a ROM having unique data such as different ID numbers is formed, and a method for manufacturing such a semiconductor device.

  In order to solve the above problems, in the present invention, in a semiconductor device capable of communication by wireless communication, a wiring material is melted in an electrolytic solution and a voltage is applied to melt the wiring material and cut off an electrical connection. In addition, different data is written to each semiconductor device by forming a wiring that maintains electrical connection.

  More specifically, an electrode or wiring that is electrically connected to an active layer of a TFT that forms a memory cell array of a memory circuit in a semiconductor device is immersed in an electrolytic solution to interrupt the electrical connection. By applying a voltage to the electrode, the electrode or wiring is dissolved. As a result, it is possible to make a separate electrode or wiring in which the electrical connection is interrupted and an electrode or wiring in which the electrical connection is maintained.

  In the present invention, the data different from the above semiconductor device is unique data such as an ID number corresponding to each semiconductor device.

  In a semiconductor device (also referred to as an ID chip, an IC chip, an IC tag, an ID tag, a wireless chip, and an RFID) that can communicate by wireless communication according to the present invention, a ROM and a logic circuit are formed, and a thin film transistor (Thin Film Transistor ( TFT)).

  The present invention includes a thin film transistor having a channel formation region, an island-like semiconductor film having a source region or a drain region, a gate insulating film, and a gate electrode on a substrate, and a first interlayer insulating film on the thin film transistor A first electrode formed on the first interlayer insulating film and electrically connected to one of the source region or the drain region; and formed on the first interlayer insulating film, the source region Or a second electrode electrically connected to the other of the drain region, the first interlayer insulating film, the first electrode, and a second interlayer insulating film formed on the second electrode; A first wiring formed on the second interlayer insulating film, electrically connected to one of the first electrode or the second electrode, and formed on the second interlayer insulating film; Of the first electrode or the second electrode And the second wiring and the other of the first electrode and the second electrode are divided regions formed in the second interlayer insulating film. Thus, the semiconductor device is not electrically connected.

  In the present invention, an island-shaped semiconductor film, a gate insulating film, and a gate electrode are formed over a substrate, an impurity imparting one conductivity is added to the island-shaped semiconductor film, and the island-shaped semiconductor film is added. Forming a channel forming region, a source region or a drain region, covering the island-shaped semiconductor film, the gate insulating film, and the gate electrode, forming a first interlayer insulating film, and over the first interlayer insulating film Forming a first electrode electrically connected to one of the source region and the drain region, and a second electrode electrically connected to the other of the source region and the drain region on the first interlayer insulating film. And forming a second interlayer insulating film covering the first interlayer insulating film, the first electrode, and the second electrode, and in the second interlayer insulating film, Forming a first contact hole reaching the first electrode; A second contact hole reaching the second electrode is formed in the second interlayer insulating film, the first electrode and the second electrode are immersed in an electrolytic solution, and the first electrode or the second electrode A voltage is applied to one of the electrodes to dissolve one of the first electrode or the second electrode to form a dividing region, and the first or second contact hole is formed on the second interlayer insulating film. A first wiring not electrically connected to one of the first electrode or the second electrode is formed in one of the first and second contacts, and the first or second contact is formed on the second interlayer insulating film. The present invention relates to a method for manufacturing a semiconductor device, wherein a second wiring electrically connected to the other of the first electrode or the second electrode is formed through the other of the holes.

  In the present invention, the thin film transistor is used in a nonvolatile memory circuit.

  The present invention provides a first channel formation region, a first island-shaped semiconductor film having a first source region or a drain region, a gate insulating film, and a first gate electrode on a substrate. A second thin film transistor having a second channel formation region, a second island-shaped semiconductor film having a second source region or a drain region, the gate insulating film, and a second gate electrode; The first interlayer insulating film and the first interlayer insulating film are formed on the first and second thin film transistors, and are electrically connected to one of the first source region and the drain region. A first electrode, a second electrode formed on the first interlayer insulating film and electrically connected to the other of the first source region or the drain region, and on the first interlayer insulating film Formed in the second A third electrode electrically connected to one of the source region and the drain region and the first electrode formed on the first interlayer insulating film and electrically connected to the other of the second source region and the drain region A fourth electrode, the first interlayer insulating film, the second interlayer insulating film formed on the first electrode to the fourth electrode, and the second interlayer insulating film; A first wiring electrically connected to the first electrode; a second wiring formed on the second interlayer insulating film and electrically connected to the second electrode; A third wiring formed on the second interlayer insulating film and not electrically connected to the third electrode; and formed on the second interlayer insulating film and electrically connected to the fourth electrode. A fourth wiring, and the third wiring and the third electrode are formed in the second interlayer insulating film. By dividing region, to a semiconductor device which is characterized in that not electrically connected.

  In the present invention, a first island-shaped semiconductor film, a second island-shaped semiconductor film, a gate insulating film, a first gate electrode, and a second gate electrode are formed on a substrate, and the first and second gate electrodes are formed. An impurity imparting one conductivity is added to the island-shaped semiconductor film, and a first channel formation region, a first source region or a drain region is added to the second island-shaped semiconductor film in the second island-shaped semiconductor film. A second channel formation region, a second source region or a drain region are formed in the island-shaped semiconductor film, and the first and second island-shaped semiconductor films, the gate insulating film, the first and second regions are formed. A first interlayer insulating film is formed to cover the gate electrode, and a first electrode electrically connected to one of the first source region or the drain region is formed on the first interlayer insulating film. And forming the first source region or the drain region on the first interlayer insulating film. Forming a second electrode that is electrically connected to the first electrode, and forming a third electrode that is electrically connected to one of the second source region and the drain region on the first interlayer insulating film. A fourth electrode electrically connected to the other of the second source region and the drain region is formed on the first interlayer insulating film, and the first interlayer insulating film, the first interlayer insulating film, A second interlayer insulating film is formed to cover the electrode to the fourth electrode, a first contact hole reaching the first electrode is formed in the second interlayer insulating film, and the second interlayer insulating film is formed. A second contact hole reaching the second electrode is formed in the insulating film, a third contact hole reaching the third electrode is formed in the second interlayer insulating film, and the second contact hole is formed. In the interlayer insulating film, a fourth contact hole reaching the fourth electrode is formed. The first to fourth electrodes are immersed in an electrolytic solution, a voltage is applied to the third electrode, the third electrode is dissolved to form a divided region, and the second interlayer insulating film is formed on the second interlayer insulating film. Forming a first wiring electrically connected to the first electrode via the first contact hole, and over the second interlayer insulating film via the second contact hole; Forming a second wiring electrically connected to the second electrode and electrically connecting to the third electrode in the third contact hole on the second interlayer insulating film Forming a third wiring not to be formed, and forming a fourth wiring electrically connected to the fourth electrode through the fourth contact hole on the second interlayer insulating film. The present invention relates to a method for manufacturing a semiconductor device.

  In the present invention, the first and second thin film transistors are used in a nonvolatile memory circuit.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  According to the present invention, it is possible to easily attach unique data such as a different ID number to each semiconductor device capable of wireless communication using an IC.

  Accordingly, the manufacturing time and manufacturing cost of a semiconductor device capable of wireless communication using an IC can be reduced.

[Embodiment 1]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

  This embodiment is shown in FIGS. 1, 5A to 5C, 6A to 6C, 7A to 7C, and 8A. Description will be made with reference to FIG. 8B, FIG. 9A to FIG. 9B, FIG. 10, FIG. 11, FIG. 12, FIG.

  FIG. 10 is a circuit diagram of a mask ROM, which includes a column decoder 15, a row decoder 16, a memory cell array 11 including n-channel TFTs 118 to 121, bit lines (data lines) 24 and 25, word lines W1 and W2, and a high voltage power source. (VDD) 22, low voltage power supply (VSS or GND) 23, column switches SW 1 to SW 4, address lines S 1 and S 2 controlled by the column decoder 15, output line 14 and control line 17, and high voltage power supply 22 electrically Wirings 27 and 28 are connected.

  FIG. 1 is a cross-sectional view of TFTs 118 and 119 included in the memory cell array 11 shown in FIG. The mask ROM shown in FIG. 1 represents a memory state depending on whether the wiring is electrically connected to the other of the source region or the drain region of the TFT forming the memory cell formed in the mask ROM. The TFT 118 is electrically connected to the wiring 27, and the TFT 119 is not electrically connected to the wiring 28.

  In FIG. 10, a 4-bit memory cell array is shown for simplification of explanation, but the nonvolatile memory circuit of the present invention is not limited to 4 bits.

  1 and 10, TFTs 118 to 121 are n-channel TFTs. As shown in FIG. 1, the TFT 118 includes a gate including an island-shaped semiconductor film 131 which is an active layer, a lower gate electrode 103a, and an upper gate electrode 103b. An electrode 103 is provided. The TFT 119 has a gate electrode 104 including an island-shaped semiconductor film 132 which is an active layer, a lower gate electrode 104a, and an upper gate electrode 104b.

  The gate electrodes 103 and 104 are electrically connected to the word line W1. Note that each of the TFTs 120 and 121 shown in FIG. 10 has the same structure as either the TFT 118 or 119, and the gate electrodes of the TFTs 120 and 121 are electrically connected to the word line W2.

  One of the source region or the drain region of the TFT 118 and one of the source region or the drain region of the TFT 120 are electrically connected to the bit line 24 (same as the wiring 175). One of the source region and the drain region of the TFT 119 and one of the source region and the drain region of the TFT 121 are electrically connected to the bit line 25 (same as the wiring 177).

  The other of the source region or the drain region of each of the TFTs 118 to 121 is electrically connected to the high voltage power source 22 via the wiring 27 (same as the wiring 176) or the wiring 28 (same as the wiring 178) as necessary. Is done. The storage state of the mask ROM is determined by whether or not it is electrically connected to the high voltage power supply 22.

  As shown in FIG. 1, the TFT 118 is formed on the base film 153 formed on the substrate 151. The TFT 118 includes an island-shaped semiconductor film 131, a gate insulating film 154, a gate electrode 103 including a lower gate electrode 103a and an upper gate electrode 103b, and sidewalls 171a and 171b. The island-shaped semiconductor film 131 includes a region 163 that is one of a source region and a drain region, a region 164 that is the other of the source region and the drain region, low-concentration impurity regions 162a and 162b, and a channel formation region 161.

  The TFT 119 is formed on the base film 153 formed on the substrate 151. The TFT 119 includes an island-shaped semiconductor film 132, a gate insulating film 154, a gate electrode 104 including a lower gate electrode 104a and an upper gate electrode 104b, and sidewalls 191a and 191b. The island-shaped semiconductor film 132 includes a region 184 that is one of a source region and a drain region, a region 183 that is the other of the source region and the drain region, low-concentration impurity regions 182a and 182b, and a channel formation region 181.

  In FIG. 1, the base film 153 is one layer, but the number of layers may be determined as necessary.

  A first interlayer insulating film 155 is formed on the TFTs 118 and 119, and a second interlayer insulating film 156 is further formed.

  Note that the TFTs 120 and 121 have the same cross-sectional structure as either the TFT 118 or the TFT 119.

  On the second interlayer insulating film 156, the electrode 109 electrically connected to the region 163, the electrode 113 electrically connected to the region 164, the electrode 114 electrically connected to the region 183, and the region 184 are electrically connected. An electrode 110 is formed. The electrode 109 and the electrode 113 function as a source electrode or a drain electrode of the TFT 118, respectively, and the electrode 114 and the electrode 110 function as a source electrode or a drain electrode of the TFT 119, respectively.

  However, the electrode 110 is partially etched by immersing it in an electrolyte while applying a voltage after forming the electrode 110. Accordingly, the electrode 110 is not electrically connected to the wiring 178 formed in a later process.

  A third interlayer insulating film 135 is formed on the second interlayer insulating film 156, the electrode 109, the electrode 113, the electrode 114, and the electrode 110.

  On the third interlayer insulating film 135, a wiring 175 (same as the bit line 24), a wiring 177 (same as the bit line 25), a wiring 176 (same as the wiring 27), and a wiring 178 (same as the wiring 28) are formed. ing. The wiring 175 (bit line 24) is electrically connected to the electrode 109, the wiring 177 (bit line 25) is electrically connected to the electrode 114, and the wiring 176 (wiring 27) is electrically connected to the electrode 113. It is connected to the. However, as described above, the wiring 178 (wiring 28) is disconnected from the electrode 110 and thus is not electrically connected.

  FIG. 11 is a cross-sectional view of a TFT of a logic circuit (also referred to as a logic circuit) that controls the mask ROM, and FIG. 12 is a circuit diagram thereof. The basic configuration of the logic circuit is a CMOS circuit in which an n-channel TFT and a p-channel TFT are complementarily connected. A column decoder and a row decoder described later are formed using such a CMOS circuit. 11 and 12 show an inverter using a CMOS circuit.

  11 and 12, the gate electrode 443 and the gate electrode 444 are formed using the same material and the same process. The wiring 407, the wiring 404, and the wiring 405 are formed using the same material and the same process. Further, the power supply line 431, the wiring 432, and the power supply line 433 are formed using the same material and the same process. However, it goes without saying that different processes and different materials may be used as required.

  As shown in FIG. 11, the n-channel TFT 411 is formed on the base film 453 formed on the substrate 451. The TFT 411 includes an island-shaped semiconductor film 412, which is an active layer, a gate insulating film 454, a gate electrode 443 including a lower gate electrode 443a and an upper gate electrode 443b, and sidewalls 471a and 471b. Note that although the base film 453 has one layer, the number of layers may be determined as necessary.

  In the island-shaped semiconductor film 412, a channel formation region 461, low-concentration impurity regions 462a and 462b, a region 463 that is one of a source region and a drain region, and a region 464 that is the other of the source region and the drain region are formed.

  A region 463 which is one of a source region and a drain region of the TFT 411 is connected to the wiring 404, and a region 464 which is the other of the source region and the drain region is connected to the wiring 407.

  The p-channel TFT 421 is formed on the base film 453 formed on the substrate 451. The TFT 421 includes an island-shaped semiconductor film 422 which is an active layer, a gate insulating film 454, a gate electrode 444 including a lower gate electrode 444a and an upper gate electrode 444b, and sidewalls 491a and 491b.

  In the island-shaped semiconductor film 422, a channel formation region 481, a region 484 that is one of a source region and a drain region, and a region 483 that is the other of the source region and the drain region are formed.

  A region 484 that is one of a source region and a drain region of the TFT 421 is connected to the wiring 405, and a region 483 that is the other of the source region and the drain region is connected to the wiring 407.

  Note that in this embodiment mode, the p-channel TFT 421 does not have a low-concentration impurity region, but a low-concentration impurity region may be formed if necessary.

  The wiring 407 electrically connects the region 464 which is the other of the source region and the drain region of the n-channel TFT 411 and the region 483 which is the other of the source region and the drain region of the p-channel TFT 421.

  A first interlayer insulating film 455 and a second interlayer insulating film 456 are formed on the TFTs 411 and 421.

  A wiring 404, a wiring 405, and a wiring 407 are formed over the second interlayer insulating film 456, and the wiring 404 is electrically connected to the region 463. The wiring 405 is electrically connected to the region 484. The wiring 407 is electrically connected to the region 464 and the region 483.

  A third interlayer insulating film 458 is formed over the second interlayer insulating film 456, the wiring 404, the wiring 405, and the wiring 407.

  A power supply line 431 electrically connected to the wiring 404, a power supply line 433 electrically connected to the wiring 405, and a wiring 432 electrically connected to the wiring 407 are formed over the third interlayer insulating film 458. . The wiring 432 is an output terminal of the inverter. A gate electrode 443 and a wiring 434 electrically connected to the gate electrode 444 are formed, and the wiring 434 serves as an input terminal of the inverter.

  The operation of the mask ROM having the present invention produced by the above steps will be described with reference to FIG. Note that the circuit configuration and operation are not limited to those described below as long as unique data such as an ID number stored or written in a memory cell can be read. In FIG. 10, for the sake of simplicity of explanation, the operation of the memory cell for 2 bits will be described using a 4-bit mask ROM as an example, but the number of bits and the operation of the mask ROM are limited to this description. It is not effective, but is effective even when the number of bits is larger, and the data of the memory cells of all bits are read.

  As shown in FIG. 10, the mask ROM having the present invention includes a column decoder 15, a row decoder 16, a memory cell array 11 including n-channel TFTs 118 to 121, bit lines (data lines) 24 and 25, word lines W1 and W2. , High voltage power supply (VDD) 22, low voltage power supply (VSS or GND) 23, column switches SW 1 to SW 4, address lines S 1 and S 2 controlled by the column decoder 15, output line 14 and control line 17. .

  First, when reading unique data such as an ID number stored or written in a 1-bit memory cell, an operation of precharging the potential of the low voltage power supply (VSS or GND) using 1/4 of the read time. Will be described.

  SW3 and SW4 are selected in the control line 17 for 1/4 of the readout time, and the bit lines (data lines) 24 and 25 are electrically connected to the low voltage power supply (VSS or GND) 23. Send. By doing so, the bit lines (data lines) 24 and 25 become low voltage power supplies (VSS or GND).

  At this time, the n-channel TFTs 118 to 121 are not selected in the word lines W1 and W2. Here, the selected state is that the source terminals and drain terminals of the n-channel TFTs 118 to 121 are electrically connected.

  Also, the address lines S1 and S2 controlled by the column decoder 15 do not have the column switches SW1 and SW2 selected. Here, the selected state is that the bit lines (data lines) 24 and 25 and the output line 14 are electrically connected.

  Note that the voltage to be precharged is precharged to a high voltage power supply (VDD) when precharged to a low voltage power supply (VSS or GND) as in the present invention due to differences in circuit configuration, method, logic, etc. There are various cases and cases where the precharge is performed to other generation voltages, and is not limited. In some cases, an optimum voltage may be selected.

  Next, an operation of reading unique data such as an ID number from the mask ROM having the present invention using the remaining 3/4 of the reading time will be described. Here, when the same voltage as the high voltage power supply (VDD) is output as the unique data such as the read ID number, the high is output when the same voltage as the low voltage power supply (VSS or GND) is output. And Note that whether the unique data such as the read ID number is high or low differs depending on the circuit configuration, method, logic, etc., and is not limited to this description.

  When the word line W1 is selected by the row decoder 16 and the address line S1 is selected by the column decoder 15, the n-channel TFT 118 is selected. Then, the source terminal and the drain terminal of the n-channel TFT 118 are electrically connected. That is, the bit line (data line) 24 and the high voltage power supply (VDD) 22 corresponding to the source terminal and the drain terminal of the n-channel TFT 118 are electrically connected. The bit line is charged to a voltage lower than the high voltage power supply (VDD) 22 by the threshold value of the n-channel TFT 118. Further, since the address line S1 is selected by the column decoder 15, the bit line (data line) 24 and the output line 14 are electrically connected. Here, since the bit line is charged to a voltage lower than the high voltage power supply (VDD) 22 by the threshold of the n-channel TFT 118, the output line 14 is also at the same potential. That is, a voltage lower than the high voltage power supply (VDD) 22 by the threshold value of the n-channel TFT 118 is output to the output line 14.

  Although not shown, a voltage lower than the high voltage power supply (VDD) 22 by the threshold value of the n-channel TFT 118 is passed through the amplifier, thereby outputting the same voltage as the high voltage power supply (VDD). Here, the amplifier is a circuit capable of increasing voltage or current, and may have a configuration in which two stages of inverters are connected, or a configuration using a comparator or the like.

  In this manner, high that is unique data such as an ID number stored or written in the n-channel TFT 118 is output to the output line 14.

  Similarly, when the word line W1 is selected by the row decoder 16 and the address line S2 is selected by the column decoder 15, the n-channel TFT 119 is selected. One terminal of the n-channel TFT 119 is not connected anywhere, but the bit line (data line) 25 which is the other terminal becomes the low voltage power supply (VSS or GND) 23 by the precharge operation. Yes. That is, one terminal and the other terminal of the n-channel TFT 119 have substantially the same voltage as the low voltage power supply (VSS or GND) 23. Further, since the address line S2 is selected by the column decoder 15, the bit line (data line) 25 and the output line 14 are electrically connected. That is, almost the same voltage as the low voltage power supply (VSS or GND) 23 is output to the output line 14.

  In this way, low, which is unique data such as an ID number stored or written in the n-channel TFT 119, is output to the output line.

  As described above, unique data such as an ID number stored or written in the mask ROM having the present invention can be read.

  5A to 5C, FIG. 6A to FIG. 6C, FIG. 7A to FIG. 7C, and FIG. Description will be made with reference to FIGS. 9A to 8B and FIGS. 9A to 9B.

  First, as shown in FIG. 5A, a base film 153 is formed over a substrate 151. As the substrate 151, for example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a stainless steel substrate, a so-called SOI (Silicon on Insulator) substrate in which a single crystal semiconductor layer is formed on an insulating surface, or the like is used. be able to. In addition, a substrate made of a plastic such as PET (poly (ethylene terephthalate)), PES (poly (ether sulfone)), or PEN (poly (ethyl naphthaphthalate)) or a flexible synthetic resin such as acrylic is used. It is also possible. Hereinafter, the case where a glass substrate is used as the substrate 151 will be described.

  The base film 153 is provided to prevent an alkali metal such as Na or an alkaline earth metal contained in the substrate 151 from diffusing into the semiconductor film and adversely affecting the characteristics of the semiconductor element. Therefore, an insulating film such as silicon nitride or silicon oxide containing nitrogen that can suppress diffusion of alkali metal or alkaline earth metal into the semiconductor film is used. In this embodiment mode, a silicon oxide film is formed with a plasma CVD method to have a thickness of 10 to 100 nm (preferably 20 to 70 nm, more preferably 50 nm), and a silicon oxide film containing nitrogen is 10 to 400 nm (preferably 50 to 300 nm). And more preferably 100 nm).

  Note that even though the base film 153 is a single layer of an insulating film such as silicon nitride, silicon oxide containing nitrogen, or silicon nitride containing oxygen, insulation such as silicon oxide, silicon nitride, silicon oxide containing nitrogen, or silicon nitride containing oxygen is used. A plurality of laminated films may be used. In addition, when using a substrate that contains alkali metal or alkaline earth metal, such as a glass substrate, stainless steel substrate, or plastic substrate, it is effective to provide a base film from the viewpoint of preventing impurity diffusion. However, when diffusion of impurities does not cause any problem, such as a quartz substrate, it is not necessarily provided.

  Next, the semiconductor film 101 is formed over the base film 153. The thickness of the semiconductor film 101 is 25 nm to 100 nm (preferably 30 nm to 80 nm). Note that the semiconductor film 101 may be an amorphous semiconductor or a polycrystalline semiconductor. As the semiconductor, not only silicon (Si) but also silicon germanium (SiGe) can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%. In this embodiment mode, an amorphous silicon film is formed as the semiconductor film 101 with a thickness of 66 nm.

  Next, as shown in FIG. 5B, the semiconductor film 101 is irradiated with a linear beam 111 from a laser irradiation apparatus to be crystallized.

  In the case of performing laser crystallization, heat treatment for 1 hour at 500 ° C. may be applied to the semiconductor film 101 in order to increase the resistance of the semiconductor film 101 to the laser before laser crystallization.

  For laser crystallization, a pulsed laser having an oscillation frequency of 10 MHz or more, preferably 80 MHz or more can be used as a continuous wave laser or a pseudo CW laser.

Specifically, as a continuous wave laser, Ar laser, Kr laser, CO ₂ laser, YAG laser, YVO ₄ laser, forsterite (Mg ₂ SiO ₄ ) laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, alexandrite laser, Ti: sapphire laser, helium cadmium laser, polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ as dopants Nd, Yb, Cr, Ti, Ho , Er, Tm, Ta, or the like, or a laser having a medium added with one or more of them.

As a pseudo CW laser, an Ar laser, a Kr laser, an excimer laser, a CO ₂ laser, a YAG laser, a Y ₂ O ₃ laser, a YVO can be used as long as it can oscillate a pulse having an oscillation frequency of 10 MHz or more, preferably 80 MHz or more. ₄ laser, forsterite (Mg ₂ SiO ₄ ) laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, alexandrite laser, Ti: sapphire laser, copper vapor laser or gold vapor laser, polycrystalline (ceramic) YAG, Y ₂ A pulse like a laser in which one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta are added as dopants to O ₃ , YVO ₄ , YAlO ₃ , and GdVO ₄ as a medium. An oscillation laser can be used.

  Such a pulsed laser has an effect equivalent to that of a continuous wave laser as the oscillation frequency is increased.

For example, when a solid-state laser capable of continuous oscillation is used, a crystal having a large grain size can be obtained by irradiating laser light of second to fourth harmonics. Typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of a YAG laser (fundamental wave 1064 nm). For example, laser light emitted from a continuous wave YAG laser is converted into a harmonic by a non-linear optical element, and irradiated to the semiconductor film 604. Energy density may be about 0.01 to 100 MW / cm ² (preferably 0.1~10MW / cm ^2). Irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta, a laser that uses one or a plurality of types added as a medium, Ar laser, Kr laser, or Ti: sapphire laser It is also possible to cause pulse oscillation by performing Q switch operation, mode synchronization, and the like. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

  Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, the output is greatly improved.

  Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction.

  By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion.

  By irradiating the semiconductor film 101 with the laser light, the crystalline semiconductor film 102 with higher crystallinity is formed.

  Next, as illustrated in FIG. 5C, island-shaped semiconductor films 131 and 132 are formed using the crystalline semiconductor film 102. The island-like semiconductor films 131 and 132 become active layers of TFTs formed in the subsequent processes.

  Note that in this embodiment, the case where a glass substrate is used as the substrate 151 is described; however, in the case where an SOI substrate is used as the substrate 151, the single crystal semiconductor layer is formed into an island shape, and the active layer of the TFT And it is sufficient.

Next, impurities for threshold control are introduced into the island-shaped semiconductor films 131 and 132. In this embodiment mode, boron (B) is introduced into the island-shaped semiconductor films 131 and 132 by doping with diborane (B ₂ H ₆ ).

  Next, a gate insulating film 154 is formed over the island-shaped semiconductor films 131 and 132. For the gate insulating film 154, for example, silicon oxide having a thickness of 10 to 110 nm, silicon nitride, silicon oxide containing nitrogen, or the like can be used. As a film formation method, a plasma CVD method, a sputtering method, or the like can be used. In this embodiment, the gate insulating film 154 is formed using a silicon oxide film containing nitrogen which is formed to a thickness of 20 nm by a plasma CVD method.

  Next, the first conductive film 115 and the second conductive film 116 are formed over the gate insulating film 154 (see FIG. 6A).

  As the first conductive film 115 and the second conductive film 116, an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), and aluminum (Al), or the above element is used. An alloy material or a compound material having a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus (P) may be used.

  In this embodiment, a tantalum nitride film is formed as the first conductive film 115 with a thickness of 10 to 50 nm, for example, 30 nm, and a tungsten (W) film is formed as the second conductive film 116 with a thickness of 200 to 400 nm. For example, a stacked film formed with a film thickness of 370 nm is formed.

  Next, the first conductive film 115 and the second conductive film 116 are etched to form the lower gate electrodes 103 a and 104 a from the first conductive film 115 and the upper gate electrodes 103 b and 104 b from the second conductive film 116. . Thus, the gate electrode 103 having the lower gate electrode 103a and the upper gate electrode 103b and the gate electrode 104 having the lower gate electrode 104a and the upper gate electrode 104b are formed (see FIG. 6B). However, the gate electrodes 103 and 104 may be a single layer film instead of a laminated film.

  The gate electrodes 103 and 104 may be formed as part of the gate wiring, or a gate wiring may be formed separately and the gate electrodes 103 and 104 may be connected to the gate wiring.

  Next, an impurity imparting one conductivity is added to the island-shaped semiconductor films 131 and 132. As an impurity imparting one conductivity, phosphorus (P) or arsenic (As) may be used as long as it is an impurity imparting n-type conductivity. Further, boron (B) may be used as long as it is an impurity imparting p-type.

In this embodiment, first, as a first addition step, an impurity imparting n-type conductivity is added to the island-shaped semiconductor films 131 and 132 (see FIG. 6C). Specifically, phosphorous (P) is applied using phosphine (PH ₃ ), the applied voltage is 40 to 120 keV, and the dose is 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ^−2. Introduce into. In this embodiment mode, phosphorus is added into the island-shaped semiconductor films 131 and 132 using phosphine at an applied voltage of 60 keV and a dose of 2.6 × 10 ⁻¹³ cm ⁻² . Thereby, impurity regions 125 to 128 are formed. In addition, when the impurities are introduced, regions to be channel formation regions 161 and 181 are determined.

  Thereafter, as shown in FIG. 7A, insulating films, so-called sidewalls 171 and 191 are formed so as to cover the side surfaces of the gate electrodes 103 and 104. That is, sidewalls 171 (171a and 171b) are formed on the side surfaces of the gate electrode 103, and sidewalls 191 (191a and 191b) are formed on the side surfaces of the gate electrode 104.

  The sidewalls 171 and 191 can be formed of an insulating film containing silicon by a plasma CVD method or a low pressure CVD (LPCVD) method. In this embodiment mode, a silicon oxide film with a thickness of 50 to 200 nm, preferably 100 nm, is formed by a plasma CVD method, and then the silicon oxide film is etched to form tapered sidewalls 171 and 191. Further, the sidewalls 171 and 191 may be formed using a silicon oxide film containing nitrogen.

  Further, the end portions of the sidewalls 171 and 191 do not have to have a tapered shape, and may have a rectangular shape.

Next, as a second addition step, phosphine (PH ₃ ) is used in the island-shaped semiconductor films 131 and 132, and the applied voltage is 10 to 50 keV, for example, 20 keV, and the dose is 5.0 × 10 ^{14 to} 2.5 × 10. Phosphorus (P) is introduced at ¹⁶ cm ⁻² , for example, 3.0 × 10 ¹⁵ cm ⁻² .

  In this second addition step, phosphorus is introduced into the island-shaped semiconductor film 131 using the gate electrode 103 and the sidewall 171 as a mask, and one of the source region or the drain region 163 in the island-shaped semiconductor film 131, the source region Alternatively, the other region 164 of the drain region, and the low-concentration impurity regions 162a and 162b are formed. Similarly, phosphorus is introduced into the island-shaped semiconductor film 132 using the gate electrode 104 and the sidewall 191 as a mask, and one of the source region and the drain region 183 and the other of the source region and the drain region are inserted into the island-shaped semiconductor film 132. Region 184, and low concentration impurity regions 182a and 182b are formed.

In this embodiment mode, the regions 163 and 164 which are the source region and the drain region of the n-channel TFT 118 and the regions 183 and 184 which are the source region and the drain region of the n-channel TFT 119 are each 1 × 10 ^19. Phosphorus (P) will be contained at a concentration of ˜5 × 10 ²¹ cm ⁻³ .

Further, each of the low concentration impurity regions 162a and 162b of the n-channel TFT 118 and the low concentration impurity regions 182a and 182b of the n-channel TFT 119 has phosphorus (P) at a concentration of 1 × 10 ^{18 to} 5 × 10 ¹⁹ cm ^−3. Is included.

  Next, a first interlayer insulating film 155 is formed to cover the island-shaped semiconductor films 131 and 132, the gate insulating film 152, the gate electrodes 103 and 104, and the sidewalls 171 and 191 (see FIG. 7C).

  As the first interlayer insulating film 155, an insulating film containing silicon, for example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, or a stacked film thereof is formed using a plasma CVD method or a sputtering method. Needless to say, the first interlayer insulating film 155 is not limited to a silicon oxide film or silicon nitride film containing nitrogen, or a laminated film thereof, and other insulating films containing silicon may be used as a single layer or a laminated structure. .

  In this embodiment mode, a silicon oxide film containing nitrogen is formed to a thickness of 50 nm by a plasma CVD method, and impurities are activated by a laser irradiation method. Alternatively, after forming a silicon oxide film containing nitrogen, the impurity may be activated by heating at 550 ° C. for 4 hours in a nitrogen atmosphere.

  Next, a silicon nitride film is formed to 100 nm by a plasma CVD method, and a silicon oxide film is further formed to 600 nm. The laminated film of the silicon oxide film containing nitrogen, the silicon nitride film, and the silicon oxide film is the first interlayer insulating film 155.

  Next, the whole is heated at 410 ° C. for 1 hour, and hydrogen is released by releasing hydrogen from the silicon nitride film.

  Next, a second interlayer insulating film 156 is formed so as to cover the first interlayer insulating film 155.

  As the second interlayer insulating film 156, an inorganic material such as silicon oxide or silicon nitride can be used by a CVD method, a sputtering method, a SOG (Spin On Glass) method, or the like. In this embodiment, a silicon oxide film is formed as the second interlayer insulating film 156.

  Further, as the second interlayer insulating film 156, an insulating film using siloxane may be formed. Siloxane has a skeletal structure composed of a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used as a substituent. . A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Note that a passivation film may be formed over the second interlayer insulating film 156. As the passivation film, a film that does not easily transmit moisture, oxygen, or the like as compared with other insulating films is used. Typically, a silicon nitride film, a silicon oxide film, a silicon nitride film containing oxygen or a silicon oxide film containing nitrogen obtained by a sputtering method or a CVD method, a thin film mainly containing carbon (for example, a diamond-like carbon film (DLC) Film), carbon nitride film (CN film)) and the like can be used.

  Next, a conductive film is formed over the second interlayer insulating film 156, and the electrode 109, the electrode 113, the electrode 114, and the electrode 110 which serve as a source electrode or a drain electrode are formed using the conductive film (see FIG. 8A). .

  The electrode 109 which is one of the source electrode and the drain electrode of the TFT 118 is electrically connected to the region 163, and the electrode 113 which is the other of the source electrode and the drain electrode is electrically connected to the region 164. The electrode 114 which is one of the source electrode and the drain electrode of the TFT 119 is electrically connected to the region 183, and the electrode 110 which is the other of the source electrode and the drain electrode is electrically connected to the region 184.

  In this embodiment mode, as the electrode 109, the electrode 113, the electrode 114, and the electrode 110, aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo) is formed by a CVD method, a sputtering method, or the like. ), Nickel (Ni), cobalt (Co), iron (Fe), platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C ), An element selected from silicon (Si), or an alloy material or a compound material containing these elements as a main component. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The electrode 109, the electrode 113, the electrode 114, and the electrode 110 include, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier. A laminated structure of films may be employed. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon have low resistance and are inexpensive, and are optimal materials for forming the electrode 109, the electrode 113, the electrode 114, and the electrode 110. Further, the aluminum alloy film can prevent mutual diffusion of silicon and aluminum even when it comes into contact with silicon. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented.

  In this embodiment mode, a film in which a titanium film (Ti), a titanium nitride film, an aluminum film (Al), and a titanium film (Ti) are stacked to 60 nm, 50 nm, 500 nm, and 100 nm, respectively, is used. Electrode 114 and electrode 110 are formed.

  In addition, the electrode 109, the electrode 113, the electrode 114, and the electrode 110 may each be formed using the same material and the same process in the same process, or may be formed separately and connected to each other.

  Next, a third interlayer insulating film 135 is formed on the electrode 109, the electrode 113, the electrode 114, the electrode 110, and the second interlayer insulating film 156, or on the passivation film if a passivation film is formed ( (See FIG. 8B). The third interlayer insulating film 135 may be formed using a material similar to that of the second interlayer insulating film 156.

  A contact hole 165 reaching the electrode 109, a contact hole 166 reaching the electrode 113, a contact hole 167 reaching the electrode 114, and a contact hole 168 reaching the electrode 110 are formed in the third interlayer insulating film 135 (FIG. 9). (See (A)).

  Next, the entire substrate is immersed in the electrolytic solution. As the electrolytic solution, an electrolytic solution that dissolves the materials of the electrode 109, the electrode 113, the electrode 114, and the electrode 110 may be selected. For example, when aluminum is used as the material of the electrode 109, the electrode 113, the electrode 114, and the electrode 110, potassium hydroxide or phosphate can be used as the electrolytic solution. However, it is not always necessary to immerse the entire substrate in the electrolytic solution, as long as the electrode is immersed in the electrolytic solution to such an extent that the electrode can be dissolved.

  Table 1 shows an example of a combination of a material for forming the electrode 109, the electrode 113, the electrode 114, and the electrode 110 and an electrolytic solution for the material.

  When the electrode is immersed in the electrolytic solution and a voltage is applied to the electrode, the metal on the electrode surface dissolves into the electrolytic solution as ions, and the electrode material dissolves. As shown in FIG. 9B, part of the electrode 110 is dissolved to form a divided region 169. Note that the TFT 119 is preferably normally off in order to prevent the electrode 114 from being dissolved at this time. Alternatively, the contact hole reaching the electrode 114 may be formed after the dividing region 169 is formed.

  Next, as shown in FIG. 1, on the third interlayer insulating film 135, the wiring 175 electrically connected to the electrode 109, the wiring 176 electrically connected to the electrode 113, and the electrode 114 are electrically connected. A wiring 177 is formed.

  Although the wiring 178 is formed over the third interlayer insulating film 135 and above the electrode 110, the wiring 178 is formed so as to reach the dividing region 169, and thus the wiring 178 and the electrode 110 are not electrically connected.

  Note that the wirings 175 to 178 may be formed using any of the materials for forming the electrodes 109 and the like described above.

  Thus, the TFT of the memory cell array is formed. Note that the TFT of the logic circuit may be formed in the same manner as the TFT of the memory cell array, or may be peeled off after being formed on another substrate and electrically connected to the TFT of the memory cell array.

  According to the present invention, since a memory cell of a mask ROM having information of different ID numbers can be easily formed, it is possible to reduce manufacturing time and manufacturing cost of a semiconductor device capable of wireless communication using an IC. Become.

  FIG. 13 shows a top view of a mask ROM including the memory cell array of the present invention. In the mask ROM 900, the memory cell array 920 of the present invention (same as the memory cell array 11 of FIG. 10) is formed, and the column decoder 921 (same as the column decoder 15 of FIG. 10) and the row are formed by using the above-described logic circuit TFT. A decoder 922 (same as row decoder 16 in FIG. 10) is formed.

  FIG. 14 shows an example of a semiconductor device having the mask ROM 900 of FIG. 13 and capable of wireless communication using an IC. Note that the semiconductor device illustrated in FIG. 14 is an example, and the present invention is not limited to the structure illustrated in FIG.

  A semiconductor device (ID chip, IC chip, IC tag, ID tag, wireless chip, RFID) 931 illustrated in FIG. 14 includes an antenna 917, a high-frequency circuit 914, a power supply circuit 915, a reset circuit 911, a rectifier circuit 906, and a demodulation circuit. 907, an analog amplifier 908, a clock generation circuit 903, a modulation circuit 909, a signal output control circuit 901, a CRC circuit 902, a code extraction circuit 904, a code determination circuit 905, and a mask ROM 900 circuit block. The power supply circuit 915 includes circuit blocks including a rectifier circuit 913 and a storage capacitor 912. Further, the mask ROM 900 includes a memory cell array 920, a column decoder 921, and a row decoder 922 as shown in FIG.

  9B, the circuit 951 and the computer 955 shown in FIG. 15 are connected to the memory cell array 920 in the step of forming the dividing region 169 by dissolving the electrode 110 shown in FIG. The circuit 951 may be formed on the same substrate as the memory cell array 920 or may be externally attached.

  In the circuit 951, TFTs corresponding to the respective TFTs of the memory cell array 920 are formed. It is assumed that the circuit 951 can selectively apply a target voltage to each wiring (electrode) in the memory cell array 920 in accordance with a signal from the computer 955. In the state where this voltage is applied, the substrate is immersed in the electrolytic solution, and the voltage of the wiring elution condition in consideration of the electrolytic solution and the wiring material is applied to the wiring, so that the wiring in the opening is eluted into the electrolytic solution. In this way, individual wires (electrodes) in the substrate surface are selectively divided.

  Further, a part of the circuit 951 which is connected to the computer 955 and reaches the opening may be formed on the back surface in order to secure a space on the substrate surface. At this time, an opening reaching the back surface from the front surface is provided in the substrate, and the wiring is penetrated and connected.

  According to the present invention, it is possible to easily attach unique data such as a different ID number to a semiconductor device capable of wireless communication using an IC. In particular, when a large number of semiconductor devices capable of wireless communication are formed in a large-area substrate, tact and cost can be reduced.

  Note that this embodiment can be combined with any description in the other embodiments and examples if necessary.

[Embodiment 2]
In this embodiment mode, a process of manufacturing a TFT of a memory cell array and a TFT of a logic circuit over the same substrate is described with reference to FIGS. 16A to 16D, FIGS. 17A to 17C, and FIG. This will be described with reference to FIGS. 18A to 18C, FIGS. 19A to 19B, and FIGS. 20A to 20B.

  First, as shown in FIG. 16A, a base film 602 is formed over a substrate 601. As the substrate 601, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a stainless steel substrate, a so-called SOI (Silicon on Insulator) substrate in which a single crystal semiconductor layer is formed on an insulating surface, or the like is used. be able to. In addition, a substrate made of a plastic such as PET (poly (ethylene terephthalate)), PES (poly (ether sulfone)), or PEN (poly (ethyl naphthaphthalate)) or a flexible synthetic resin such as acrylic is used. It is also possible. Hereinafter, a case where a glass substrate is used as the substrate 601 will be described.

  The base film 602 is provided to prevent alkali metal such as Na or alkaline earth metal contained in the substrate 601 from diffusing into the semiconductor film and adversely affecting the characteristics of the semiconductor element. Therefore, an insulating film such as silicon nitride or silicon oxide containing nitrogen that can suppress diffusion of alkali metal or alkaline earth metal into the semiconductor film is used. In this embodiment mode, a silicon oxide film is formed with a plasma CVD method to have a thickness of 10 to 100 nm (preferably 20 to 70 nm, more preferably 50 nm), and a silicon oxide film containing nitrogen is 10 to 400 nm (preferably 50 to 300 nm). And more preferably 100 nm).

  Note that even though the base film 602 is an insulating film single layer such as silicon nitride, silicon oxide containing nitrogen, or silicon nitride containing oxygen, insulation such as silicon oxide, silicon nitride, silicon oxide containing nitrogen, or silicon nitride containing oxygen is used. A plurality of laminated films may be used. In addition, when using a substrate that contains alkali metal or alkaline earth metal, such as a glass substrate, stainless steel substrate, or plastic substrate, it is effective to provide a base film from the viewpoint of preventing impurity diffusion. However, when diffusion of impurities does not cause any problem, such as a quartz substrate, it is not necessarily provided.

  Next, a semiconductor film 604 is formed over the base film 602. The thickness of the semiconductor film 604 is 25 nm to 100 nm (preferably 30 nm to 80 nm). Note that the semiconductor film 604 may be an amorphous semiconductor or a polycrystalline semiconductor. As the semiconductor, not only silicon (Si) but also silicon germanium (SiGe) can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%. In this embodiment, an amorphous silicon film is formed as the semiconductor film 604 with a thickness of 66 nm.

  Next, as shown in FIG. 16B, the semiconductor film 604 is irradiated with a linear beam 603 from a laser irradiation apparatus to be crystallized.

  In the case of performing laser crystallization, heat treatment for one hour at 500 ° C. may be applied to the semiconductor film 604 in order to increase the resistance of the semiconductor film 604 to the laser before laser crystallization.

  For laser crystallization, a pulsed laser having an oscillation frequency of 10 MHz or more, preferably 80 MHz or more can be used as a continuous wave laser or a pseudo CW laser.

Specifically, as a continuous wave laser, Ar laser, Kr laser, CO ₂ laser, YAG laser, YVO ₄ laser, forsterite (Mg ₂ SiO ₄ ) laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, alexandrite laser, Ti: sapphire laser, helium cadmium laser, polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ as dopants Nd, Yb, Cr, Ti, Ho , Er, Tm, Ta, or the like, or a laser having a medium added with one or more of them.

As a pseudo CW laser, an Ar laser, a Kr laser, an excimer laser, a CO ₂ laser, a YAG laser, a Y ₂ O ₃ laser, a YVO can be used as long as it can oscillate a pulse having an oscillation frequency of 10 MHz or more, preferably 80 MHz or more. ₄ laser, forsterite (Mg ₂ SiO ₄ ) laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, alexandrite laser, Ti: sapphire laser, copper vapor laser or gold vapor laser, polycrystalline (ceramic) YAG, Y ₂ A pulse like a laser in which one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta are added as dopants to O ₃ , YVO ₄ , YAlO ₃ , and GdVO ₄ as a medium. An oscillation laser can be used.

  Such a pulsed laser has an effect equivalent to that of a continuous wave laser as the oscillation frequency is increased.

For example, when a solid-state laser capable of continuous oscillation is used, a crystal having a large grain size can be obtained by irradiating laser light of second to fourth harmonics. Typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of a YAG laser (fundamental wave 1064 nm). For example, laser light emitted from a continuous wave YAG laser is converted into a harmonic by a non-linear optical element, and irradiated to the semiconductor film 604. Energy density may be about 0.01 to 100 MW / cm ² (preferably 0.1~10MW / cm ^2). Irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta, a laser that uses one or a plurality of types added as a medium, Ar laser, Kr laser, or Ti: sapphire laser It is also possible to cause pulse oscillation by performing Q switch operation, mode synchronization, and the like. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

  Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, the output is greatly improved.

  Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction.

  By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion.

  By irradiation of the semiconductor film 604 with laser light, the crystalline semiconductor film 605 with higher crystallinity is formed.

  Next, as illustrated in FIG. 16C, island-shaped semiconductor films 611 to 614 are formed using the crystalline semiconductor film 605. These island-like semiconductor films 611 to 614 serve as active layers of TFTs formed in the subsequent steps.

  Note that this embodiment mode describes the case where a glass substrate is used as the substrate 601, but when an SOI substrate is used as the substrate 601, a single crystal semiconductor layer is formed into an island shape and an active layer of a TFT And it is sufficient.

Next, impurities for threshold control are introduced into the island-shaped semiconductor films 611 to 614. In this embodiment mode, boron (B) is introduced into the island-shaped semiconductor films 611 to 614 by doping with diborane (B ₂ H ₆ ).

  Next, a gate insulating film 615 is formed over the island-shaped semiconductor films 611 to 614. For the gate insulating film 615, silicon oxide, silicon nitride, silicon oxide containing nitrogen, or the like with a thickness of 10 to 110 nm can be used, for example. As a film formation method, a plasma CVD method, a sputtering method, or the like can be used. In this embodiment, the gate insulating film 615 is formed using a silicon oxide film containing nitrogen which is formed to a thickness of 20 nm by a plasma CVD method.

  Next, after a conductive film is formed over the gate insulating film 615, gate electrodes 621 to 624 are formed using the conductive film.

  The gate electrodes 621 to 624 are formed using a structure in which a single conductive film or two or more conductive films are stacked. In the case where two or more conductive films are stacked, an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), and aluminum (Al), or the element as a main component The gate electrodes 621 to 624 may be formed by stacking alloy materials or compound materials to be stacked. Alternatively, the gate electrode may be formed using a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus (P). In this embodiment, a tantalum nitride film having a thickness of 10 to 50 nm, for example, 30 nm is formed as the lower gate electrodes 621a to 624a, and a tungsten (W) film is formed to 200 to 400 nm as the upper gate electrodes 621b to 624b. For example, the gate electrodes 621 to 624 are formed using a stacked film formed with a thickness of 370 nm.

  The gate electrodes 621 to 624 may be formed as part of the gate wiring, or a gate wiring may be formed separately and the gate electrodes 621 to 624 may be connected to the gate wiring.

  Next, an impurity imparting one conductivity is added to the island-shaped semiconductor films 611 to 613. Note that in this addition step, the island-shaped semiconductor film 614 and the gate electrode 624, that is, a region to be the p-channel TFT 694 is covered with the resist 618, and an impurity imparting one conductivity is in the island-shaped semiconductor film 614. Is not added.

  As an impurity imparting one conductivity, phosphorus (P) or arsenic (As) may be used as long as it is an impurity imparting n-type conductivity. Further, boron (B) may be used as long as it is an impurity imparting p-type.

In this embodiment, first, as a first addition step, an impurity imparting n-type conductivity is added to the island-shaped semiconductor films 611 to 613 (see FIG. 16D). Specifically, phosphorous (P) is applied using phosphine (PH ₃ ), the applied voltage is 40 to 120 keV, the dose is 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² , and the island-shaped semiconductor films 611 to 613 are used. Introduce into. In this embodiment mode, phosphorus is added into the island-shaped semiconductor films 611 to 613 using phosphine at an applied voltage of 60 keV and a dose of 2.6 × 10 ⁻¹³ cm ⁻² . When this impurity is introduced, regions to be channel formation regions 631, 641, and 651 are determined.

  Thereafter, as shown in FIG. 17A, insulating films, so-called sidewalls 626 to 629 are formed so as to cover the side surfaces of the gate electrodes 621 to 624. That is, the sidewall 626 (626a and 626b) is formed on the side surface of the gate electrode 621, the sidewall 627 (627a and 627b) is formed on the side surface of the gate electrode 622, the sidewall 628 (628a and 628b) is formed on the side surface of the gate electrode 623, and the gate electrode 624. Side walls 629 (629a and 629b) are formed on the side surfaces.

  The sidewalls 626 to 629 can be formed using an insulating film containing silicon by a plasma CVD method or a low pressure CVD (LPCVD) method. In this embodiment mode, a silicon oxide film is formed with a thickness of 50 to 200 nm, preferably 100 nm by a plasma CVD method, and then the silicon oxide film is etched, whereby tapered sidewalls 626 to 629 are formed. The sidewalls 626 to 629 may be formed using a silicon oxide film containing nitrogen.

  Further, the end portions of the sidewalls 626 to 629 do not have to have a tapered shape, and may have a rectangular shape.

  Next, as illustrated in FIG. 17B, a resist 616 is formed so as to cover the island-shaped semiconductor film 614, the gate electrode 624, the sidewall 629, that is, a region that will later become a p-channel TFT 694.

Next, as a second addition step, phosphine (PH ₃ ) is used in the island-shaped semiconductor films 611 to 613 to apply an applied voltage of 10 to 50 keV, for example, 20 keV, and a dose amount of 5.0 × 10 ^{14 to} 2.5 × 10. Phosphorus (P) is introduced at ¹⁶ cm ⁻² , for example, 3.0 × 10 ¹⁵ cm ⁻² .

  In this second addition step, phosphorus is introduced into the island-shaped semiconductor film 611 using the gate electrode 621 and the sidewall 626 as a mask, and one of the source region or the drain region 633 in the island-shaped semiconductor film 611, the source region Alternatively, the other region 634 of the drain region, and the low-concentration impurity regions 632a and 632b are formed. Similarly, phosphorus is introduced into the island-shaped semiconductor film 612 using the gate electrode 622 and the sidewall 627 as a mask, and one of the source region and the drain region 643 and the other of the source region and the drain region are inserted into the island-shaped semiconductor film 612. Region 644, and low-concentration impurity regions 642a and 642b. Further, phosphorus is introduced into the island-shaped semiconductor film 613 using the gate electrode 623 and the sidewall 628 as a mask, and one region 653 of the source region or the drain region and the other region of the source region or the drain region are inserted into the island-shaped semiconductor film 613. 654, and low concentration impurity regions 652a and 652b are formed.

In this embodiment mode, regions 633 and 634 which are a source region and a drain region of an n-channel TFT 691, regions 643 and 644 which are a source region and a drain region of an n-channel TFT 692, and a source region of the n-channel TFT 693 In addition, each of the region 653 and the region 654 which are drain regions contains phosphorus (P) at a concentration of 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ .

Further, low concentration impurity regions 632a and 632b of the n-channel TFT 691, low-concentration impurity regions 642a and 642b of the n-channel TFT 692, and low-concentration impurity regions 652a and 652b of the n-channel TFT 693 are each 1 × 10 ^{18 to} 5 Phosphorus (P) is contained at a concentration of × 10 ¹⁹ cm ⁻³ .

  Next, the resist 616 is further removed, and a resist 617 is formed to cover the island-shaped semiconductor films 611 to 613, the gate electrodes 621 to 623, and the sidewalls 626 to 628, that is, the regions to be the n-channel TFTs 691 to 693.

In order to manufacture the p-channel TFT 694, an impurity imparting a conductivity type opposite to the impurity imparting one conductivity type, that is, an impurity imparting p-type conductivity is added to the island-shaped semiconductor film 614. Specifically, using diborane (B ₂ H ₆ ), an applied voltage of 60 to 100 keV, for example, 80 keV, a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁵ cm ⁻² , for example, 3 × 10 ¹⁵ cm ⁻² . Boron (B) is introduced into the island-shaped semiconductor film 614. Thus, a region 663 and a region 664 which are a source region and a drain region of the p-channel TFT, and a channel formation region 661 are formed when this impurity is introduced (see FIG. 17C).

  Note that in the p-channel TFT 694, since an applied voltage is high when boron is introduced, sufficient boron to form the region 663 and the region 664 is formed in the island-shaped semiconductor film 614 through the sidewall 629 and the gate insulating film 615. Added in.

The regions 663 and 664 which are the source region and the drain region of the p-channel TFT 694 contain boron (B) at a concentration of 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ .

  Next, the resist 617 is removed, and a first interlayer insulating film 671 is formed to cover the island-shaped semiconductor films 611 to 614, the gate insulating film 615, the gate electrodes 621 to 624, and the sidewalls 626 to 629.

  As the first interlayer insulating film 671, an insulating film containing silicon, for example, a silicon oxide film, a silicon nitride film, a silicon oxide film containing nitrogen, or a stacked film thereof is formed using a plasma CVD method or a sputtering method. Needless to say, the first interlayer insulating film 671 is not limited to a silicon oxide film or a silicon nitride film containing nitrogen, or a laminated film thereof, and another insulating film containing silicon may be used as a single layer or a laminated structure. .

  In this embodiment mode, a silicon oxide film containing nitrogen is formed to a thickness of 50 nm by a plasma CVD method, and impurities are activated by a laser irradiation method. Alternatively, after forming a silicon oxide film containing nitrogen, the impurity may be activated by heating at 550 ° C. for 4 hours in a nitrogen atmosphere.

  Next, a silicon nitride film is formed to 100 nm by a plasma CVD method, and a silicon oxide film is further formed to 600 nm. The laminated film of the silicon oxide film containing nitrogen, the silicon nitride film, and the silicon oxide film is the first interlayer insulating film 671.

  Next, the whole is heated at 410 ° C. for 1 hour, and hydrogen is released by releasing hydrogen from the silicon nitride film.

  Next, a second interlayer insulating film 672 is formed so as to cover the first interlayer insulating film 671 (see FIG. 18A).

  As the second interlayer insulating film 672, an inorganic material such as silicon oxide or silicon nitride can be used by a CVD method, a sputtering method, a SOG (Spin On Glass) method, or the like. In this embodiment, a silicon oxide film is formed as the second interlayer insulating film 672.

  Further, as the second interlayer insulating film 672, an insulating film using siloxane may be formed. Siloxane has a skeletal structure composed of a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used as a substituent. . A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Note that a third interlayer insulating film may be formed over the second interlayer insulating film 672. As the third interlayer insulating film, a film that hardly transmits moisture, oxygen, or the like as compared with other insulating films is used. Typically, a silicon nitride film, a silicon oxide film, a silicon nitride film containing oxygen or a silicon oxide film containing nitrogen obtained by a sputtering method or a CVD method, a thin film mainly containing carbon (for example, a diamond-like carbon film (DLC) Film), carbon nitride film (CN film)) and the like can be used.

  Next, contact holes for electrical connection with the island-shaped semiconductor films 611, 612, 613, and 614 are formed in the first interlayer insulating film 671 and the second interlayer insulating film 672.

  In the first interlayer insulating film 671 and the second interlayer insulating film 672, a contact hole 673 reaching the region 633 of the island-shaped semiconductor film 611, a contact hole 674 reaching the region 634 of the island-shaped semiconductor film 611, and the island-shaped semiconductor film 612 Contact hole 675 reaching the region 643, contact hole 676 reaching the region 644 of the island-shaped semiconductor film 612, contact hole 677 reaching the region 653 of the island-shaped semiconductor film 613, and reaching the region 654 of the island-shaped semiconductor film 613 A contact hole 678 reaching the region 663 of the island-shaped semiconductor film 614, and a contact hole 680 reaching the region 664 of the island-shaped semiconductor film 614 are formed (see FIG. 18B).

  Further, the contact holes 673 to 680 may be constituted by one contact hole or may be constituted by a plurality of contact holes.

  Next, a conductive film is formed over the second interlayer insulating film 672, and source or drain electrodes 681, 682, 683, 684, 685, 686, and 687 are formed using the conductive film (see FIG. 18C). .

  An electrode 681 which is one of a source electrode and a drain electrode of the TFT 691 is electrically connected to the region 633, and an electrode 682 which is the other of the source electrode and the drain electrode is electrically connected to the region 634. An electrode 683 that is one of a source electrode and a drain electrode of the TFT 692 is electrically connected to the region 643. An electrode 684 which is the other of the source electrode and the drain electrode of the TFT 692 is electrically connected to the region 644.

  An electrode 685 which is one of a source electrode and a drain electrode of the TFT 693 is electrically connected to the region 653. An electrode 686 which is the other of the source electrode and the drain electrode of the TFT 693 and one of the source electrode and the drain electrode of the TFT 694 is electrically connected to the region 654 and the region 663. An electrode 687 which is the other of the source electrode and the drain electrode of the TFT 694 is electrically connected to the region 664. Thereby, the TFTs 693 and 694 constitute a CMOS circuit 695.

  In this embodiment mode, as the electrodes 681 to 687, aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), CVD, sputtering, or the like is used. From cobalt (Co), iron (Fe), platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si) The selected element or an alloy material or compound material containing these elements as a main component is formed in a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. For example, the electrodes 681 to 687 adopt a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. Good. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are suitable as materials for forming the electrodes 681 to 687 because they have low resistance and are inexpensive. Further, the aluminum alloy film can prevent mutual diffusion of silicon and aluminum even when it comes into contact with silicon. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented.

  In this embodiment mode, the electrodes 681 to 687 are formed using layers in which a titanium film (Ti), a titanium nitride film, an aluminum film (Al), and a titanium film (Ti) are stacked to 60 nm, 50 nm, 500 nm, and 100 nm, respectively. To do.

  Each of the electrodes 681 to 687 may be formed of the same material and electrode in the same process, or may be formed separately and connected to each other.

  Next, an interlayer insulating film 697 is formed over the electrodes 681 to 687 and the interlayer insulating film 672, or over the passivation film if a passivation film is formed (see FIG. 19A). The interlayer insulating film 697 may be formed using a material similar to that of the interlayer insulating film 672.

  In the interlayer insulating film 672, a contact hole 851 reaching the electrode 681, a contact hole 852 reaching the electrode 682, a contact hole 853 reaching the electrode 683, a contact hole 854 reaching the electrode 684, and a contact hole reaching the electrode 685. 855, a contact hole 856 that reaches the electrode 686, and a contact hole 857 that reaches the electrode 687 are formed (see FIG. 19B).

  Next, the entire substrate is immersed in the electrolytic solution. As the electrolytic solution, an electrolytic solution that dissolves the materials of the electrodes 681 to 687 may be selected. A combination of a material for forming the electrodes 681 to 687 and an electrolytic solution for the material may be selected from Table 1 described in the first embodiment. However, it is not always necessary to immerse the entire substrate in the electrolytic solution, as long as the electrode is immersed in the electrolytic solution to such an extent that the electrode can be dissolved.

  When the electrode is immersed in the electrolytic solution and a voltage is applied to the electrode, the metal on the electrode surface dissolves into the electrolytic solution as ions, and the electrode material dissolves. As shown in FIG. 20A, a part of the electrode 683 is dissolved to form a divided region 860.

  Next, as illustrated in FIG. 20B, the wiring 871 electrically connected to the electrode 681, the wiring 872 electrically connected to the electrode 682, and the electrode 684 are electrically connected over the interlayer insulating film 697. A wiring 874 to be electrically connected to the electrode 685, a wiring 876 to be electrically connected to the electrode 686, and a wiring 877 to be electrically connected to the electrode 687 are formed.

  Although the wiring 873 is formed over the interlayer insulating film 672 and above the electrode 683, the wiring 873 is formed so as to reach the dividing region 860, so that the wiring 873 and the electrode 683 are not electrically connected.

  Note that the wirings 871 to 877 may be formed using any of the materials for forming the electrode 681 and the like described above.

  As described above, the memory cell array TFT and the logic circuit TFT are formed on the same substrate.

  Note that this embodiment can be combined with any of the other embodiments and examples if necessary.

[Embodiment 3]
In this embodiment, a method for manufacturing a semiconductor device capable of wireless communication using an IC which is different from those in Embodiments 1 and 2 will be described with reference to FIGS. 14, 21 </ b> A to 21 </ b> B, and 22. This will be described with reference to FIGS. In the present embodiment, the same reference numerals are used for the same components as those in the first and second embodiments.

  First, the semiconductor device illustrated in FIG. 20B is manufactured based on the description in Embodiment Mode 2. Note that a peeling layer 802, a first base film 803, and a second base film 804 are formed instead of the base film 602.

  The separation layer 802 is formed using an amorphous semiconductor film, a polycrystalline semiconductor film, or a semi-amorphous semiconductor film. For example, a layer containing silicon as its main component such as amorphous silicon, polycrystalline silicon, single crystal silicon, or semi-amorphous silicon can be used. The separation layer 802 can be formed by a sputtering method, a plasma CVD method, or the like. In this embodiment, amorphous silicon with a thickness of about 500 nm is formed by a sputtering method and used as the separation layer 802.

  Note that a semi-amorphous semiconductor film (hereinafter also referred to as a SAS film) is a film including a semiconductor having an intermediate structure between an amorphous semiconductor film and a semiconductor (including single crystal and polycrystal) film having a crystal structure. This semi-amorphous semiconductor film is a semiconductor film having a third state that is stable in terms of free energy, and is a crystalline film having short-range order and lattice distortion, and has a grain size of 0.5 to 20 nm. And can be dispersed in the non-single-crystal semiconductor film.

  Further, in order to terminate dangling bonds (dangling bonds), at least 1 atomic% or more of hydrogen or halogen is contained.

  In this specification, for convenience, the semiconductor film is referred to as a semi-amorphous semiconductor (SAS) film. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, the stability is improved and a good semi-amorphous semiconductor film can be obtained. Note that a microcrystalline semiconductor film is also included in the semi-amorphous semiconductor film.

A typical example of the semi-amorphous semiconductor film is a semi-amorphous silicon film. The semi-amorphous silicon film has its Raman spectrum shifted to a lower wavenumber than 520 cm ⁻¹ , and diffraction peaks of (111) and (220) that are derived from the Si crystal lattice in X-ray diffraction are observed. The

A semi-amorphous silicon film can be obtained by glow discharge decomposition of a gas containing silicon. A typical gas containing silicon is SiH ₄ , and Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can also be used. Forming a semi-amorphous silicon film by diluting a gas containing silicon with hydrogen or a gas obtained by adding one or more kinds of rare gas elements selected from helium, argon, krypton, or neon to hydrogen. Can be made easy. It is preferable to dilute the gas containing silicon in a range of a dilution rate of 2 to 1000 times. Furthermore, a gas containing silicon, a carbide gas such as CH ₄ or C ₂ H ₆ , a germanium gas such as GeH ₄ or GeF ₄ , F _2, or the like is mixed, so that the energy bandwidth is 1.5-2. It may be adjusted to .4 eV, or 0.9 to 1.1 eV.

  The first base film 803 and the second base 804 are formed using an insulating film such as a silicon oxide film, a silicon nitride film, a silicon nitride film containing oxygen, or a silicon oxide film containing nitrogen. In this embodiment, a silicon nitride film containing oxygen is stacked as the first base film 803 in a thickness of 10 to 200 nm, and a silicon oxide film containing nitrogen is stacked as the second base film 804 in order of 50 to 200 nm.

  After the wirings 871 to 877 are formed based on the description in Embodiment Mode 2, the interlayer insulating film 806 is formed over the interlayer insulating film 697, and the electrodes 811 to 816 functioning as an antenna are formed. The electrodes 811 to 816 functioning as an antenna are formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, or a plating method. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  A protective layer 807 is formed over the interlayer insulating film 806 so as to cover the electrodes 811 to 816 functioning as an antenna. The protective layer 807 is formed using a material that can protect the electrodes 811 to 816 functioning as an antenna when the peeling layer 802 is removed by etching later. For example, the protective layer 807 can be formed by applying an epoxy resin, an acrylate resin, or a silicon resin soluble in water or alcohols over the entire surface (see FIG. 21A).

  Next, a groove 808 for separating the separation layer 802 is formed (see FIG. 21B). The groove 808 may be of a size that exposes the release layer 802. The groove 808 can be formed by etching, dicing, scribing, laser irradiation, or the like.

Next, the peeling layer 802 is removed by etching (see FIG. 22A). In this embodiment mode, halogen fluoride is used as an etching gas, and the gas is introduced from the groove 808. In this embodiment, for example, ClF ₃ (chlorine trifluoride) is used, and the temperature is 350 ° C., the flow rate is 300 sccm, the atmospheric pressure is 800 Pa, and the time is 3 hours. Further, a gas in which nitrogen is mixed with ClF ₃ gas may be used. By using halogen fluoride such as ClF ₃ , the peeling layer 802 can be selectively etched and the substrate 601 can be peeled off. The halogen fluoride may be either a gas or a liquid.

  Next, the memory cell array including the peeled TFTs 691 and 692 and the logic circuit including the TFTs 693 and 694 are attached to the support 821 using an adhesive 822 (see FIG. 22B). As the adhesive 822, a material capable of bonding the support 821 and the first base film 803 is used. As the adhesive 822, for example, various curable adhesives such as a reaction curable adhesive, a thermosetting adhesive, a photo-curable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

  As the support 821, an organic material such as flexible paper or plastic can be used. Alternatively, a flexible inorganic material may be used as the support 821. The support 821 preferably has a high thermal conductivity of about 2 to 30 W / mK in order to diffuse the heat generated in the integrated circuit.

  Note that a method for peeling the integrated circuit of the memory cell array and the logic circuit from the substrate 601 is not limited to the method using etching of a layer containing silicon as a main component as shown in this embodiment mode, and other various methods can be used. Can be used. For example, a metal oxide film can be provided between a substrate having high heat resistance and an integrated circuit, and the integrated circuit can be peeled by weakening the metal oxide film by crystallization. Further, for example, the integrated layer can be peeled from the substrate by breaking the peeling layer by laser light irradiation. Further, for example, the integrated circuit can be peeled from the substrate by mechanically removing the substrate on which the integrated circuit is formed or removing the substrate by etching with a solution or gas.

  In addition, the surface of the object has a curved surface, and the support of the semiconductor device having the memory cell array and the logic circuit bonded to the curved surface has a curved surface drawn by the movement of the bus such as a cone surface or a column surface. In the case of bending so as to have, it is desirable to align the direction of the bus and the direction in which the TFT carrier moves. With the above configuration, even if the support is bent, it can be suppressed that the characteristics of the TFT are affected thereby. In addition, by setting the ratio of the area occupied by the island-shaped semiconductor film in the integrated circuit to 1 to 30%, even if the support is bent, the influence on the characteristics of the TFT can be further suppressed.

  Through the above manufacturing process, a semiconductor device capable of wireless communication using the IC of the present invention is manufactured.

  Note that in this embodiment mode, an antenna is formed over the same substrate as the substrate over which the semiconductor device is formed. However, after the semiconductor device is formed, the antenna is formed over the substrate over which the semiconductor device is formed by a printing method. It may be formed. Alternatively, the antenna may be formed separately from the substrate over which the semiconductor device is formed, the substrate over which the semiconductor device is formed, and the substrate over which the antenna is formed are bonded to electrically connect the semiconductor device and the antenna.

  An example in which the antenna is formed separately from the substrate on which the semiconductor device is formed, the substrate on which the semiconductor device is formed and the substrate on which the antenna is formed is bonded, and the semiconductor device and the antenna are electrically connected to each other. 14 will be described.

  A terminal portion 1605 including a terminal electrode and the like is provided over a substrate 1601 provided with a semiconductor device 1602 including a memory cell array and a logic circuit.

  Then, an antenna 1612 provided over a substrate 1611 different from the substrate 1601 is electrically connected to the terminal portion 1605. A substrate 1601 and a substrate 1611 provided with an antenna 1612 are attached to each other so as to be connected to the terminal portion 1605. Conductive particles 1603 and a resin 1604 are provided between the substrate 1601 and the substrate 1611. The antenna 1612 and the terminal portion 1605 are electrically connected by the conductive particles 1603. Note that the antenna 1612 illustrated in FIG. 23 is equivalent to the antenna 917 illustrated in FIG. 14. The antenna 1612 and the antenna 917 are electrically connected to a ground potential (GND) and a circuit such as the power supply circuit 915 and the high-frequency circuit 914. It is connected to the.

  This embodiment can be used in combination with any of the other embodiments and examples.

  In this embodiment, the structure and operation of a semiconductor device capable of wireless communication using an IC created using the present invention will be described with reference to FIGS.

  First, the configuration will be described. As shown in FIG. 14, a semiconductor device (also referred to as an ID chip, an IC chip, an IC tag, an ID tag, a wireless chip, or an RFID) 931 manufactured using the present invention includes an antenna 917, a high-frequency circuit 914, and a power supply circuit 915. , Reset circuit 911, rectifier circuit 906, demodulation circuit 907, analog amplifier 908, clock generation circuit 903, modulation circuit 909, signal output control circuit 901, CRC circuit 902, code extraction circuit 904, code determination circuit 905, and circuit of mask ROM 900 Has a block. The power supply circuit 915 includes circuit blocks including a rectifier circuit 913 and a storage capacitor 912. Further, as shown in FIG. 13, the mask ROM 900 includes a memory cell array 920, a column decoder 921, and a row decoder 922.

  Here, as the antenna 917, any of a dipole antenna, a patch antenna, a loop antenna, and a Yagi antenna can be used.

  In addition, a method for transmitting and receiving a radio signal in the antenna 917 may be any of an electromagnetic coupling method, an electromagnetic induction method, and a radio wave method.

  Note that the semiconductor device 931 manufactured using the present invention is applied to the semiconductor device 221 of FIG.

  Next, the operation of the semiconductor device 931 created using the present invention will be described. A radio signal is transmitted from an antenna unit 222 electrically connected to an interrogator (also referred to as a reader / writer) 223. The wireless signal includes a command from the interrogator (also referred to as a reader / writer) 223 to the semiconductor device 931.

  A radio signal received by the antenna 917 is sent to each circuit block via the high frequency circuit 914. A signal sent to the power supply circuit 915 through the high frequency circuit 914 is input to the rectifier circuit 913.

  Here, the rectifier circuit 913 has a function of adjusting the polarity of the radio signal. The signal is rectified and further smoothed by the storage capacitor 912. Then, a high power supply potential (VDD) is generated.

  The radio signal received by the antenna 917 is also sent to the rectifier circuit 906 via the high frequency circuit 914. The signal is rectified and demodulated by a demodulation circuit 907. The demodulated signal is amplified by an analog amplifier 908.

  Further, the radio signal received by the antenna 917 is also sent to the clock generation circuit 903 via the high frequency circuit 914. The signal sent to the clock generation circuit 903 is divided to become a basic clock signal. Here, the basic clock signal is sent to each circuit block and used for signal latching, signal selection, and the like.

  The signal amplified by the analog amplifier 908 and the basic clock signal are sent to the code extraction circuit 904. The code extraction circuit 904 extracts a command sent from the interrogator (also referred to as a reader / writer) 223 to the semiconductor device 931 from the signal amplified by the analog amplifier 908. A signal for controlling the code determination circuit 905 is also created.

  The instruction extracted by the code extraction circuit 904 is sent to the code determination circuit 905. The code determination circuit 905 determines what instruction is sent from the interrogator (also referred to as a reader / writer) 223. It also has a role of controlling the CRC circuit 902, the mask ROM 900, and the signal output control circuit 901.

  Thus, it is determined what command is sent from the interrogator (also referred to as reader / writer) 223, and the CRC circuit 902, the mask ROM 900, and the signal output control circuit 901 are operated according to the determined command. Then, a signal including unique data such as an ID number stored or written in the mask ROM 900 is output.

  Here, the mask ROM 900 has a memory cell array 920, a column decoder 921, and a row decoder 922.

  The signal output control circuit 901 also has a role of changing a signal including unique data such as an ID number stored or written in the mask ROM 900 into a signal encoded by an encoding method conforming to a standard such as ISO. .

  Finally, the signal sent to the antenna 917 is modulated by the modulation circuit 909 according to the encoded signal.

  The modulated signal is received by an antenna unit 222 that is electrically connected to an interrogator (also referred to as a reader / writer) 223. The received signal is analyzed by an interrogator (also referred to as a reader / writer) 223, and unique data such as the ID number of the semiconductor device 931 created using the present invention can be recognized.

  In a wireless communication system using a semiconductor device 931 capable of wireless communication using an IC created using the present invention, a semiconductor device 931, an interrogator (also referred to as a reader / writer) having a known configuration, and an interrogator (reader) An antenna that is electrically connected to an interrogator (also referred to as a reader / writer) and a control terminal that controls an interrogator (also referred to as a reader / writer) can be used. A communication method between the semiconductor device 931 and an antenna electrically connected to an interrogator (also referred to as a reader / writer) is unidirectional communication or bidirectional communication, and includes a space division multiplexing method and a polarization plane division multiplexing method. Any of frequency division multiplexing, time division multiplexing, code division multiplexing, and orthogonal frequency division multiplexing can be used.

  The wireless signal is a signal obtained by modulating a carrier wave. The modulation of the carrier wave is analog modulation or digital modulation, and may be any of amplitude modulation, phase modulation, frequency modulation, and spread spectrum.

  The frequency of the carrier wave is 300 GHz to 3 THz which is a submillimeter wave, 30 GHz to 300 GHz which is a millimeter wave, 3 GHz to 30 GHz which is a microwave, 300 MHz to 3 GHz which is an ultrashort wave, 30 MHz to 300 MHz which is an ultrashort wave, and 3 MHz which is a short wave. Any frequency of ˜30 MHz, medium wave of 300 KHz to 3 MHz, long wave of 30 KHz to 300 KHz, and super long wave of 3 KHz to 30 KHz can be used.

  Note that this embodiment can be used in combination with the embodiment mode and other embodiments if necessary.

  In this embodiment, an example in which an external antenna is attached to a semiconductor device formed using the present invention will be described with reference to FIGS. 24 (A) to 24 (E) and FIGS. 25 (A) to 25 (B). explain.

  FIG. 24A shows the semiconductor device covered with a single antenna. An antenna 1001 is formed over a substrate 1000, and a semiconductor device 1002 formed using the present invention is electrically connected. In FIG. 24A, the periphery of the semiconductor device 1002 is covered with the antenna 1001. However, the entire surface of the substrate is covered with the antenna 1001, and the semiconductor device 1002 including electrodes is attached thereon. Also good.

  FIG. 24B illustrates an example of a coil antenna in which an antenna is arranged around a semiconductor device. An antenna 1004 is formed over a substrate 1003 and a semiconductor device 1005 formed using the present invention is electrically connected. The arrangement of the antennas is an example and is not limited to this.

  FIG. 24C illustrates a high frequency antenna. An antenna 1007 is formed over a substrate 1006, and a semiconductor device 1008 formed using the present invention is electrically connected.

  FIG. 24D illustrates an antenna that is 180 degrees omnidirectional (same reception is possible from any direction). An antenna 1010 is formed over a substrate 1009 and a semiconductor device 1011 formed using the present invention is electrically connected.

  FIG. 24E shows an antenna elongated in a rod shape. An antenna 1013 is formed over a substrate 1012, and a semiconductor device 1014 formed using the present invention is electrically connected.

  FIG. 25A illustrates another example of a coil antenna. An antenna 1016 is formed over a substrate 1015, and a semiconductor device 1017 formed using the present invention is electrically connected. Note that one end of the antenna 1016 is connected to the semiconductor device 1017, and the other end of the antenna 1016 is connected to a wiring 1018 formed in a different process from the antenna 1016. The semiconductor device 1017 is electrically connected. Note that although the wiring 1018 is formed above the antenna 1016 in FIG. 25A, it may be formed below.

  FIG. 25B illustrates another example of a coil antenna. An antenna 1026 is formed over a substrate 1025, and a semiconductor device 1027 formed using the present invention is electrically connected. Note that one end of the antenna 1026 is connected to the semiconductor device 1027, and the other end of the antenna 1026 is connected to a wiring 1028 formed in a different process from the antenna 1026, The semiconductor device 1027 is electrically connected. Note that although the wiring 1028 is formed above the antenna 1026 in FIG. 25B, it may be formed below.

  The semiconductor device formed by using the present invention and connection to these antennas can be performed by a known method. For example, the antenna and the semiconductor device may be connected using wire bonding connection or bump connection, or a method may be adopted in which one surface of the circuit formed as a chip is attached to the antenna as an electrode. In this method, it can be attached using an ACF (anisotropy conductive film).

  The length required for the antenna differs depending on the frequency used for reception. For example, when the frequency is 2.45 GHz, the length may be about 60 mm (1/2 wavelength) if a half-wave dipole antenna is provided, and about 30 mm (¼ wavelength) if a monopole antenna is provided.

  Note that the example shown in this embodiment is just an example, and does not limit the shape of the antenna. The present invention can be implemented with any shape of antenna. The present embodiment can be realized by using a configuration including any combination of the embodiment mode and other embodiments.

  In this example, a method for forming a split region which is different from that in Embodiment Mode 1 is described with reference to FIGS.

  In the first embodiment, as shown in FIG. 9B, the electrode 110 is in contact with the electrolytic solution through the contact hole 168 formed in the third interlayer insulating film 135. However, in this embodiment, a part of the insulating film is removed in advance to form an opening, and the electrode or wiring formed in the opening is removed by dipping in an electrolytic solution while applying a voltage.

  As shown in FIG. 26A, the insulating film 251 is provided with an opening 252. Further, an electrode or wiring 253 is formed in the opening 252. Note that although the electrode or wiring 253 is formed over the insulating film 251 in FIG. 26A, the insulating film 251 may be formed over the electrode or wiring 253 if necessary, and then the opening 252 may be formed. Good.

  Next, the electrode or wiring 253 in the opening 252 is immersed in an electrolytic solution and dissolved by applying a voltage. Thus, a divided region 254 is formed (see FIG. 26B). The materials shown in Table 1 may be used for the electrode or wiring 253 and the electrolyte.

  Next, an electrode or wiring 255 is formed in the dividing region 254. The electrical connection between the electrodes or wirings 253 and 255 is cut off by the dividing region 254.

  Note that this embodiment can be combined with the embodiment mode and other embodiments if necessary.

  The semiconductor device according to the present invention can be used as an IC tag used as a product packaging box or a tag attached to a product in the distribution field. In addition, it can be used as an IC tag attached to a passenger's baggage in airplane or rail transport. Furthermore, in the medical field, for example, by attaching to a medical chart, the medical chart can be handled accurately and quickly. The semiconductor device of the present invention can be used in all fields in the ubiquitous society.

  Since these IC tags need to store identification information individually, by applying the present invention, the productivity of IC tags storing identification information in advance is improved, and the manufacturing time and manufacturing cost are reduced. It becomes possible.

Sectional drawing of the semiconductor device of this invention. The figure which shows the outline | summary of an individual authentication system. The block diagram which shows the structure of the conventional semiconductor device. The block diagram which shows the structure of the conventional semiconductor device. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device of the present invention. Sectional view of the semiconductor device of the present invention 1 is a circuit diagram of a semiconductor device of the present invention. 1 is a block diagram illustrating a configuration of a semiconductor device of the present invention. 1 is a block diagram illustrating a configuration of a semiconductor device of the present invention. 4 is a block diagram illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 1 is a top view of a semiconductor device of the present invention. 1 is a top view of a semiconductor device of the present invention. 1 is a top view of a semiconductor device of the present invention.

Explanation of symbols

11 Memory cell array 14 Output line 15 Column decoder 16 Row decoder 17 Control line 22 High voltage power supply (VDD)
23 Low voltage power supply (VSS or GND)
24 bit line 25 bit line 27 wiring 28 wiring 101 semiconductor film 102 crystalline semiconductor film 103 gate electrode 103a lower gate electrode 103b upper gate electrode 104 gate electrode 104a lower gate electrode 104b upper gate electrode 109 electrode 110 electrode 111 linear beam 113 electrode 114 Electrode 115 Conductive film 116 Conductive film 118 TFT
119 TFT
120 TFT
121 TFT
125 impurity region 126 impurity region 127 impurity region 128 impurity region 131 island-like semiconductor film 132 island-like semiconductor film 135 interlayer insulating film 151 substrate 152 gate insulating film 153 base film 154 gate insulating film 155 interlayer insulating film 156 interlayer insulating film 161 channel formation Region 162a Low-concentration impurity region 162b Low-concentration impurity region 163 Region 164 Region 165 Contact hole 166 Contact hole 167 Contact hole 168 Contact hole 169 Dividing region 171 Side wall 171a Side wall 171b Side wall 175 Wiring 176 Wiring 177 Wiring 178 Wiring 181 Channel formation Region 182a Low-concentration impurity region 182b Low-concentration impurity region 183 Region 184 Region 191 Side wall 191a Side wall 191b Sidewall 200 Semiconductor device 201 Antenna circuit 202 Rectifier circuit 203 Stable power supply circuit 205 Modulation circuit 206 Amplifier 207 Logic circuit 208 Amplifier 209 Logic circuit 211 Memory circuit 211 Memory circuit 212 Memory control circuit 213 Demodulation circuit 221 Semiconductor device 222 Antenna unit 223 Interrogator 224 Bag 241 Antenna coil 242 Capacitance 243 Diode 245 Capacitance 251 Insulating film 252 Opening 253 Electrode or wiring 254 Dividing region 255 Electrode or wiring 401 Gate wiring 402 Wiring 403 Wiring 404 Wiring 405 Wiring 407 Wiring 411 TFT
412 Island-like semiconductor film 421 TFT
422 Island-like semiconductor film 431 Power supply line 432 Wiring 433 Power supply line 434 Wiring 443 Gate electrode 443a Lower gate electrode 443b Upper gate electrode 444 Gate electrode 444a Lower gate electrode 444b Upper gate electrode 451 Substrate 453 Base film 454 Gate insulating film 455 Interlayer insulating film 456 interlayer insulating film 458 interlayer insulating film 461 channel formation region 462a low concentration impurity region 462b low concentration impurity region 463 region 464 region 471a sidewall 471b sidewall 481 channel formation region 483 region 484 region 491a sidewall 491b sidewall 601 substrate 602 Base film 603 Linear beam 604 Semiconductor film 605 Crystalline semiconductor film 611 Island-like semiconductor film 612 Island-like semiconductor film 613 Island-like semiconductor film 614 Island-like semiconductor film 615 Gate insulating film 616 resist 617 resist 618 resist 621 gate electrode 621a lower gate electrode 621b upper gate electrode 622 gate electrode 622a lower gate electrode 622b upper gate electrode 623 gate electrode 623a lower gate electrode 623b upper gate electrode 624 gate electrode 624a lower gate electrode 624b Upper gate electrode 626 Side wall 626a Side wall 626b Side wall 627 Side wall 627a Side wall 627b Side wall 628 Side wall 628a Side wall 628b Side wall 629 Side wall 629a Side wall 629b Side wall 631 Channel formation region 632a Low concentration impurity region 632b Low concentration impurity region 633 region 634 region 642 a low-concentration impurity region 642b low-concentration impurity region 643 region 644 region 652a low-concentration impurity region 652b low-concentration impurity region 653 region 654 region 661 channel formation region 663 region 664 region 671 interlayer insulating film 672 interlayer insulating film 673 contact hole 674 contact hole 675 Contact hole 676 Contact hole 677 Contact hole 678 Contact hole 679 Contact hole 680 Contact hole 681 Electrode 682 Electrode 684 Electrode 685 Electrode 686 Electrode 687 Electrode 691 TFT
692 TFT
693 TFT
694 TFT
695 CMOS circuit 697 Interlayer insulating film 802 Peeling layer 803 Base film 804 Base film 806 Interlayer insulating film 807 Protective layer 808 Groove 811 Electrode 812 Electrode 813 Electrode 815 Electrode 816 Electrode 821 Support 822 Adhesive 851 Contact hole 852 Contact hole 853 Contact hole 854 Contact hole 855 Contact hole 856 Contact hole 857 Contact hole 860 Dividing region 871 Wiring 872 Wiring 873 Wiring 874 Wiring 875 Wiring 876 Wiring 877 Wiring 900 Mask ROM
901 Signal output control circuit 902 CRC circuit 903 Clock generation circuit 904 Code extraction circuit 905 Code determination circuit 906 Rectification circuit 907 Demodulation circuit 908 Analog amplifier 909 Modulation circuit 911 Reset circuit 912 Retention capacity 913 Rectification circuit 914 High frequency circuit 915 Power supply circuit 917 Antenna 920 Memory cell array 921 column decoder 922 row decoder 931 semiconductor device 951 circuit 955 computer 1000 substrate 1001 antenna 1002 semiconductor device 1003 substrate 1004 antenna 1005 semiconductor device 1006 substrate 1007 antenna 1008 semiconductor device 1009 substrate 1010 antenna 1011 semiconductor device 1012 substrate 1013 antenna 1014 semiconductor device 1015 Substrate 1016 Antenna 1017 Semiconductor device 1018 Wiring 1 025 Substrate 1026 Antenna 1027 Semiconductor device 1028 Wiring 1601 Substrate 1602 Semiconductor device 1603 Conductive particles 1604 Resin 1605 Terminal portion 1610 Substrate 1611 Substrate 1612 Antenna

Claims (8)

On the board
A thin film transistor having a channel formation region, an island-shaped semiconductor film having a source region or a drain region, a gate insulating film, and a gate electrode;
A first interlayer insulating film on the thin film transistor;
A first electrode formed on the first interlayer insulating film and electrically connected to one of the source region or the drain region;
A second electrode formed on the first interlayer insulating film and electrically connected to the other of the source region or the drain region;
A second interlayer insulating film formed on the first interlayer insulating film, the first electrode, and the second electrode;
A first wiring formed on the second interlayer insulating film and electrically connected to one of the first electrode or the second electrode;
A second wiring formed on the second interlayer insulating film and not electrically connected to the other of the first electrode or the second electrode;
Have
2. The semiconductor device according to claim 1, wherein the second wiring and the other of the first electrode or the second electrode are not electrically connected by a dividing region formed in the second interlayer insulating film. On the board
A first thin film transistor having a first channel formation region, a first island-shaped semiconductor film having a first source region or a drain region, a gate insulating film, and a first gate electrode;
A second thin film transistor having a second channel formation region, a second island-shaped semiconductor film having a second source region or a drain region, the gate insulating film, and a second gate electrode;
A first interlayer insulating film on the first and second thin film transistors;
A first electrode formed on the first interlayer insulating film and electrically connected to one of the first source region or the drain region;
A second electrode formed on the first interlayer insulating film and electrically connected to the other of the first source region or the drain region;
A third electrode formed on the first interlayer insulating film and electrically connected to one of the second source region or the drain region;
A fourth electrode formed on the first interlayer insulating film and electrically connected to the other of the second source region or the drain region;
A first interlayer insulating film, a second interlayer insulating film formed on the first to fourth electrodes, and
A first wiring formed on the second interlayer insulating film and electrically connected to the first electrode;
A second wiring formed on the second interlayer insulating film and electrically connected to the second electrode;
A third wiring formed on the second interlayer insulating film and not electrically connected to the third electrode;
A fourth wiring formed on the second interlayer insulating film and electrically connected to the fourth electrode;
Have
The semiconductor device, wherein the third wiring and the third electrode are not electrically connected by a dividing region formed in the second interlayer insulating film. In claim 1,
The thin film transistor is used in a nonvolatile memory circuit. In claim 2,
The semiconductor device, wherein the first and second thin film transistors are used in a nonvolatile memory circuit. On the substrate, an island-shaped semiconductor film, a gate insulating film, and a gate electrode are formed,
In the island-like semiconductor film, an impurity imparting one conductivity is added to form a channel formation region, a source region or a drain region in the island-like semiconductor film,
Covering the island-shaped semiconductor film, the gate insulating film, and the gate electrode, forming a first interlayer insulating film,
Forming a first electrode electrically connected to one of the source region and the drain region on the first interlayer insulating film;
Forming a second electrode electrically connected to the other of the source region or the drain region on the first interlayer insulating film;
Covering the first interlayer insulating film, the first electrode, and the second electrode, forming a second interlayer insulating film;
Forming a first contact hole reaching the first electrode in the second interlayer insulating film;
Forming a second contact hole reaching the second electrode in the second interlayer insulating film;
The first electrode and the second electrode are immersed in an electrolytic solution, a voltage is applied to one of the first electrode and the second electrode, and one of the first electrode and the second electrode is dissolved and divided. Forming a region,
On the second interlayer insulating film, a first wiring that is not electrically connected to one of the first electrode or the second electrode is formed in one of the first or second contact hole. ,
A second wiring electrically connected to the other of the first electrode or the second electrode is formed on the second interlayer insulating film via the other of the first or second contact hole. A method for manufacturing a semiconductor device. Forming a first island-shaped semiconductor film, a second island-shaped semiconductor film, a gate insulating film, a first gate electrode, and a second gate electrode on a substrate;
An impurity imparting one conductivity is added to the first and second island-shaped semiconductor films, and a first channel formation region, a first source region, or Forming a drain region in the second island-shaped semiconductor film by forming a second channel formation region, a second source region, or a drain region;
Covering the first and second island-shaped semiconductor films, the gate insulating film, and the first and second gate electrodes, forming a first interlayer insulating film,
Forming a first electrode electrically connected to one of the first source region and the drain region on the first interlayer insulating film;
Forming a second electrode electrically connected to the other of the first source region or the drain region on the first interlayer insulating film;
Forming a third electrode electrically connected to one of the second source region or the drain region on the first interlayer insulating film;
Forming a fourth electrode electrically connected to the other of the second source region or the drain region over the first interlayer insulating film;
Forming a second interlayer insulating film covering the first interlayer insulating film and the first to fourth electrodes;
Forming a first contact hole reaching the first electrode in the second interlayer insulating film;
Forming a second contact hole reaching the second electrode in the second interlayer insulating film;
Forming a third contact hole reaching the third electrode in the second interlayer insulating film;
Forming a fourth contact hole reaching the fourth electrode in the second interlayer insulating film;
Immersing the first to fourth electrodes in an electrolyte, applying a voltage to the third electrode, dissolving the third electrode to form a divided region;
Forming a first wiring electrically connected to the first electrode through the first contact hole on the second interlayer insulating film;
Forming a second wiring electrically connected to the second electrode through the second contact hole on the second interlayer insulating film;
Forming a third wiring not electrically connected to the third electrode in the third contact hole on the second interlayer insulating film;
A method for manufacturing a semiconductor device, comprising: forming a fourth wiring electrically connected to the fourth electrode through the fourth contact hole on the second interlayer insulating film. In claim 5,
The method for manufacturing a semiconductor device, wherein the thin film transistor is used in a nonvolatile memory circuit. In claim 6,
The method for manufacturing a semiconductor device, wherein the first and second thin film transistors are used in a nonvolatile memory circuit.

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