JP2008034539A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cope with the problem that the constituent element of a ferroelectric film is evaporated by heat treatment. <P>SOLUTION: This semiconductor device comprises a semiconductor substrate, an MOS transistor formed on the semiconductor substrate, a lower interlayer insulating film covering the MOS transistor, a ferroelectric capacitor formed above the lower interlayer insulating film and including a capacitor lower electrode, an oxide ferroelectric film formed on the capacitor lower electrode, and a capacitor upper electrode formed on the oxide ferroelectric film, a first insulating capacitor protective film covering at least the upper electrode and the exposed surface of the oxide ferroelectric film and having the function for suppressing the transmission of a reducing material, an evaporation compensating film covering the first insulating capacitor protective film and containing at least one element among the constituent elements other than oxygen of the oxide ferroelectric substance, and a second insulating capacitor protective film covering the evaporation compensating film and having the function for suppressing the transmission of a reducing material. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a ferroelectric capacitor and a manufacturing method thereof.

  In recent years, with the advancement of digital technology, there is a high demand for processing or storing a large amount of data at high speed. For this reason, high integration and high performance of semiconductor devices used in electronic devices are required. For example, in order to realize high integration of dynamic random access memory (DRAM), a technique using a ferroelectric material film or a high dielectric constant material film as a capacitor dielectric film instead of a silicon oxide film or a silicon nitride film is widely used. Researched and developed.

  Ferroelectric memory (FeRAM) using a ferroelectric material film with spontaneous polarization characteristics as a capacitor dielectric film is actively researched in order to realize a non-volatile memory that can be written and read at a lower voltage and higher speed. Has been developed.

  A ferroelectric memory stores information using the hysteresis characteristic of a ferroelectric capacitor in which a ferroelectric film is sandwiched between a pair of electrodes. The ferroelectric film generates polarization according to the applied voltage between the electrodes, and retains spontaneous polarization even when the applied voltage is removed. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Information can be read if spontaneous polarization is detected. A ferroelectric memory operates at a lower voltage than a flash memory, and can save power and write at high speed.

  FeRAM is roughly classified into a planar type and a stack type depending on its structure. In the planar type, the MOS transistor formed on the semiconductor substrate and the capacitor lower electrode are electrically connected via the metal wiring above the capacitor, and the area occupied by the capacitor tends to increase.

  In the stacked FeRAM, a capacitor lower electrode is formed on a conductive plug connected to a source / drain region of a MOS transistor, and the lower electrode and the MOS transistor are electrically connected through the conductive plug. According to such a structure, the area occupied by the capacitor can be reduced as compared with the planar type, which is advantageous for miniaturization of the FeRAM. The stack type FeRAM is required to exhibit excellent ferroelectric capacitor characteristics even when miniaturized.

  When the upper electrode of the ferroelectric capacitor is formed or when the capacitor is patterned, the ferroelectric film is physically damaged by high energy sputtering particles, etching gas, or the like. When the ferroelectric film is damaged, a part of the crystal structure of the ferroelectric film is destroyed, and the characteristics of the capacitive element are deteriorated. Various countermeasures have been proposed in order to suppress the damage of the capacitor and recover the characteristic deterioration.

  Japanese Patent Laid-Open No. 2003-332536 laminates a lower electrode film, a ferroelectric film, and an upper electrode film, patterns the upper electrode film, heat-treats in an oxygen atmosphere, patterns the ferroelectric film, and heat-treats in an oxygen atmosphere And patterning the lower electrode film, performing heat treatment in an oxygen atmosphere, and then depositing a hydrogen diffusion prevention film formed of aluminum oxide, titanium oxide, PLZT, or PZT in order to block the entry of hydrogen. To do.

  By heat treatment in an oxygen atmosphere, oxygen is supplied to the ferroelectric film to restore crystallinity. In order to protect the ferroelectric film from hydrogen degradation, an aluminum oxide film or the like is formed as a hydrogen diffusion preventing film so as to cover the capacitor.

  Japanese Patent Laid-Open No. 2001-111007 covers the surface of a ferroelectric capacitor with a volatilization preventive film such as titanium oxide having a function of preventing volatilization of oxygen from the capacitor dielectric film, and an oxidation that prevents diffusion of hydrogen entering from the outside on the film. A capsule structure covered with a hydrogen intrusion prevention film such as aluminum is proposed.

  Japanese Patent Application Laid-Open No. 2005-183843 discloses that, in order to recover the deterioration of the PZT ferroelectric film, after forming the ferroelectric capacitor, an aluminum oxide protective film is formed, and recovery annealing is performed in an oxygen atmosphere to supply oxygen to PZT. At the same time, a method of suppressing the evaporation of Pb from PZT and further forming a second aluminum oxide protective film thereon is proposed.

  Japanese Patent Laid-Open No. 2003-273332 proposes a method of covering a PZT ferroelectric capacitor with two types of aluminum oxide films having different carbon contents.

JP 2003-332536 A JP 2001-111007 PR Japanese Laid-Open Patent Publication No. 2005-183843 JP 2003-273332 A

  If heat treatment is performed after patterning the ferroelectric film, the constituent elements of the ferroelectric film may evaporate, and vacancies may be formed in the ferroelectric film. When a ferroelectric film such as PZT or PLZT is used, Pb deficiency may occur due to heat treatment. Such deficiency degrades the switching characteristics of the ferroelectric capacitor, and degrades the initial characteristics and the retention characteristics. With the miniaturization of semiconductor integrated circuits, the area ratio of the ferroelectric film side surface of the ferroelectric capacitor is increasing. Therefore, the problem of evaporation of the constituent elements of the ferroelectric film increases with the miniaturization of the semiconductor integrated circuit.

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can cope with the problem of evaporation of constituent elements of a ferroelectric film by heat treatment.

According to one aspect of the present invention,
A semiconductor substrate;
A MOS transistor formed on the semiconductor substrate;
A lower interlayer insulating film covering the MOS transistor;
A capacitor lower electrode formed on the lower interlayer insulating film; an oxide ferroelectric film formed on the capacitor lower electrode; and a capacitor upper electrode formed on the oxide ferroelectric film. Including a ferroelectric capacitor,
A first insulating capacitor protective film that covers at least the exposed surface of the upper electrode and the oxide ferroelectric film and has a function of suppressing transmission of a reducing substance;
An evaporation compensation film that covers the first insulating capacitor protective film and contains an element that is most easily evaporated among constituent elements other than oxygen of the oxide ferroelectric;
A second insulating capacitor protective film covering the evaporation compensation film and having a function of suppressing transmission of a reducing substance;
A semiconductor device is provided.

According to another aspect of the invention,
(A) forming a MOS transistor on a semiconductor substrate;
(B) forming a lower interlayer insulating film on the semiconductor substrate so as to cover the MOS transistor;
(C) Laminating a capacitor lower electrode film above the lower interlayer insulating film, an oxide ferroelectric capacitor dielectric film on the capacitor lower electrode, and a capacitor upper electrode film on the capacitor dielectric film. Process,
(D) patterning at least the capacitor upper electrode film;
(E) forming a first insulating capacitor protective film having a function of covering the exposed surface of the capacitor upper electrode film and the capacitor dielectric film and suppressing permeation of a reducing substance;
(F) forming an evaporation compensation film that covers the first insulating capacitor protective film and includes an element that is most easily evaporated among constituent elements other than oxygen of the oxide ferroelectric;
(G) After the step (f), a step of heat-treating in an oxidizing atmosphere;
(H) After the step (g), forming a second insulating capacitor protective film having a function of covering the evaporation compensation film and suppressing the permeation of the reducing substance;
A method of manufacturing a semiconductor device having the above is provided.

  By covering the exposed surface of the ferroelectric film with a capacitor protective film having a hydrogen diffusion preventing function, and further forming an evaporation protection film containing the most easily evaporated element among the constituent elements other than oxygen of the ferroelectric film, The constituent element introduced from the evaporation protection film compensates for the constituent element evaporated from the ferroelectric film. By covering the evaporation compensation film with a protective film having a function of preventing hydrogen diffusion, it is possible to reduce the escape of constituent elements evaporated from the evaporation compensation film to the outside.

  Embodiments of the present invention will be described below with reference to the drawings. When one memory cell is constituted by one switching transistor and one capacitor, the current terminal regions of the transistors of the two memory cells can be shared. For example, two memory cells can be formed by connecting the source regions of two MOS transistors to a bit line in common and connecting a capacitor to each drain region. The substrate area utilization rate can be improved. This is a connection format widely used in DRAM. This connection type is also adopted in the embodiments of the present invention described below.

  With reference to FIGS. 1A to 1T, description will be made on a stacked FeRAM manufacturing method according to a first embodiment of the present invention. The configuration of the semiconductor device manufactured by this manufacturing method is also the first embodiment of the present invention.

  As shown in FIG. 1A, an element isolation groove is formed in the surface layer portion of a substrate 1 made of n-type or p-type silicon, and the groove surface is oxidized to form a liner, and then oxidized by, for example, high density plasma (HDP) CVD. A silicon film is buried, unnecessary portions are removed by CMP, a mask / stopper is removed, an element isolation region 2 is formed by shallow trench isolation (STI), and an active region is defined. The element isolation region may be formed by LOCOS instead of STI. A p-type well 3 is formed by implanting p-type impurities into the surface layer portion of the active region.

  Two MOS transistors 5 are formed in each active region constituted by a p-type well, and one ferroelectric capacitor is connected to each MOS transistor. Hereinafter, a method for forming the MOS transistor 5 will be briefly described.

A SiO ₂ film to be a gate insulating film is formed by thermally oxidizing the surface layer portion of the active region. A gate electrode 5G is formed by forming and patterning a silicon film made of amorphous or polycrystalline silicon on the substrate. In a plan view, two gate electrodes cross one active region substantially in parallel. The gate electrode also serves as a word line.

  N-type impurities are ion-implanted using the gate electrode 5G as a mask to form extension portions of the source region 5S and the drain region 5D. Sidewall spacers are formed on the side surfaces of the gate electrode 5G using silicon oxide or the like. By using the gate electrode 5G and the sidewall spacer as a mask, n-type impurities are ion-implanted to form a deep high concentration region of the source region 5S and the drain region 5D. Through the steps so far, the MOS transistor 5 is formed.

  Next, a film made of a refractory metal such as cobalt (Co) is formed on the substrate by sputtering. By performing heat treatment, the refractory metal film reacts with silicon, and a refractory metal silicide film is formed on the upper surfaces of the gate electrode 5G, the source region 5S, and the drain region 5D. Thereafter, the unreacted refractory metal film is removed and further heat-treated as necessary to form a silicide film 6. The resistance of the source / drain regions 5S and 5D is reduced, and the resistance of the gate electrode is also reduced.

A cover insulating film 11 of SiON having a thickness of 200 nm is formed on the substrate so as to cover the MOS transistor 5 by plasma CVD. Further, an SiO ₂ interlayer insulating film 12 having a thickness of 1000 nm, for example, is formed on the cover insulating film 11. The interlayer insulating film 12 is formed by plasma CVD using, for example, oxygen (O ₂ ) and tetraethylorthosilicate (TEOS). Thereafter, the surface of the interlayer insulating film 12 is planarized by chemical mechanical polishing (CMP). After planarization, CMP is controlled so that the thickness of the flat portion of the substrate is about 700 nm.

  Contact holes that penetrate through the interlayer insulating film 12 and the cover insulating film 11 to reach the silicide film 6 on the drain region 5D and the silicide film 6 on the source region 5S are formed. The diameter of the contact hole is, for example, 0.25 μm.

  By sputtering, the inner surface of the contact hole and the upper surface of the interlayer insulating film 12 are covered with two layers of a Ti film having a thickness of 30 nm and a TiN film having a thickness of 20 nm. Further thereon, a W film is formed until the contact hole is completely filled by CVD. The thickness of the W film may be 300 nm, for example. By removing the excess W film, TiN film, and Ti film on the interlayer insulating film 12 by CMP, in the contact hole, an adhesion layer composed of a Ti film and a TiN film, and a conductive plug 15 composed of a W film, Leave 16. Conductive plugs 15 and 16 are connected to drain region 5D and source region 5S, respectively.

As shown in FIG. 1B, an antioxidant film 21 made of SiON having a thickness of 130 nm is formed on the interlayer insulating film 12 by plasma CVD. Instead of SiON, an antioxidant film 21 made of SiN or AlO may be formed. Further thereon, an interlayer insulating film 22 made of SiO ₂ and having a thickness of 300 nm is formed by plasma CVD using O ₂ and TEOS.

  As shown in FIG. 1C, contact holes are formed in the interlayer insulating film 22 and the antioxidant film 21 to expose the conductive plugs 15 therebelow. The inner surface of the contact hole is covered with an adhesive film, and W is embedded in the contact hole to form a conductive plug 25. The conductive plug 25 can be formed by the same method as the conductive plug 15 below. A poly-Si plug can be used instead of the W plug.

  The CMP for removing the excess W film and the adhesion film is performed under the condition that the polishing rate of the W film and the adhesion film is faster than the polishing rate of the interlayer insulating film 22. For example, SSW2000 manufactured by Cabot Microelectronics Corporation is used as the slurry. Further, over-polishing is performed slightly so that no adhesion film or W film remains on the interlayer insulating film 22. For this reason, the upper surface of the conductive plug 25 becomes lower than the upper surface of the surrounding interlayer insulating film 22, and the dent 25a is generated. The depth of the recess 25a is, for example, 20 nm to 50 nm, and typically about 50 nm.

After the CMP, the upper surface of the interlayer insulating film 22 and the upper surface of the conductive plug 25 are exposed to ammonia (NH ₃ ) plasma. This plasma processing is performed using, for example, a parallel plate type plasma processing apparatus under the following conditions.
The distance between the substrate surface and the counter electrode is about 9 mm (350 mils);
Pressure 266 Pa (2 Torr);
-Substrate temperature: 400 ° C;
NH ₃ gas flow rate: 350 sccm;
-RF power of 13.56 MHz supplied to the substrate side electrode 100 W;
-350 kHz RF power 55 W supplied to the counter electrode;
・ Processing time 60 seconds.
By NH ₃ plasma treatment, NH groups are bonded to oxygen atoms on the surface of the silicon oxide film.

As shown in FIG. 1D, a Ti film having a thickness of 100 nm is formed on the plasma-treated surface by DC sputtering. The sputtering conditions are, for example, as follows.
-Target Ti;
-Distance between substrate and target 60mm;
Ar gas pressure 0.15 Pa;
-Substrate temperature 20 ° C;
・ Sputter power 2.6 kW;
・ Deposition time 35 seconds.
Since NH groups are bonded to oxygen atoms on the surface of the silicon oxide film, Ti atoms attached to the surface can freely migrate on the surface without being captured by oxygen atoms. As a result, a Ti film having a hexagonal close-packed structure on the surface of the interlayer insulating film and self-organized in (002) orientation is obtained.

Next, rapid thermal annealing (RTA) is performed in a nitrogen atmosphere. The RTA conditions are, for example, as follows.
-Annealing temperature 650 ° C;
・ Processing time 60 seconds.
By this annealing, the Ti film is nitrided to obtain the base conductive film 30 made of TiN having a face-centered cubic structure and (111) orientation. Note that the thickness of the base conductive film 30 may be in the range of 100 nm to 300 nm. At this stage, a depression is generated above the conductive plug 25 on the surface of the underlying conductive film 30 reflecting the depression 25a on the underlying surface. The surface of the underlying conductive film 30 is planarized by CMP. For example, SSW2000 manufactured by Cabot Microelectronics Corporation is used as the slurry. The thickness of the underlying conductive film 30 after CMP is set to 50 nm to 100 nm, typically about 50 nm.

The ground conductive layer subjected to CMP has a crystal near the surface distorted by polishing. If the lower electrode of the ferroelectric capacitor is formed on the underlying conductive layer as it is, the strain of the underlying conductive layer is transmitted to the lower electrode, which affects the crystallinity of the lower electrode and the ferroelectric film thereon. give. In order to avoid this, the surface of the planarized underlying conductive film 30 is exposed to NH ₃ plasma after CMP. Thereby, the crystal distortion generated in the surface layer portion of the underlying conductive film 30 during CMP is repaired.

  Note that any of tungsten, silicon, and copper can be used as the base conductive film instead of titanium nitride. However, a combination of ammonia plasma treatment and a TiN film is preferable for improving crystallinity.

As shown in FIG. 1E, a Ti film having a thickness of, for example, 20 nm is formed by sputtering on the underlying conductive film 30 from which crystal distortion has been eliminated by NH ₃ plasma. This Ti film becomes a crystalline conductive film functioning as an adhesion film. Further, RTA is performed in a nitrogen atmosphere. The RTA conditions are, for example, as follows.
-Annealing temperature 650 ° C;
・ Processing time 60 seconds.
By this annealing, the Ti film is nitrided, and the crystallinity improving film 31 made of TiN having a face-centered cubic structure and (111) orientation is obtained.

  As the crystallinity improving film, Ir, Pt or the like can be used instead of TiN. The thickness is preferably about 20 nm.

As shown in FIG. 1F, an oxygen barrier film 33 made of TiAlN having a thickness of 100 nm is formed on the crystallinity improving film 31 by reactive sputtering using a TiAl alloy target. The sputtering conditions are, for example, as follows.
-Ar gas flow rate 40 sccm;
-N ₂ gas flow rate 10 sccm;
Pressure 253.3 Pa;
-Substrate temperature 400 ° C;
-Sputter power 1.0 kW.

A lower electrode 36 made of Ir and having a thickness of 100 nm is formed on the oxygen barrier film 33 by sputtering. The sputtering conditions are, for example, as follows.
-Ar atmosphere pressure 0.11 Pa;
-Substrate temperature 500 ° C;
・ Sputter power 0.5kW.

After the film formation of the lower electrode 36, heat treatment by RTA is performed in an Ar atmosphere and at a temperature higher than the film formation temperature of the lower electrode 36. Specifically, RTA is performed under the following conditions.
-Temperature 650 ° C;
・ Processing time 60 seconds.
This heat treatment can improve the crystallinity of the lower electrode. The in-plane distribution of crystallinity can also be improved. By this heat treatment, Al, which is a constituent element of the oxygen barrier film 33, reacts with Ir, which is a constituent element of the upper electrode 36, and an intermediate layer 34 made of an IrAl alloy is formed at the interface between them. The intermediate layer 34 improves the adhesion between the oxygen barrier film 33 and the upper electrode 36. Note that the atmosphere of the heat treatment may be replaced with other inert gas such as nitrogen or He instead of Ar. As the lower electrode, a platinum group metal such as Ir or Pt, a conductive oxide such as PtO, IrO _x , or SrRuO ₃ , or a laminate thereof can be used. When the lower electrode 36 is formed of Pt or PtO, an intermediate layer 34 containing a PtAl alloy is formed. When the lower electrode 36 is formed of SrRuO ₃ , an intermediate layer 34 containing a RuAl alloy is formed.

  As shown in FIG. 1G, a ferroelectric film 37 made of PZT is formed on the lower electrode 36 by metal organic chemical vapor deposition (MOCVD). Hereinafter, a method for forming the ferroelectric film 37 will be described.

As the Pb raw material, a liquid raw material having a concentration of 0.3 mol / liter in which Pb (C ₁₁ H ₁₉ O ₂ ) ₂ [Pb (DPM) 2] is dissolved in tetrahydrofuran (THF) is used. As the Zr raw material, a liquid raw material having a concentration of 0.3 mol / liter in which Zr (C ₉ H ₁₅ O ₂ ) ₄ [Zr (dmhd) 4] is dissolved in THF is used. As a Ti raw material, Ti (C ₃ H ₇ O) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ [Ti (O—iOr) 2 (DPM) 2] is dissolved in THF and has a concentration of 0.3 mol / liter. Use raw materials. These liquid raw materials are supplied to the vaporizer of the MOCVD apparatus together with the THF solvent at 0.474 ml / min. The flow rates of the Pb raw material, the Zr raw material, and the Ti raw material are 0.326 ml / min, 0.200 ml / min, and 0.200 ml / min, respectively.

  The substrate on which the ferroelectric film 37 is to be formed is loaded into the chamber of the MOCVD apparatus. The pressure in the chamber is 665 Pa (5 Torr), and the substrate temperature is 620 ° C. The vaporized source gas is supplied into the chamber, and film formation is performed for 620 seconds. Thereby, a PZT film having a thickness of 100 nm is formed.

  Next, a second PZT film having an amorphous phase with a thickness of 1 nm to 30 nm, typically 20 nm, is formed by sputtering. By disposing an amorphous phase PZT film, leakage current can be reduced. An amorphous ferroelectric film can also be formed by MOCVD.

  As shown in FIG. 1H, an upper electrode 38 having a three-layer structure including a first conductive oxide film 38a, a second conductive oxide film 38b, and a third conductive oxide film 38c on the ferroelectric film 37. Form.

A first upper electrode 38 a is formed on the ferroelectric film 37. For example, an IrO _x film having a thickness of 20 nm to 70 nm is formed by reactive sputtering in a state of being crystallized at the time of film formation. The film forming conditions are, for example, as follows.
・ Target: Ir
-Substrate temperature during film formation: 300 ° C
・ Deposition gas: Ar + O ₂
Flow rate: [Ar] = 140 sccm, [O ₂ ] = 60 sccm,
Flow rate ratio: [O ₂ ] / [Ar] = 0.43
Sputtering power: about 1 kW to 2 kW.

IrO _x of the first conductive oxide film 38a formed by this reactive sputtering has a composition having a smaller oxygen composition x than the stoichiometric composition (x = 2).

After forming the first conductive oxide film 38a, RTA is performed under the following conditions.
-Processing temperature: 725 ° C;
Atmosphere O ₂ flow rate 20 sccm + Ar flow rate 2000 sccm;
・ Processing time 60 seconds.

  By this heat treatment, the ferroelectric film 37 is completely crystallized, and at the same time, the damage received by the exposure of the PZT film 37 to the plasma when the first conductive oxide film 38a is formed is recovered. Oxygen deficiency is compensated.

On the first conductive oxide film 38a, a second conductive oxide film (IrO _y film) 38b having a thickness of 30 nm to 100 nm, a third conductive oxide film (IrO _z film) having a thickness of 50 to 150 nm, or conductive The noble metal film 38c is formed. Abnormal growth is suppressed by setting the oxygen composition y of the second conductive oxide film to a value close to the stoichiometric composition (2) and the oxygen composition z of the third conductive oxide film to a value lower than y. In addition, the generation of oxygen vacancies can be suppressed.

For example, a second conductive oxide film 38b of an IrO _y film having a thickness of 30 nm to 100 nm is formed on the first conductive oxide film 38a by reactive sputtering. The film forming conditions are, for example, as follows.
・ Target: Ir
-Substrate temperature during film formation: 20 ° C
・ Deposition gas: Ar + O ₂
Flow rate: [Ar] = 100 sccm, [O ₂ ] = 100 sccm,
Flow rate ratio: [O ₂ ] / [Ar] = 1.00
Sputtering power: about 1 kW to 2 kW.

IrO _y of the second conductive oxide film 38b did not grow abnormally, and a clean amorphous film was obtained. IrO _y of the second conductive oxide film 38b has an oxygen composition y higher than the oxygen composition x of the first conductive oxide film IrO _x , y> x, and a value closer to the stoichiometric composition.

After the formation of the second conductive oxide film 38b. RTA is performed under the following conditions.
-Processing temperature: 700 ° C
Atmosphere: O ₂ flow rate 20 sccm + Ar flow rate 2000 sccm,
・ Processing time: 60 seconds
By this heat treatment, the second conductive oxide film 38b is completely crystallized, and at the same time, the adhesion between the first conductive oxide film and the second conductive oxide film is improved.

A third conductive oxide film or noble metal film 38c of IrO _z having a thickness of 50 nm to 150 nm is further formed on the second conductive oxide film 38b of IrO _y . The conditions for forming the conductive oxide film are, for example, as follows.
・ Target: Ir
-Substrate temperature during film formation: 300 ° C
・ Deposition gas: Ar + O ₂
Flow rate: [Ar] = 160 sccm, [O ₂ ] = 40 sccm,
Flow rate ratio: [O ₂ ] / [Ar] = 0.25,
Sputtering power: about 1 kW to 2 kW.

Since the oxygen flow rate is reduced, the third conductive oxide film 38c of IrO _z has a low oxygen composition z, z <y and z <x. Abnormal growth does not occur in the conductive oxide film having a high metallic component. A very clean crystal film was obtained.

The film forming conditions for forming the noble metal film are as follows, for example.
・ Target: Ir,
-Substrate temperature during film formation: 400 ° C
・ Deposition gas: Ar,
-Flow rate: [Ar] = 100 sccm,
Sputtering power: about 1 kw to 2 kw.

The composition of the iridium oxide film was measured by stoichiometric composition (stoichiometry) using a high-resolution RBS (Rutherford backscattering) analyzer HRBSV500. The first iridium oxide film IrO _x formed at an [Ar]: [O ₂ ] flow rate ratio of 140: 60 is x = 1.92, and is in an oxygen-deficient state from the stoichiometric composition (x = 2). is there. The second iridium oxide film IrO _y formed at an [Ar]: [O ₂ ] flow rate ratio of 100: 100 has y = 2.02, almost equal to the stoichiometric composition (y = 2), and slightly oxygen Excessive state. The second iridium oxide film IrO _y formed with the oxygen flow rate ratio slightly decreased and the [Ar]: [O ₂ ] flow rate ratio set to 120: 80 was y = 2.00. The third iridium oxide film IrO _z formed at an [Ar]: [O ₂ ] flow rate ratio of 160: 40 has z = 1.84, and the degree of oxygen deficiency is the most than the stoichiometric composition (z = 2). It is in a high state. When films are formed at the same temperature and the same total flow rate, the oxygen composition seems to be determined by the flow rate ratio [O ₂ ] / [Ar].

The film formation temperature of the second conductive oxide film 38b and the third conductive oxide film 38c is not limited to 300 ° C., and can be selected from a range of 50 ° C. to 500 ° C., for example. However, IrO _z film formed, it is desirable that IrO _z is crystallized in the film forming time. The flow rate and flow rate ratio of the deposition gas can be changed as appropriate in accordance with the deposition temperature.

  Instead of the third conductive oxide film, a noble metal film such as an Ir film or a Ru film can also be used. The upper electrode 38 of the ferroelectric capacitor is formed by combining the first upper electrode 38a, the second upper electrode 38b, and the third upper electrode 38c.

As shown in FIG. 1I, a first hard mask 45 made of TiN and a second hard mask 46 made of SiO ₂ are formed on the upper electrode 38. The first hard mask 45 is formed by sputtering, for example. The second hard mask 46 is formed by, for example, CVD using O ₂ and TEOS.

  As shown in FIG. 1J, the second hard mask 46 is patterned so as to have a planar shape of the ferroelectric capacitor to be formed. Next, the first hard mask 45 is etched using the patterned second hard mask 46 as an etching mask.

As shown in FIG. 1K, the upper electrode 38, the ferroelectric film 37, and the lower electrode 36 (and the intermediate layer 34) are etched using the second hard mask 46 and the first hard mask 45 as an etching mask. This etching is performed, for example, by plasma etching using a mixed gas of HBr, O ₂ , Ar, and C ₄ F ₈ . The composition of the etching gas remaining for the etching target can be selected. The patterned lower electrode 36, ferroelectric film 37, and upper electrode 38 constitute a ferroelectric capacitor 35. During this etching, the surface layer portion of the second hard mask 46 is also etched.

  As shown in FIG. 1L, the second hard mask 46 is removed by dry etching or wet etching. As a result, the first hard mask 45 is exposed. The first hard mask 45 of TiN and the oxygen barrier film 33 of TiAlN are conductive, and the switching charge amount of the ferroelectric capacitor can be measured at this stage.

As shown in FIG. 1M, the oxygen barrier film 33, the crystallinity improving film 31, and the base conductive film 30 in the region where the ferroelectric capacitor 35 is not disposed are etched. For example, in a flow rate ratio, a mixed gas of 5% CF ₄ gas and 95% O ₂ gas is supplied as an etching gas into the downflow plasma etching chamber, and a 2.45 GHz micro gas is supplied to the upper electrode in the chamber. Waves are supplied with high frequency power of 1400 W and dry etching is performed at a substrate temperature of 200 ° C. Alternatively, wet etching using a mixed solution of H ₂ O ₂ , NH ₂ OH, and pure water as an etchant may be performed. At this time, the first hard mask 45 remaining on the upper electrode 38 is also removed, and the upper electrode 38 is exposed.

As shown in FIG. 1N, a first protective film 50 having a hydrogen diffusion preventing function or a hydrogen diffusion suppressing function is sputtered on an exposed surface with an Al ₂ O ₃ film having a thickness of 1 nm to 30 nm, for example, 20 nm. To form. Further, a PZT film 53 having a thickness of 1 nm to 100 nm, for example, a thickness of 10 nm is formed on the alumina film 50 by MOCVD. The MOCVD of the PZT film can be performed in the same manner as the film formation by MOCVD of the PZT film 37 of the ferroelectric capacitor. For example, when a source gas is allowed to act for 62 seconds at a substrate temperature of 620 ° C. under the above-described conditions, a PZT film having a thickness of 10 nm grows on the side wall with good uniformity. The thickness of the evaporation compensation film is preferably 20 nm to 30 nm.

  As a method for forming the evaporation compensation film, sputtering or atomic layer deposition (ALD) can be used instead of MOCVD. Sputtering is a simple film formation method, and ALD is a film formation method with good step coverage.

  The PZT film 53 opposes the PZT film 37 of the ferroelectric capacitor through the protective film 50. In the heat treatment, when the constituent element evaporates from the PZT film 37, the same constituent element evaporates from the PZT film 53 and can compensate each other. From this function, the PZT film 53 can be called an evaporation compensation film. The evaporation compensation film may not have the same composition as the ferroelectric film of the ferroelectric capacitor. For example, when evaporation of Pb becomes a problem, a material containing Pb and evaporating Pb by heating can be used. As described above, the evaporation compensation film can be formed using a material containing the element that is most easily evaporated among the constituent elements other than oxygen of the ferroelectric film.

  By separating the PZT film 37 of the capacitor dielectric film and the PZT film 53 of the evaporation compensation film by the protective film 50, the PZT films 37 and 53 are separated in the state after the heat treatment, and the migration between them is prevented. The Even if the Pb composition of the PZT film 53 decreases, the PZT film 37 is not affected.

  As shown in FIG. 1O, recovery annealing is performed at a temperature in the range of 550 ° C. to 700 ° C. in an oxygen atmosphere. Thereby, the damage of the ferroelectric film 37 can be recovered. As an example, when the ferroelectric film 37 is formed of PZT, it is preferable to perform recovery annealing at a temperature of 650 ° C. for 60 minutes. Even if Pb evaporates from the PZT film 37, Pb can be introduced from the PZT film 53. The conditions for this recovery annealing are not particularly limited. For example, it is performed in an oxygen atmosphere at 650 ° C. for 60 minutes.

As shown in FIG. 1P, a second protective film 51 made of Al ₂ O ₃ and having a thickness of 20 nm or more is formed on the evaporation compensation film 53 so as to cover the ferroelectric capacitor by sputtering, MOCVD, or ALD. Form by the method. Here, the MOCVD method or the ALD method with good step coverage is desirable. The first and second protective films 50 and 51 constitute a protective film that prevents or suppresses the entry of hydrogen from the outside. By covering the evaporation compensation film 53 with the second protective film 51, evaporation of the constituent elements from the evaporation compensation film 53 is suppressed.

  The alumina film has an excellent function of blocking the permeation of reducing substances such as hydrogen and moisture. Therefore, it can be suppressed that the capacitor dielectric film is reduced by the reducing substance and the characteristics thereof deteriorate.

  In order to prevent the capacitor protective film from being peeled off, annealing may be performed in a furnace containing oxygen before the capacitor protective film is formed. For example, oxygen atmosphere annealing is performed at a substrate temperature of 350 ° C. and a processing time of 1 hour. The capacitor protective film may be formed of titanium oxide, tantalum oxide, zirconium oxide, aluminum nitride, tantalum nitride, and aluminum oxynitride in addition to aluminum oxide.

  As described above, the thickness of the first capacitor protective film is preferably 1 nm to 30 nm. The thickness of the second capacitor protective film is preferably in the range of 1 nm-100 nm, and particularly preferably 20 nm-30 nm. In order to prevent the entry of hydrogen and moisture from the outside, it is desirable to form the second capacitor protective film by MOCVD.

As shown in FIG. 1Q, an interlayer insulating film 55 made of SiO ₂ and having a thickness of 1500 nm is formed on the second protective film 51 by plasma CVD using O ₂ , TEOS, and He. After the film formation, the surface of the interlayer insulating film 55 is planarized by CMP. The interlayer insulating film 55 may be formed of an inorganic insulating material or the like instead of SiO ₂ .

After planarization, heat treatment is performed in a plasma atmosphere of N ₂ O gas or N ₂ gas. By this heat treatment, moisture in the interlayer insulating film 55 is removed, the film quality of the interlayer insulating film 55 is changed, and moisture hardly enters the interlayer insulating film 55.

  Thereafter, a barrier film 57 made of AlO having a thickness of 20 nm to 100 nm is formed on the interlayer insulating film 55 by sputtering or CVD. Since the base surface of the barrier film 57 is flattened, a stable barrier property can be ensured as compared with the case where the barrier film 57 is formed on a surface having irregularities.

As shown in FIG. 1R, an interlayer insulating film 58 made of SiO ₂ and having a thickness of 800 nm to 1000 nm is formed on the barrier film 57 by plasma CVD using O ₂ , TEOS, and He. Note that the interlayer insulating film 58 may be formed of SiON or SiN instead of SiO ₂ . The surface of the interlayer insulating film 58 is planarized by CMP.

  As shown in FIG. 1S, a contact hole 80 that penetrates through five layers from the interlayer insulating film 58 to the first protective film 50 and reaches the upper electrode 38 on the ferroelectric capacitor 35 is formed.

  Heat treatment is performed at 550 ° C. in an oxygen atmosphere. Thereby, oxygen vacancies generated in the ferroelectric film 37 with the formation of the contact holes 80 can be recovered.

An adhesion film having a Ti / TiN structure is formed on the inner surface of the contact hole 80, and W or the like is buried in the contact hole 80 to form a conductive plug 60. Note that the adhesion film may have a two-layer structure of a Ti film formed by sputtering and a TiN film formed by MOCVD. After the TiN film is formed, plasma treatment using a mixed gas of N ₂ gas and H ₂ gas is performed in order to remove carbon from the TiN film. When the third upper electrode is made of Ir, the Ir film prevents hydrogen from entering, so that the upper electrode 38 can be prevented from being reduced. Furthermore, since the composition ratio of IrO of the second upper electrode 38b is close to the stoichiometric composition ratio, the upper electrode 38 is unlikely to cause a catalytic action against hydrogen. For this reason, the ferroelectric film 37 is difficult to be reduced by hydrogen radicals.

  As shown in FIG. 1T, a contact hole 85 that penetrates through seven layers from the interlayer insulating film 58 to the antioxidant film 21 and reaches the upper surface of the conductive plug 16 is formed. After forming an adhesion film having a Ti / TiN structure covering the inner surface of the contact hole 85, W or the like is buried in the contact hole 85 to form a conductive plug 65.

  On the interlayer insulating film 58, wirings 71 and 75 connected to the conductive plugs 60 and 65 are formed. First, a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an AlCu alloy film having a thickness of 360 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 70 nm are sequentially formed by sputtering. The wirings 71 and 75 are formed by patterning the laminated structure composed of these films. Further, for example, an upper multilayer wiring of the second to fifth layers is formed thereon.

A second embodiment of the present invention will be described with reference to FIG. Differences from the first embodiment will be mainly described. 1A to 1C are performed to form the W plug 25. By CMP, a recess 25 a is formed at the top of the plug 25. Similar to the first embodiment, NH ₃ plasma treatment is performed, and then a Ti film having a thickness of 100 nm is formed. Here, heat treatment by RTA is performed in an N ₂ atmosphere to nitride the Ti film. In this way, the TiN base conductive film 30 is formed. The base conductive film 30 is not limited to TiN, and may be formed of TiAlN, tungsten, silicon, or copper.

  A recess reflecting the recess is formed on the surface of the underlying conductive film 30. If the upper structure is formed as it is, the crystallinity of the ferroelectric film may be deteriorated. Therefore, the upper surface of the underlying conductive film 30 is polished by CMP, planarized to remove the recesses, and further polished to polish the insulating film 22. The upper surfaces of the insulating film 22 and the plug are flush with each other. A Ti conductive adhesion film is formed thereon and nitrided to form a TiN film 31. Thereafter, an oxygen barrier film 34 and a lower electrode 36 are formed. Further, RTA at 600 ° C. or higher is performed in an inert gas. Thereafter, the same process as in the first embodiment is continued.

A third embodiment of the present invention will be described with reference to FIG. Differences from the second embodiment will be mainly described. Up to the conductive plug 25 is formed. However, CMP is performed using a low-pressure polishing apparatus. By polishing at a low pressure, no recess is produced. Similar to the second embodiment, NH ₃ plasma treatment is performed to form a Ti film having a thickness of 20 nm. A heat treatment by RTA is performed in an N 2 atmosphere, and the Ti film is nitrided to form the TiN film 30. A TiAlN oxygen barrier film 33 and a lower electrode 36 are directly formed thereon. Thereafter, the same process as in the second embodiment is performed.

As a method for forming the ferroelectric film, there are sol-gel method, organometallic decomposition (MOD), CSD (chemical solution deposition), CVD, and epitaxial growth in addition to sputtering and MOCVD. As the ferroelectric film, a film whose crystal structure becomes a Bi-based layered structure or a perovskite structure can be formed by heat treatment. As such a film, in addition to the PZT film, a film represented by the general formula ABO ₃ such as PZT, SBT, BLT, Bi-based layered compound doped with a small amount of La, Ca, Sr, Si, or the like can be given.

  When forming the bottom layer of the upper electrode. For example, reactive sputtering using a target containing one or more of platinum, iridium, ruthenium, rhodium, rhenium, osmium, and palladium can be performed under conditions where oxidation of these noble metal elements occurs.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

The features of the present invention will be described below.
(Appendix 1)
A semiconductor substrate;
A MOS transistor formed on the semiconductor substrate;
A lower interlayer insulating film covering the MOS transistor;
A capacitor lower electrode formed on the lower interlayer insulating film; an oxide ferroelectric film formed on the capacitor lower electrode; and a capacitor upper electrode formed on the oxide ferroelectric film. Including a ferroelectric capacitor,
A first insulating capacitor protective film that covers at least the exposed surface of the upper electrode and the oxide ferroelectric film and has a function of suppressing transmission of a reducing substance;
An evaporation compensation film that covers the first insulating capacitor protective film and contains at least one element of constituent elements other than oxygen of the oxide ferroelectric;
A second insulating capacitor protective film covering the evaporation compensation film and having a function of suppressing transmission of a reducing substance;
A semiconductor device.
(Appendix 2)
2. The semiconductor device according to claim 1, wherein the evaporation compensation film includes an element that is most easily evaporated among constituent elements other than oxygen other than oxygen of the oxide ferroelectric film.
(Appendix 3)
The semiconductor device according to claim 1, wherein the oxide ferroelectric film and the evaporation compensation film contain Pb.
(Appendix 4)
The first and second insulating capacitor protective films are each formed of at least one selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, aluminum nitride, tantalum nitride, and aluminum oxynitride. The semiconductor device according to any one of 1 to 3.
(Appendix 5)
(A) forming a MOS transistor on a semiconductor substrate;
(B) forming a lower interlayer insulating film on the semiconductor substrate so as to cover the MOS transistor;
(C) Laminating a capacitor lower electrode film above the lower interlayer insulating film, an oxide ferroelectric capacitor dielectric film on the capacitor lower electrode, and a capacitor upper electrode film on the capacitor dielectric film. Process,
(D) patterning at least the capacitor upper electrode film;
(E) forming a first insulating capacitor protective film having a function of covering the exposed surface of the capacitor upper electrode film and the capacitor dielectric film and suppressing permeation of a reducing substance;
(F) forming an evaporation compensation film that covers the first insulating capacitor protective film and includes at least one element of the oxide ferroelectric substance other than oxygen;
(G) After the step (f), a step of heat-treating in an oxidizing atmosphere;
(H) After the step (g), forming a second insulating capacitor protective film having a function of covering the evaporation compensation film and suppressing permeation of the reducing substance;
A method for manufacturing a semiconductor device comprising:
(Appendix 6)
The semiconductor device manufacturing method according to claim 5, wherein the evaporation compensation film includes an element that is most easily evaporated among constituent elements other than oxygen of the oxide ferroelectric film.
(Appendix 7)
Capacitor dielectric film obtained by patterning the upper electrode film, the capacitor dielectric film, and the lower electrode film in the step (d) and patterning the steps (e), (f), and (h) 7. The method of manufacturing a semiconductor device according to appendix 5 or 6, wherein the first insulating capacitor protective film, the evaporation compensation film, and the second insulating capacitor protective film are stacked so as to cover a side surface of the first insulating capacitor.
(Appendix 8)
The method for manufacturing a semiconductor device according to claim 5, wherein the oxide ferroelectric film and the evaporation compensation film contain Pb.
(Appendix 9)
The first and second insulating capacitor protective films are each formed of at least one selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, aluminum nitride, tantalum nitride, and aluminum oxynitride. The manufacturing method of the semiconductor device of any one of 5-8.

/ / / / / / / 1A to 1T are cross-sectional views of a semiconductor substrate showing main steps of a semiconductor device manufacturing method according to a second embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor substrate for explaining a third embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor substrate for explaining a fourth embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 11 Silicon oxynitride film 12 Silicon oxide film 21 Antioxidation film 22 Interlayer insulating film 25 Conductive plug 30 Underlying conductive film 31 Crystallinity improvement film 33 Oxygen barrier (TiAlN) film 34 Intermediate layer 36 Lower electrode (Ir film)
37 Ferroelectric (PZT) film 38 Upper (IrO) electrode 45, 46 Hard mask 50, 51 Protective (AlO) film 53 Evaporation compensation film 55 Interlayer insulating film 57 Barrier (AlO) film 58 Interlayer insulating film 60, 65 Conductivity Plug 71, 75 wiring

Claims (5)

A semiconductor substrate;
A MOS transistor formed on the semiconductor substrate;
A lower interlayer insulating film covering the MOS transistor;
A capacitor lower electrode formed on the lower interlayer insulating film; an oxide ferroelectric film formed on the capacitor lower electrode; and a capacitor upper electrode formed on the oxide ferroelectric film. Including a ferroelectric capacitor,
A first insulating capacitor protective film that covers at least the exposed surface of the upper electrode and the oxide ferroelectric film and has a function of suppressing transmission of a reducing substance;
An evaporation compensation film that covers the first insulating capacitor protective film and contains at least one element of constituent elements other than oxygen of the oxide ferroelectric;
A second insulating capacitor protective film covering the evaporation compensation film and having a function of suppressing transmission of a reducing substance;
A semiconductor device.   The semiconductor device according to claim 1, wherein the oxide ferroelectric film and the evaporation compensation film contain Pb. (A) forming a MOS transistor on a semiconductor substrate;
(B) forming a lower interlayer insulating film on the semiconductor substrate so as to cover the MOS transistor;
(C) Laminating a capacitor lower electrode film above the lower interlayer insulating film, an oxide ferroelectric capacitor dielectric film on the capacitor lower electrode, and a capacitor upper electrode film on the capacitor dielectric film. Process,
(D) patterning at least the capacitor upper electrode film;
(E) forming a first insulating capacitor protective film having a function of covering the exposed surface of the capacitor upper electrode film and the capacitor dielectric film and suppressing permeation of a reducing substance;
(F) forming an evaporation compensation film that covers the first insulating capacitor protective film and includes at least one element of the oxide ferroelectric substance other than oxygen;
(G) After the step (f), a step of heat-treating in an oxidizing atmosphere;
(H) After the step (g), forming a second insulating capacitor protective film having a function of covering the evaporation compensation film and suppressing the permeation of the reducing substance;
A method for manufacturing a semiconductor device comprising:   Capacitor dielectric film obtained by patterning the upper electrode film, the capacitor dielectric film, and the lower electrode film in the step (d) and patterning the steps (e), (f), and (h) 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first insulating capacitor protective film, the evaporation compensation film, and the second insulating capacitor protective film are stacked so as to cover a side surface of the first insulating capacitor.   The method for manufacturing a semiconductor device according to claim 3, wherein the oxide ferroelectric film and the evaporation compensation film contain Pb.

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