JP2008027939A - Protective element and its fabrication process, and compound semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protective element in which a leakage current can be reduced while enhancing surge resistance. <P>SOLUTION: In a protective element having an n-type n<SP>-</SP>GaAs layer 6, and a p-type emitter region 8 and a p-type collector region 9 formed in the n<SP>-</SP>GaAs layer, an n<SP>+</SP>GaAs layer having a doping concentration higher than that of dopant in the n<SP>-</SP>GaAs layer is provided between the p-type emitter region 8 and the p-type collector region 9 on the n<SP>-</SP>GaAs layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a protective element, a manufacturing method thereof, and a compound semiconductor device. Specifically, by forming a two-layered conductor layer and making the carrier concentration in the upper conductor layer larger than the carrier concentration in the lower conductor layer, the surge resistance is improved and the leakage current is reduced. The present invention relates to a protective element to be reduced, a manufacturing method thereof, and a compound semiconductor device.

  A compound semiconductor field effect transistor having a compound semiconductor layer such as GaAs has high electron mobility and good high frequency characteristics, and is therefore widely used in the field of high frequency regions such as cellular phones.

  Here, it is known that the gate electrode and the drain electrode of the compound semiconductor field effect transistor are not so high that the surge resistance is required for a field effect transistor having a desired application, structure, and dimensions. In the case of a transistor having a small gate width, the gate electrode and the drain electrode are extremely resistant to surges, and may be broken by a surge voltage of 20 to 30V. In order to improve the high-frequency characteristics, the distance between the gate and the drain and the distance between the gate and the source are reduced. This is one of the causes for reducing the resistance to surge.

  Therefore, in order to improve the resistance to surge, a protective element is sometimes used between the gate and the drain and between the gate and the source (see, for example, Patent Document 1), and this protective element has a leak during normal operation. There is a demand for reducing the current and improving the surge resistance of the protection element itself.

  Hereinafter, a compound semiconductor device including a conventional protection element will be described with reference to the drawings.

  FIG. 4 is a schematic cross-sectional view for explaining a compound semiconductor device provided with a conventional protection element. In the compound semiconductor device 101 shown here, no impurity is added on a semi-insulating GaAs substrate 102. A channel layer 104 and a barrier layer 105 are sequentially stacked via a buffer layer 103 made of (undoped) GaAs single crystal.

An n ⁺ GaAs layer 106 having a Si doping concentration of 6 × 10 ¹⁸ / cm ³ is formed on the barrier layer 105, and a p-type emitter region 107 and a p-type collector region 108 are formed on the surface of the n ⁺ GaAs layer. Is formed.

Further, a passivation film 110 made of SiN provided with contact holes 113 and 114 is formed on the n ⁺ GaAs layer 106, and an emitter electrode 111 and a contact hole 114 that are in ohmic contact with the p-type emitter region through the contact hole 113. A collector electrode 112 is formed in ohmic contact with the p-type collector region. In the figure, reference numerals 115 and 116 denote element isolation regions containing p-type impurities.

  In the above-described conventional protection element, a surge current can be released by utilizing Zener breakdown.

  However, this conventional protection element has a problem that the junction leakage current is high in a normal operation state (during normal operation) that does not reach the breakdown voltage. For this reason, in the integrated circuit using the protection element, the current consumption is increased.

  Therefore, the applicant of the present invention has repeatedly studied to solve such a problem, and has a two-layer structure in which a conductor layer is further provided in the lower layer of the conductor layer forming the pn junction, and the upper conductor layer forming the pn junction is formed. A protective element having a carrier concentration smaller than that of the lower conductor layer has been developed (see Patent Document 2).

That is, by making the carrier concentration of the upper conductive layer forming the pn junction smaller than the carrier concentration of the lower conductive layer, the surge resistance is improved and the leakage current is further reduced.
JP 2002-9253 A JP 2006-32582 A

  As described above, the present applicant has developed a protective element in which the carrier concentration of the upper conductive layer forming the pn junction is smaller than the carrier concentration of the lower conductive layer. There is a demand for a protective element capable of further improving the resistance to surge of the element itself and a compound semiconductor device including the protective element.

  Therefore, as a result of further research, the present applicant has found that the protective element has a problem to be solved.

That is, due to the heat applied in the manufacturing process, Si in the high concentration n ⁺ GaAs layer diffuses into the lower layer of the n ⁺ GaAs layer and affects other elements such as field effect transistors, resulting in deterioration of characteristics. I will.

Moreover, n ⁺ by Si in GaAs layer diffuses into the underlying n ⁺ GaAs layer, which leads to reduction in the resistance to a surge protection device.

  Therefore, the present invention was devised in view of the above points, and includes a protection element capable of improving surge resistance and reducing leakage current, a manufacturing method thereof, and a compound semiconductor device. It is intended to provide.

  In order to achieve the above object, the invention according to claim 1 is formed in a first conductive layer of a first conductivity type and the first conductive layer, and a pn junction is formed between the first conductive layer and the first conductive layer. And a pair of second conductivity type second conductor layers formed on the first conductor layer and between the second conductor layers than the first conductor layer. A third conductive layer of the first conductivity type having a high concentration is provided.

  Here, the second conductor layer of the second conductivity type forming a pn junction with the first conductor layer is formed in the first conductor layer, and the carrier concentration in the first conductor layer is the carrier in the third conductor layer. Since it is smaller than the concentration, current flows only in the first conductor layer having a low carrier concentration during normal operation, and leakage current can be suppressed.

  In addition, when a surge occurs, current flows not only through the first conductor layer but also through the third conductor layer having a high carrier concentration, so that surge resistance can be improved.

  In addition, since the third conductor layer having a high carrier concentration is above the first conductor layer, the dopant of the third conductor layer does not diffuse into the lower layer of the first conductor layer, and a field effect transistor or the like It is possible to avoid affecting other elements.

  Furthermore, since the dopant of the third conductor layer diffuses into the first conductor layer, the allowable current amount of the first conductor layer can be improved.

  According to a second aspect of the present invention, there is provided a step of forming a first conductive layer of a first conductivity type on a substrate, and a carrier concentration on the first conductive layer is higher than that of the first conductive layer. A step of forming a large first conductive type third conductive layer in a predetermined shape, and a position at which the third conductive layer is sandwiched and the first conductive layer and the pn junction are formed on the first conductive layer Forming a second conductive layer of the second conductivity type.

  Here, a first conductive type third conductive layer having a carrier concentration higher than the carrier concentration in the first conductive layer is formed on the first conductive type first conductive layer, and the inside of the first conductive layer In addition, by forming a second conductive type second conductive layer that forms a pn junction with the first conductive layer, current flows only in the second conductive layer having a low carrier concentration during normal operation, and leakage current is reduced. Can be suppressed.

  In addition, when a surge occurs, current flows not only through the first conductor layer but also through the third conductor layer having a high carrier concentration, so that surge resistance can be improved.

  According to a third aspect of the present invention, there is provided a substrate having a compound semiconductor layer, a first conductive layer of a first conductivity type formed on or in the substrate, and formed on the first conductive layer. And a pair of second conductive type second conductive layers forming a pn junction with the first conductive layer, wherein the second conductive layer is on the first conductive layer and the second conductive layer. A third conductive layer of a first conductivity type having a carrier concentration higher than that of the first conductive layer is provided between body layers.

  Here, the second conductor layer of the second conductivity type forming a pn junction with the first conductor layer is formed in the first conductor layer, and the carrier concentration in the first conductor layer is the carrier in the third conductor layer. Since it is smaller than the concentration, current flows only in the first conductor layer having a low carrier concentration during normal operation, and leakage current can be suppressed.

  In addition, when a surge occurs, current flows not only through the first conductor layer but also through the third conductor layer having a high carrier concentration, so that surge resistance can be improved.

  In addition, since the third conductor layer having a high carrier concentration is in the upper layer of the first conductor layer, the dopant of the third conductor layer does not diffuse into the lower layer of the first conductor layer, and the first conductor Even when other elements such as a field effect transistor formed below the layer are formed, it is possible to avoid affecting the other elements.

  Furthermore, since the dopant of the third conductor layer diffuses into the first conductor layer, the allowable current amount of the first conductor layer can be improved.

  In the protection element, the manufacturing method thereof, and the compound semiconductor device of the present invention described above, leakage current during normal operation can be suppressed and resistance to surge can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view for explaining a compound semiconductor device 1 having a protection element to which the present invention is applied. The compound semiconductor device 1 shown here has impurities on a semi-insulating GaAs substrate 2. A channel layer 4 and a barrier layer 5 are sequentially stacked via a buffer layer 3 made of undoped GaAs single crystal.

Here, the semi-insulating GaAs substrate 2 contains almost no impurities and is made of a single crystal having a resistivity of about 10 ⁶ to 10 ⁸ Ω · cm, for example. The semi-insulating GaAs substrate 2 is a bulk crystal and includes many lattice defects such as point defects and dislocations. Therefore, when an epitaxial layer is grown on the semi-insulating GaAs substrate 2, a good quality crystal is not obtained. In order to prevent this, the buffer layer 3 is provided on the semi-insulating GaAs substrate 2.

As a material for the channel layer 4, for example, In _x Ga _1-x As (undoped-InGaAs) mixed crystal to which no impurity is added is used. Usually, an InGaAs mixed crystal has a higher electron mobility than an AlGaAs mixed crystal, and high-speed electron transfer is possible by using InGaAs as a channel layer. When an In _x Ga _1-x As mixed crystal is used as the channel layer 4, the In composition ratio x is usually 0.1 to 0.2.

The barrier layer 5 is made of a Group III-V compound semiconductor such as Al _x Ga _1-x As mixed crystal, and the Al composition ratio x is usually 0.2 to 0.3.

An n ⁻ GaAs layer 6 (corresponding to an example of a first conductor layer) having a Si doping concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁷ / cm ³ and a film thickness of 50 nm is formed on the barrier layer 5. On the n ⁻ GaAs layer 6, an n ⁺ GaAs layer 7 (corresponding to an example of a third conductor layer) having a Si doping concentration of 6 × 10 ¹⁸ / cm ³ and a film thickness of 80 nm is formed. . Further, a p-type emitter region 8 and a p-type collector region 9 (corresponding to an example of a pair of second conductor layers) are formed on the surface of the n ⁻ GaAs layer 6.

Incidentally, by changing the thickness of the Si concentration and the n ⁺ GaAs layer 7 which is doped n ⁺ GaAs layer 7, it is possible to arbitrarily adjust the resistance to surge. Further, n ^- Si concentration and n are doped in the GaAs layer 6 ^- also by changing the thickness of the GaAs layer 6, it is possible to arbitrarily adjust the leakage current.

Further, a passivation film 12 made of SiN provided with contact holes 10 and 11 is formed on the n ⁻ GaAs layer 6, and an emitter electrode 13 and a contact hole 11 that are in ohmic contact with the p-type emitter region through the contact hole 10. A collector electrode 14 is formed in ohmic contact with the p-type collector region. In the figure, reference numerals 15 and 16 denote element isolation regions containing p-type impurities.

If GaAs layer 6 only - ^Here, n - are you a two-layer structure of the GaAs layer 6 and the n ⁺ GaAs layer 7, during normal operation ⁿ - GaAs layer 6 only to conduct current when a surge enters ⁿ This is because current is passed through the n ⁺ GaAs layer 7 to improve surge resistance.

Therefore, if the surge resistance can be sufficiently increased by making the Si dose in the n ⁺ GaAs layer 7 larger than the Si dose in the n ⁻ GaAs layer 6, the film of the n ⁺ GaAs layer 7 is not necessarily required. The thickness need not be greater than that of the n ⁻ GaAs layer 6.

However, in order to allow a larger current to flow through the n ⁺ GaAs layer 7 when a surge occurs, that is, in order to sufficiently increase the allowable current amount, the dose amount of Si in the n ⁺ GaAs layer 7 is changed to that in the n ⁻ GaAs layer. It is preferable that the n ⁺ GaAs layer 7 has a larger thickness than that of the n ⁻ GaAs layer 6.

  Hereinafter, a method for manufacturing a compound semiconductor device including the above-described protection element will be described.

  In the above-described method for manufacturing a compound semiconductor device, first, undoped-AlGaAs is epitaxially grown on the semi-insulating GaAs substrate 2 by, for example, metal organic chemical vapor deposition (MOCVD) to form the buffer layer 3 (FIG. 2 ( a)).

  Next, on the upper layer of the buffer layer 3, undoped-InGaAs is epitaxially grown by, for example, the MOCVD method to form the channel layer 4 (see FIG. 2A).

  Further, epitaxial growth is performed on the channel layer 4 by, for example, MOCVD to form a barrier layer 5 that is a stacked layer of an undoped-AlGaAs layer, an n-AlGaAs layer, and an undoped-AlGaAs layer (see FIG. 2A).

Next, GaAs containing n-type impurities at a low concentration as an n-type impurity is epitaxially grown on the upper layer of the barrier layer 5 by, for example, the MOCVD method to form an n ⁻ GaAs layer 6 (see FIG. 2A). . n ^- n-type impurity concentration of the GaAs layer, for example, to ^{1 × 10 17 ~5 × 10 17} / cm 3.

Subsequently, on the upper layer of the n ⁻ GaAs layer 6, GaAs containing Si as a high concentration as an n-type impurity is epitaxially grown to a thickness of about 80 nm by MOCVD, for example, to form an n ⁺ GaAs layer 7 (FIG. 2A). )reference). The n-type impurity concentration of the n ⁺ GaAs layer is, for example, 6 × 10 ¹⁸ / cm ³ .

Next, a photoresist (not shown) is applied on the n ⁺ GaAs layer 7, the photoresist is exposed and developed by a general-purpose photolithography process, pattern etching is performed, and an unnecessary portion of the n ⁺ GaAs layer is formed. 7 is removed. Thereafter, the resist mask is removed by, for example, plasma ashing (see FIG. 2B). As the etching, wet etching is mainly used.

Further, the photoresist is exposed and developed by a general-purpose photolithography process, pattern etching is performed, and an unnecessary portion of the n ⁻ GaAs layer 6 is removed. Thereafter, the resist mask is removed by, for example, plasma ashing (see FIG. 2B). As the etching, wet etching is mainly used.

  Next, as shown in FIG. 2C, a passivation film 12 is formed by depositing a silicon oxide film of, eg, 300 nm on the entire surface of the substrate by, eg, plasma CVD.

Next, a photoresist (not shown) is applied on the n ⁻ GaAs layer, and the photoresist is exposed and developed by a general-purpose photolithography process to form a resist mask having an opening in an element isolation region formation region. Then, element isolation regions 15 and 16 are formed by ion implantation of boron as a p-type impurity, for example. Thereafter, the resist mask is removed by, for example, plasma ashing (see FIG. 2D).

  Next, a photoresist (not shown) is applied on the passivation film 12, and the photoresist is exposed and developed by a general-purpose photolithography process, and a resist mask having openings in the emitter electrode formation region and the collector electrode formation region. Form.

Subsequently, anisotropic etching is performed on the passivation film 12 by, for example, reactive ion etching using a CF ₄ gas.

  Thereafter, the resist mask is removed by, for example, plasma ashing to form contact holes 10 and 11 in the emitter electrode formation region and the collector electrode formation region of the passivation film 12 as shown in FIG.

Next, for example, Zn as a p-type impurity is vapor-phase diffused at about 600 ° C. in the n ⁻ GaAs layer 6 through the contact holes 10 and 11 formed in the passivation film 12, and the n ⁺ GaAs layer 7 is sandwiched between A p-type emitter region 8 and a p-type collector region 9 are formed (see FIG. 3F). Note that when the p-type emitter region and the p-type collector region extend to the n ⁺ GaAs layer 7, the leak current cannot be suppressed, so that the n ⁺ GaAs layer 7 has the p-type emitter region and the p-type collector. The p-type emitter region and the p-type collector region are formed in the n ⁻ GaAs layer.

  Subsequently, for example, a laminated film of Ti, Pt, and Au is formed on the entire surface of the substrate by, for example, an electron beam evaporation method, and then the laminated film is etched to form the emitter electrode 13 and the collector electrode 14, thereby obtaining FIG. A compound semiconductor device provided with a protective element as shown in g) can be obtained.

  In the above embodiment, the protection element formed by epitaxial growth on the GaAs substrate has been described. However, the manufacturing method of the protection element is not limited to epitaxial growth, and, for example, ion implantation is performed on the GaAs substrate. Thus, a protective element may be formed.

A compound semiconductor device having a protective element of the present invention described above, the p-type emitter region and the p-type collector region doping concentration of Si is smaller the n ^- for forming the GaAs layer, in the normal operation n ^- Current flows only in the GaAs layer, and leakage current can be suppressed.

In addition, when a surge occurs, not only the n ⁻ GaAs layer but also the n ⁻ GaAs layer and the n ⁺ GaAs layer immediately above it can be used to release the surge, improving surge resistance. Can be achieved.

Moreover, since the high-concentration n ⁺ GaAs layer is on the upper layer of the n ⁻ GaAs layer, the dopant (Si) of the n ⁺ GaAs layer does not diffuse into the lower layer of the n ⁻ GaAs layer. It is possible to avoid affecting the elements.

Additionally, the dopant of n ⁺ GaAs layer is ⁿ - ⁿ from being diffused into the GaAs layer - it is possible to improve the allowable current amount of the GaAs layer.

It is typical sectional drawing for demonstrating the compound semiconductor device provided with the protection element to which this invention is applied. It is a schematic diagram (1) for demonstrating the manufacturing method of a compound semiconductor device. It is a schematic diagram (2) for demonstrating the manufacturing method of a compound semiconductor device. It is typical sectional drawing for demonstrating the compound semiconductor device provided with the conventional protective element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Compound semiconductor device 2 Semi-insulating GaAs substrate 3 Buffer layer 4 Channel layer 5 Barrier layer 6 n ⁻ GaAs layer 7 n ⁺ GaAs layer 8 p-type emitter region 9 p-type collector region 10, 11 Contact hole 12 Passivation film 13 Emitter electrode 14 Collector electrodes 15 and 16 Element isolation region

Claims (3)

A protection comprising a first conductor layer of a first conductivity type and a pair of second conductor layers of a second conductivity type formed on the first conductor layer and forming a pn junction with the first conductor layer. In the element
A first conductive type third conductive layer having a carrier concentration higher than that of the first conductive layer is provided on the first conductive layer and between the second conductive layers. Protective element. Forming a first conductive layer of a first conductivity type on a substrate;
Forming a first conductive type third conductor layer having a higher carrier concentration than the first conductor layer in a predetermined shape on the first conductor layer;
Forming a second conductive type second conductive layer that forms a pn junction with the first conductive layer on the first conductive layer at a position sandwiching the third conductive layer;
The manufacturing method of the protection element which has this. A substrate having a compound semiconductor layer, a first conductor layer of a first conductivity type formed on or in the substrate, and a pn junction formed on the first conductor layer In a compound semiconductor device comprising a pair of second conductor layers of the second conductivity type forming
A third conductive layer of the first conductivity type having a higher carrier concentration than the first conductive layer is provided on the first conductive layer and between the second conductive layers. Compound semiconductor device.

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