CN111326590A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN111326590A CN111326590A CN202010101995.6A CN202010101995A CN111326590A CN 111326590 A CN111326590 A CN 111326590A CN 202010101995 A CN202010101995 A CN 202010101995A CN 111326590 A CN111326590 A CN 111326590A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 188
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 title claims description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000002096 quantum dot Substances 0.000 claims description 16
- 239000002086 nanomaterial Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 9
- 239000002070 nanowire Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
The disclosure provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor device includes: a substrate; a first semiconductor layer on the substrate; a doped region in the first semiconductor layer, the doped region and the first semiconductor layer having different conductivity types; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having a material with a forbidden band width greater than that of the first semiconductor layer; and a first metal layer on the second semiconductor layer and forming a schottky contact with the second semiconductor layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
The Schottky diode has unipolar conductive characteristics, a forward conduction voltage is reduced, and a reverse recovery time is short. However, the schottky diode has a disadvantage that a reverse leakage current is excessive.
In a hybrid PIN schottky (MPS) diode, a depletion region formed at a field limiting ring can bear a large reverse voltage on the one hand, and a depletion region interconnection can wrap a schottky junction on the other hand, so that increase of reverse leakage caused by reduction of a schottky barrier can be suppressed.
Disclosure of Invention
The inventors have noted that in MPS diodes, interface states between the metal and semiconductor layers forming the schottky contact can cause the schottky barrier to decrease, thereby increasing the reverse leakage current of the MPSE diode.
In order to solve the above problem, the embodiments of the present disclosure provide the following technical solutions.
According to an aspect of the embodiments of the present disclosure, there is provided a semiconductor device including: a substrate; a first semiconductor layer on the substrate; a doped region in the first semiconductor layer, the doped region and the first semiconductor layer having different conductivity types; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having a material with a forbidden band width greater than that of the first semiconductor layer; and a first metal layer on the second semiconductor layer and forming a schottky contact with the second semiconductor layer.
In some embodiments, the second semiconductor layer comprises nanostructures.
In some embodiments, the nanostructure layer comprises at least one of quantum dots and nanowires.
In some embodiments, the second semiconductor layer has a first opening, an orthographic projection of the first opening on the substrate at least partially overlaps with an orthographic projection of the doped region on the substrate; the semiconductor device further includes: and a second metal layer in the first opening and forming ohmic contact with the doped region, wherein the first metal layer is positioned on the second metal layer. In some embodiments, the material of the first semiconductor layer comprises SiC and the material of the second semiconductor layer comprises GaN.
In some embodiments, the impurity of the doped region comprises Al.
In some embodiments, the semiconductor device is a diode.
In some embodiments, the second semiconductor layer comprises a nanostructure layer.
In some embodiments, the nanostructure layer comprises at least one of quantum dots and nanowires.
In some embodiments, the second semiconductor layer has a first opening, an orthographic projection of the first opening on the substrate at least partially overlaps with an orthographic projection of the doped region on the substrate; before forming the first metal layer, further comprising: and forming a second metal layer which forms ohmic contact with the doped region in the first opening, wherein the first metal layer is positioned on the second metal layer.
In some embodiments, the second semiconductor layer comprises quantum dots; forming the second metal layer and the second semiconductor layer by: forming a second preliminary semiconductor layer on the substrate structure, the second preliminary semiconductor layer having the first opening; forming the second metal layer in the first opening; performing a first anneal to cause the ohmic contact to be formed between the second metal layer and the doped region and to cause the second preliminary semiconductor layer to become the second semiconductor layer including quantum dots.
In some embodiments, after forming the first metal layer on the second semiconductor layer, a second anneal is performed to form the schottky contact.
In some embodiments, the material of the first semiconductor layer comprises SiC and the material of the second semiconductor layer comprises GaN.
In some embodiments, the providing a substrate structure comprises: providing the substrate; forming the first semiconductor layer on the substrate; forming a mask layer having a second opening on the first semiconductor layer; doping the first semiconductor layer below the second opening by using the mask layer as a mask to form the doped region; after the doped region is formed, the mask layer is removed.
In some embodiments, the doping comprises ion implantation.
In some embodiments, the doped impurities comprise Al.
In some embodiments, the providing a substrate structure further comprises: forming a buffer layer on the first semiconductor layer; forming the mask layer on the buffer layer; and removing the buffer layer after the doped region is formed.
In some embodiments, the buffer layer comprises an oxide layer.
In some embodiments, the semiconductor device is a diode.
In the semiconductor device provided by the embodiment of the disclosure, the second semiconductor layer with a wider forbidden band than the first semiconductor layer is arranged between the first metal layer and the first semiconductor layer, so that the schottky barrier is reduced, and the reverse leakage current of the semiconductor device is reduced.
Other features, aspects, and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram illustrating a structure of a semiconductor device according to some embodiments of the present disclosure;
fig. 2 is a schematic flow chart diagram illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure;
3A-3F are cross-sectional schematic diagrams illustrating structures resulting from different stages of forming a semiconductor device according to some embodiments of the present disclosure;
fig. 4A-4C are schematic cross-sectional views illustrating structures resulting from different stages of forming a substrate structure according to some implementations of the present disclosure.
It should be understood that the dimensions of the various parts shown in the figures are not necessarily drawn to scale. Further, the same or similar reference numerals denote the same or similar components.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.
The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be intervening components between the specific component and the first component or the second component. When it is described that a specific component is connected to other components, the specific component may be directly connected to the other components without having an intervening component, or may be directly connected to the other components without having an intervening component.
All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
Fig. 1 is a schematic diagram illustrating a structure of a semiconductor device according to some embodiments of the present disclosure.
In some embodiments, the semiconductor devices provided by the embodiments of the present disclosure may be diodes. In other embodiments, the semiconductor devices provided by the embodiments of the present disclosure may include diodes and other semiconductor devices, such as transistors and the like.
As shown in fig. 1, the semiconductor device includes a substrate 101. In some implementations, the substrate 101 can be a semiconductor substrate, such as a SiC substrate.
The semiconductor device further includes a first semiconductor layer 102 on the substrate 101. In some embodiments, the first semiconductor layer 102 may be an epitaxial layer, such as a SiC epitaxial layer or the like.
The semiconductor device further comprises a doped region 103 in the first semiconductor layer 102. It is understood that the number of doped regions 103 may be one, or may be plural as shown in fig. 1. In the case where a plurality of doped regions 103 are included, adjacent doped regions 103 are spaced apart by the first semiconductor layer 102. Here, the doped region 103 and the first semiconductor layer 102 have different conductivity types. For example, the conductivity type of the first semiconductor layer 102 is n-type, and the conductivity type of the doped region 103 is p-type; and vice versa. For example, the first semiconductor layer 102 may be a lightly doped layer, and the doped region 103 may be a heavily doped region. In some embodiments, the impurity in the doped region 103 includes Al.
In some embodiments, the upper surface of the first semiconductor layer 102 is flush with the upper surface of the doped region 103. It should be understood that flush here refers to flush within the semiconductor process variation.
The semiconductor device further includes a second semiconductor layer 104 on the first semiconductor layer 102. The material of the second semiconductor layer 104 has a forbidden band width greater than that of the first semiconductor layer 102. In some implementations, the material of the first semiconductor layer 102 includes SiC (e.g., 4H-SiC) and the material of the second semiconductor layer 104 includes GaN. The band gap of 4H-SiC was 3.25eV, and the band gap of GaN was 3.4 eV.
The semiconductor device further includes a first metal layer 105 on the second semiconductor layer 104. Here, a schottky contact is formed between the first metal layer 105 and the second semiconductor layer 104. As some implementations, the material of first metal layer 105 may include aluminum or the like.
In the above embodiment, the second semiconductor layer 104 having a larger forbidden band width than the first semiconductor layer 102 is disposed between the first metal layer 105 and the first semiconductor layer 102, so that the schottky barrier is reduced, and the reverse leakage current of the semiconductor device is reduced.
The inventors have noted that there may be a lattice mismatch between the second semiconductor layer 104 and the first semiconductor layer 102, and the thermal expansion coefficients may also be different, which may result in a large number of defect states at the interface of the second semiconductor layer 104 and the first semiconductor layer 102. Accordingly, the present application proposes the following solution.
In some embodiments, the second semiconductor layer 104 may include nanostructures. Such a structure may reduce the contact area between the second semiconductor layer 104 and the first semiconductor layer 102, thereby reducing the defect state at the interface therebetween. For example, the nanostructures may comprise at least one of quantum dots or nanowires. Taking quantum dots as an example, the forbidden bandwidth of the second semiconductor layer 104 and the defect state between the second semiconductor layer 104 and the first semiconductor layer 102 can be adjusted by changing the shape, size and other parameters of the quantum dots. As some implementations, the shape of the quantum dots can include one or more of the following: cylindrical (e.g., cylindrical), spherical, and parabolic. As an example, the size range of the quantum dots may be: 20nm to 40nm, for example, 25nm, 30nm, etc.
In some embodiments, referring to fig. 1, the second semiconductor layer 104 has a first opening 114, and an orthographic projection of the first opening 114 on the substrate 101 at least partially overlaps with an orthographic projection of the doped region 103 on the substrate 101. In other words, the first opening 114 exposes at least a portion of the surface of the doped region 103.
In some implementations, the first metal layer 105 may be located in the first opening 114 and in contact with the doped region 103.
In other implementations, referring to fig. 1, the semiconductor device may further include a second metal layer 106 forming an ohmic contact between the doped region 103 and the first opening 114. In this case, the first metal layer 105 is located on the second metal layer 106. For example, first metal layer 105 may be in contact with second metal layer 106. In some embodiments, the thickness of the second metal layer 106 and the thickness of the second semiconductor layer 104 may be the same.
In the above implementation, the ohmic contact is formed between the second metal layer 106 and the doped region 103, so that the contact resistance of the semiconductor device is reduced.
In some embodiments, the semiconductor device may further include a third metal layer, such as a Ti layer, on the lower surface of the substrate 101.
Fig. 2 is a flow diagram illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. Fig. 3A-3F are cross-sectional schematic diagrams illustrating structures resulting from different stages of forming a semiconductor device according to some embodiments of the present disclosure.
Methods of fabricating semiconductor devices according to some embodiments of the present disclosure are described in detail below with reference to fig. 2, 3A-3F. It is to be understood that in the following description, certain steps are not necessary in certain embodiments.
In step 202, a substrate structure is provided.
As shown in fig. 3A, the substrate structure includes a substrate 101, a first semiconductor layer 102 on the substrate 101, and a doped region 103 in the first semiconductor layer 102. Here, the doped region 103 and the first semiconductor layer 102 have different conductivity types.
The substrate structure may be formed in different ways, and some specific implementations of forming the substrate structure will be described later in connection with fig. 4A-4.
At step 204, a second semiconductor layer 104 is formed on the first semiconductor layer 102, as shown in fig. 3E. The material of the second semiconductor layer 104 has a forbidden band width greater than that of the first semiconductor layer 102. For example, the material of the first semiconductor layer 102 includes SiC, and the material of the second semiconductor layer 104 includes GaN.
In some embodiments, the second semiconductor layer 104 comprises a nanostructure layer. As some implementations, the nanostructure layer may include at least one of quantum dots and nanowires.
In some embodiments, as shown in fig. 3E, the second semiconductor layer 104 has a first opening 114, and an orthographic projection of the first opening 114 on the substrate 101 at least partially overlaps with an orthographic projection of the doped region 103 on the substrate 101. In other words, the first opening 114 exposes at least a portion of the surface of the doped region 103. In some implementations, referring to fig. 3E, a second metal layer 106 forming an ohmic contact with the doped region 103 may also be formed in the first opening 114.
In some embodiments, the second semiconductor layer 104 comprises quantum dots. In this case, the second metal layer 106 and the second semiconductor layer 104 shown in fig. 3E may be formed through fig. 3B to 3D. This is described in detail below in conjunction with fig. 3B-3D.
As shown in fig. 3B, a second preliminary semiconductor layer 301 is formed on the substrate structure. For example, a GaN thin film may be formed as the second initial semiconductor layer by Metal Organic Chemical Vapor Deposition (MOCVD). As an example, the temperature range for forming GaN by MOCVD may be 500 ℃ to 700 ℃, such as 550 ℃, 600 ℃, and the like.
As shown in fig. 3C, the second preliminary semiconductor layer 301 is patterned to form the first opening 114 extending to the surface of the doped region 103. Here, the first opening 114 exposes at least a part of the surface of the doped region 103. It is to be understood that fig. 3C schematically illustrates the case where the first opening 114 exposes the entire surface of the doped region 103.
As shown in fig. 3D, the second metal layer 106 is formed in the first opening 114. For example, Ti may be formed as the second metal layer 106 through an electron beam evaporation process. In some embodiments, during the formation of the second metal layer 106, a third metal layer may also be formed on the lower surface of the substrate 201 as a cathode electrode.
As shown in fig. 3E, a first annealing is performed such that an ohmic contact is formed between the second metal layer 106 and the doped region 103, and the second preliminary semiconductor layer 301 becomes the second semiconductor layer 104 including quantum dots.
For example, the annealing temperature range of the first annealing may be 1000 ℃ to 1200 ℃, such as 1100 ℃, and the like. The annealing atmosphere of the first annealing may be nitrogen gas.
In step 206, a first metal layer 105 is formed on the second semiconductor layer 104, and a schottky contact is formed between the first metal layer 105 and the second semiconductor layer 104, as shown in fig. 3F.
In some implementations, after forming the first metal layer 105 on the second semiconductor layer 104, a second anneal may be performed to form a schottky contact between the first metal layer 105 and the second semiconductor layer 104. The annealing temperature range of the second annealing may be 400 ℃ to 600 ℃, for example, 400 ℃, 500 ℃, 600 ℃, or the like.
It is to be understood that in the case of forming second metal layer 106, first metal layer 105 is located on second metal layer 106, e.g., in contact with second metal layer 106.
As above, semiconductor devices according to some embodiments of the present disclosure may be formed according to fig. 3A-3F.
Fig. 4A-4C are schematic cross-sectional views illustrating structures resulting from different stages of forming a substrate structure according to some implementations of the present disclosure.
First, as illustrated in fig. 4A, a substrate 101 is provided, and a first semiconductor layer 102 is formed on the substrate 101.
In some embodiments, the material of the substrate 201 and the first semiconductor layer 102 may be the same. For example, the substrate 201 may be a SiC substrate, and the first semiconductor layer 102 may be a SiC epitaxial layer epitaxially formed on the substrate 201. For example, the doping concentration of the substrate 201 is greater than the doping concentration of the first semiconductor layer 102.
Then, as shown in fig. 4B, a mask layer 402 having a second opening 412 is formed on the first semiconductor layer 102.
For example, a mask material layer may be formed on the first semiconductor layer 102 and then patterned to form the mask layer 402 having the second opening 412. The number of the second openings 412 may be determined according to the number of doped regions desired to be formed. As some implementations, the material of the mask layer 402 may include polysilicon, silicon nitride, and the like. By way of example, the thickness of the mask layer 402 may range from 2 microns to 2.5 microns, e.g., 2.2 microns, etc.
In some embodiments, the buffer layer 401 may be first formed on the first semiconductor layer 102, and then the mask layer 402 may be formed on the buffer layer 401. As some implementations, the buffer layer 401 may be an oxide layer. By way of example, the buffer layer 401 may have a thickness in the range of 0.5 microns to 1 micron, e.g., 0.8 microns, etc.
Thereafter, as shown in fig. 4C, the first semiconductor layer 102 under the second opening 412 is doped by using the mask layer 402 as a mask to form one or more doped regions 103. In addition, an annealing process may be performed after the doping to activate the impurities in the doped region 103.
For example, the doping may be ion implantation. For example, the doped impurities may include Al. In the case where the impurity includes Al, the loss of the impurity in the subsequent annealing process may be reduced.
In addition, it is to be understood that in the case where the buffer layer 401 is formed on the first semiconductor layer 102, the buffer layer 401 may play a role of protecting the first semiconductor layer 102 in a doping process (e.g., ion implantation), for example, lattice defects generated in the doped region 103 by the ion implantation may be reduced.
Thereafter, after the doped region 103 is formed, the mask layer 402 is removed, so that a substrate structure shown in fig. 3A can be formed. It is to be understood that in the case where the buffer layer 401 is formed on the first semiconductor layer 102, the buffer layer 401 is also removed after the doped region 103 is formed.
While exemplary formation processes of substrate structures according to some implementations of the present disclosure have been described above, it should be understood that the substrate structures are not limited to being formed in the above manner.
Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (20)
1. A semiconductor device, comprising:
a substrate;
a first semiconductor layer on the substrate;
a doped region in the first semiconductor layer, the doped region and the first semiconductor layer having different conductivity types;
a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having a material with a forbidden band width greater than that of the first semiconductor layer; and
a first metal layer on the second semiconductor layer and in Schottky contact with the second semiconductor layer.
2. The semiconductor device according to claim 1, wherein the second semiconductor layer comprises a nanostructure.
3. The semiconductor device of claim 2, wherein the nanostructure layer comprises at least one of quantum dots and nanowires.
4. The semiconductor device according to claim 1, wherein the second semiconductor layer has a first opening, an orthographic projection of the first opening on the substrate at least partially overlaps with an orthographic projection of the doped region on the substrate;
the semiconductor device further includes:
and a second metal layer in the first opening and forming ohmic contact with the doped region, wherein the first metal layer is positioned on the second metal layer.
5. The semiconductor device according to claim 1, wherein a material of the first semiconductor layer comprises SiC, and a material of the second semiconductor layer comprises GaN.
6. The semiconductor device according to claim 1, wherein an impurity of the doped region comprises Al.
7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is a diode.
8. A method of manufacturing a semiconductor device, comprising:
providing a substrate structure comprising a substrate, a first semiconductor layer on the substrate, and a doped region in the first semiconductor layer, the doped region and the first semiconductor layer having different conductivity types;
forming a second semiconductor layer on the first semiconductor layer, wherein the forbidden band width of the material of the second semiconductor layer is larger than that of the material of the first semiconductor layer; and
and forming a first metal layer on the second semiconductor layer, wherein Schottky contact is formed between the first metal layer and the second semiconductor layer.
9. The method of claim 8, wherein the second semiconductor layer comprises a nanostructure layer.
10. The method of claim 9, wherein the nanostructure layer comprises at least one of quantum dots and nanowires.
11. The method of claim 8, wherein the second semiconductor layer has a first opening, an orthographic projection of the first opening on the substrate at least partially overlapping an orthographic projection of the doped region on the substrate;
before forming the first metal layer, further comprising:
and forming a second metal layer which forms ohmic contact with the doped region in the first opening, wherein the first metal layer is positioned on the second metal layer.
12. The method of claim 11, wherein the second semiconductor layer comprises quantum dots;
forming the second metal layer and the second semiconductor layer by:
forming a second preliminary semiconductor layer on the substrate structure, the second preliminary semiconductor layer having the first opening;
forming the second metal layer in the first opening;
performing a first anneal to cause the ohmic contact to be formed between the second metal layer and the doped region and to cause the second preliminary semiconductor layer to become the second semiconductor layer including quantum dots.
13. The method of claim 8, wherein after forming the first metal layer on the second semiconductor layer, a second anneal is performed to form the schottky contact.
14. The method of claim 8, wherein the material of the first semiconductor layer comprises SiC and the material of the second semiconductor layer comprises GaN.
15. The method of claim 8, wherein the providing a substrate structure comprises:
providing the substrate;
forming the first semiconductor layer on the substrate;
forming a mask layer having a second opening on the first semiconductor layer;
doping the first semiconductor layer below the second opening by using the mask layer as a mask to form the doped region;
after the doped region is formed, the mask layer is removed.
16. The method of claim 15, wherein the doping comprises ion implantation.
17. The method of claim 15, wherein the doped impurities comprise Al.
18. The method of claim 15, wherein the providing a substrate structure further comprises:
forming a buffer layer on the first semiconductor layer;
forming the mask layer on the buffer layer;
and removing the buffer layer after the doped region is formed.
19. The method of claim 18, wherein the buffer layer comprises an oxide layer.
20. The method of any of claims 8-19, wherein the semiconductor device is a diode.
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