JP2008027430A - Personal information management system and nonvolatile memory card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a personal information management system capable of solving the problem of data leakage, and to provide a nonvolatile memory card applied to the personal information management system. <P>SOLUTION: The personal information management system is provided with: a communication control unit 501 which transmits and receives data to/from a terminal; a personal information recording medium 500 including an encoding unit which encodes the received data and the nonvolatile memory which stores the encoded data; a terminal including a communication control unit 521 which transmits and receives data to/from the personal information recording medium and a server 520, a display portion which displays the received data, and an input unit; and the server including a communication control unit which transmits and receives data to/from the terminal; a decoding unit 522 which decodes the encoded data, an identification data recording portion; and a means which compares the decoded data with data in the identification data recording portion. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a personal information management system and a nonvolatile memory card applicable to the personal information management system.

  In recent years, standardization of standards, test operations for various applications, and the like have begun for practical use of RFID (Radio Frequency IDentification) tags (also called ID tags, IC tags, wireless tags, and wireless chips). RFID tags are characterized by their communication distance, protocol used, etc., depending on the frequency band in which they are operated, but all have a great advantage in that they can respond in a non-contact manner and are highly convenient. Therefore, a wide range of development such as various personal authentication, fare payment, and game fields is expected (for example, Patent Document 1).

  By the way, the current authentication method using a cash card, membership card, etc., generally uses a plurality of account numbers or membership numbers and PIN numbers recorded in the card to store a plurality of It is done by getting correspondence with only one of the personal information. In this method, the cash card and membership card owned by the user are the keys to call up personal information stored on the server, and as a security measure, it is also used to enter a password. There are many cases.

In other words, for example, even if you try to illegally use a card picked up by a third party, it will not be authenticated unless both the card and PIN are available, so it is a long-established authentication method. One of the mainstream.
JP 2002-56171 A

  However, companies that issue cash cards and membership cards must operate a server that stores a large amount of personal information, and must always be connected to some network. Therefore, it is necessary to pay close attention to information leakage. In particular, when personal information is shared and used by a plurality of stores as disclosed in Patent Document 1, there is a high risk of information leakage.

  In addition, in the situation where the maintenance of computer networks has progressed and it is possible to easily connect to the Internet environment in ordinary homes, the server may be exposed to an environment where an unspecified number of computers are connected. There is a problem that a lot of personal information leaks frequently due to access. From the user's point of view, personal information leakage where there is no negligence and management does not reach is a sufficient problem to reduce trust in the company.

  In view of the above problems, an object of the present invention is to provide a personal information management system that solves the problem of information leakage and a nonvolatile memory card that is applied to the personal information management system.

  The personal information management system of the present invention has a personal information recording medium, a terminal, and a server. The personal information recording medium includes a first communication control unit that transmits and receives information to and from the terminal, an encryption unit that encrypts received information, and a nonvolatile memory that stores the encrypted information. be able to. The terminal can be configured to include a second communication control unit that transmits / receives information to / from the personal information recording medium and the server, a display unit that displays received information, and an input unit. The server includes a third communication control unit that transmits and receives information to and from the terminal, a decryption unit that decrypts the encrypted information, a password data recording unit, and decrypted information and information of the password data recording unit. And means for comparing and referencing.

  Further, as the personal information recording medium, for example, a card (nonvolatile memory card) provided with an RFID tag having a nonvolatile memory can be used, and a name, an address, etc. are stored in the nonvolatile memory provided in the RFID tag. It is characterized in that various information including personal information is stored in an encrypted state. In other words, personal information such as name and address is stored in a non-volatile memory card, and the personal information is not stored on the server side but password data used as a key for personal authentication is stored.

  In addition, transmission / reception of information between the personal information recording medium and the terminal or transmission / reception of information between the terminal and the server is performed by wireless communication or wired communication. One may be performed by wireless communication and the other may be performed by wired communication, or both may be performed by wireless communication.

  The non-volatile memory card of the present invention includes a communication control means for transmitting / receiving information to / from a reader / writer, an encryption means for encrypting received information, an information processing means for processing encrypted information, and an encryption And a non-volatile memory for storing the received information, the communication control means has an antenna, and transmits / receives information to / from the reader / writer by wireless communication. The communication control means of the nonvolatile memory card is characterized in that it transmits encrypted information to the reader / writer and receives an unencrypted original communication text (plain text) from the reader / writer.

  By using the personal information management system of the present invention, personal information that is highly dangerous against leakage is not normally stored on the server side, and a personal information recording medium such as a nonvolatile memory card owned by the user Stored in. Therefore, the risk of a large amount of personal information being leaked due to unauthorized access to the server via the network, mistakes in the company, reading of data due to fraud, etc. is eliminated.

  In addition, even if the secret data stored in the server is leaked, they are merely random numbers that do not make sense alone, and the risk of misuse of the data is low. It is provided as a safe and new form of customer management in companies with a large number of customers.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

  First, the authentication method of the personal information management system of the present invention will be briefly described with reference to FIG.

  In the present invention, a personal information recording medium 500 owned by a user is provided with a CPU having functions such as encryption and decryption and a writable / erasable nonvolatile memory, and various information including personal information is stored in a server 520. Instead, it is stored in an encrypted state in a non-volatile memory of a personal information recording medium. On the other hand, on the server 520 side, not personal information but personal identification data as a key used for personal authentication is stored.

  When the personal information recording medium is recognized by the terminal 510, the encrypted personal information is read from the personal information recording medium and decrypted by the server 520. Subsequently, the personal identification data stored in the server 520 is used to compare with the information read from the personal information recording medium 500. Authentication is performed when the password data corresponding to the information read from the personal information recording medium 500 exists.

  By using the authentication method as described above, personal information having a high risk of leakage is not normally stored on the server 520 side, but is stored in the personal information recording medium 500 owned by the user. As a result, it is possible to prevent the risk of leakage of a large amount of personal information due to unauthorized access to the server 520 via the network, reading of data due to a mistake in the company, and the like. Even if the password data stored in the server 520 is leaked, they are merely random numbers that are meaningless by themselves, and the risk of misuse of the data is low.

  Hereinafter, a specific configuration related to the personal information management system of the present invention will be described.

(Embodiment 1)
In this embodiment, an example of a nonvolatile memory card of the present invention and a personal information management system using the nonvolatile memory card will be described with reference to the drawings.

  The personal information management system shown in this embodiment includes a personal information recording medium 500, a terminal 510, and a server 520 (FIG. 1).

  The personal information recording medium 500 includes a communication control unit 501, an encryption unit 502, an information processing unit 503, and a storage circuit 504 having a nonvolatile memory. Here, an example in which the encryption unit 502 is provided as a part of the information processing unit 503 is shown.

  The communication control unit 501 only needs to be capable of transmitting / receiving information to / from the terminal 510. Here, an antenna is provided in the communication control unit 501 of the personal information recording medium 500, and information is transmitted to and received from the terminal 510 by wireless communication. Further, the communication control unit 501 can have a structure provided with a resonance circuit, a demodulation circuit, a modulation circuit, an encoding circuit, a decoding circuit, an information determination circuit, and the like.

  The information processing unit 503 includes a circuit that processes data when information is transmitted / received to / from the outside. For example, the information processing unit 503 can be provided by a CPU (central processing unit) having an encryption / decryption function. The storage circuit 504 records personal information (name, address, telephone number, date of birth, etc.) and the like. Further, the personal information is recorded in the storage circuit 504 in a state encrypted by the encryption unit 502. The memory circuit 504 can be provided by a rewritable nonvolatile memory or the like. The information recorded in the storage circuit 504 in encrypted form includes, for example, information provided by the user by exchanging with the server 520 in addition to information such as an individual name (member information of a store, online game) The history of user information etc. participating in the program can be encrypted and recorded.

  The terminal 510 includes a communication control unit 511, a control circuit 512, a display unit 513, and an input unit 514.

  The communication control unit 511 of the terminal 510 may be any device that can transmit and receive information to and from the personal information recording medium 500 and the server 520, and can be constructed by either a wired network or a wireless network. Here, transmission / reception of information between the terminal 510 and the personal information recording medium 500 is performed by wireless communication, and transmission / reception of information between the terminal 510 and the server 520 is performed by wired communication.

  The display unit 513 displays information received from the personal information recording medium 500 or the server 520. The display unit 513 can be provided by, for example, a liquid crystal display, a self-luminous element such as an organic EL or an inorganic EL, electronic paper, or the like. The input unit 514 refers to the content displayed on the display unit 513 and is used when inputting information or selecting by each user. As the input means, for example, a touch sensor that directly contacts the keyboard or the display unit can be used. Note that in this embodiment, the terminal 510 includes a reader / writer that transmits and receives information to and from the personal information recording medium 500. However, a reader / writer is provided separately and connected to a terminal such as a computer. May be.

  The server 520 includes a communication control unit 521, a decryption unit 522, a comparison reference unit 523, an information processing program 524, and a password data recording unit 525.

  The communication control unit 521 of the server 520 may be any device that can transmit and receive information to and from the terminal 510, and can be constructed by either a wired network or a wireless network. Here, transmission / reception of information with the terminal 510 is performed using wired communication. Decryption means 522 converts the encrypted information received from personal information recording medium 500 via terminal 510 into the original communication text (plain text).

  The comparison reference unit 523 compares the decrypted information with the data recorded in the personal identification data recording unit 525, and determines whether a predetermined condition is satisfied (whether it matches the data authentication). The data recorded in the personal identification data recording unit 525 is personal identification data serving as a key used for personal authentication, and information that can identify an individual is not recorded. The information processing program 524 has a program for driving the comparison reference means 523. Note that the comparison of the data in the comparison reference unit 523 may be performed before the encrypted data is decrypted by the decryption unit 522.

  Next, interaction with the personal information recording medium 500, the terminal 510, and the server 520 will be described.

  When the user holds the personal information recording medium 500 over a reader / writer provided in the terminal 510, the communication control means 511 of the terminal recognizes the information and transmits / receives information between the personal information recording medium 500 and the terminal 510. Specifically, the personal information encrypted and recorded in the storage circuit 504 of the personal information recording medium 500 is transmitted to the terminal 510 in an encrypted state. Then, the encrypted personal information is transmitted from the communication control unit 511 of the terminal 510 to the communication control unit 521 of the server 520 via a wired network.

  Next, the encrypted personal information is decrypted by the decrypting means 522 of the server 520, and then compared with the decrypted data using the personal identification data stored in the personal identification data recording unit 525 of the server 520. Is performed to determine whether or not a predetermined condition is satisfied. Authentication is completed only when the password data corresponding to the data read from the personal information recording medium 500 exists in the password data recording unit 525 of the server 520. That is, the password data recording unit 525 stores information that is a key for authenticating personal information.

  When the authentication is completed in the server 520, the decrypted information (plain text) is transmitted from the communication control unit 521 to the communication control unit 511 of the terminal 510 via the wired network, and is transmitted to the display unit 513 via the control circuit 512. By displaying the information, the user can check the information recorded on the personal information recording medium 500. Note that a password may be requested before displaying information on the display unit 513. By requesting a password, it is possible to effectively prevent the use of a third party who illegally acquired another person's personal information recording medium 500. Further, by using the owner's biometric information (fingerprint, voice print, vein) as a password, unauthorized use by a third party can be prevented more effectively. Of course, since the biometric information is extremely important information for an individual, it is recorded in the storage circuit 504 of the personal information recording medium 500 instead of being recorded in the terminal 510 or the server 520 that is not subject to personal management responsibility. It is preferable.

  Further, when the user newly inputs information or corrects information based on the information displayed on the display unit 513, the latest information is stored in the storage circuit 504 of the personal information recording medium 500. Encrypted and recorded. Specifically, the corrected information is transmitted from the communication control unit 511 of the terminal 510 to the communication control unit 501 of the personal information recording medium 500 by wireless communication, and encrypted by the encryption unit 502 included in the information processing unit 503. Is stored in the memory circuit 504.

  Thereafter, the information displayed on the display unit 513 of the terminal 510 is deleted, and no personal information remains in the server 520.

  By using the authentication method as described above, personal information having a high risk of leakage is not normally stored on the server side, but is stored in the personal information recording medium 500 owned by the user. As a result, it is possible to prevent the risk of leakage of a large amount of personal information due to unauthorized access to the server 520 via the network, mistakes in the company, reading of data due to fraud, and the like. Even if the password data stored in the server 520 is leaked, they are merely random numbers that are meaningless by themselves, and the risk of misuse of the data is low.

  In addition, if the user loses the personal information recording medium 500, the data stored in the personal information recording medium 500 may be read illegally, but it is encrypted and stored in the personal information recording medium 500. Decoding of information is not easy, and high security can be ensured in terms of security.

(Embodiment 2)
In this embodiment, an example of a specific structure of the personal information recording medium described in the above embodiment is described with reference to FIGS. Here, a structure (hereinafter also referred to as a “nonvolatile memory card”) in which an RFID tag (also referred to as an IC tag, an ID tag, a wireless tag, or a wireless chip) having a nonvolatile memory is provided on a card will be described.

  The nonvolatile memory card described in this embodiment includes a resonance circuit 702 having an antenna and a resonance capacitor, a power supply circuit 703, a clock generation circuit 704, a demodulation circuit 705, an information processing circuit 706, and memory elements such as a nonvolatile memory. A memory circuit 707, a modulation circuit 709, an A / D conversion circuit 708, a CPU 713, and an RF circuit 716 are included.

  The RF circuit 716 includes a resonance circuit 702. The resonance circuit 702 is connected to a power supply circuit 703, a clock generation circuit 704, a demodulation circuit 705, and a modulation circuit 709, and exchanges signals and power. Signals from the power supply circuit 703, the clock generation circuit 704, and the demodulation circuit 705 are input to the information processing circuit 706, and the CPU 713 provided in the information processing circuit 706 can be operated. The modulation circuit 709 outputs the signal received from the information processing circuit 706 to the resonance circuit 702 (the signal is input to the resonance circuit 702). In addition, the information processing circuit 706 and the storage circuit 707 exchange signals with each other. A signal from the A / D conversion circuit 708 is input to the information processing circuit 706, and an analog signal and a digital signal can be converted.

  Note that the nonvolatile memory card 701 described in this embodiment is not limited to the above structure, and may include a congestion control circuit or the like. As the nonvolatile memory, a rewritable flash memory, an EEPROM (Electrically Erasable Programmable Read Only Memory), a nonvolatile memory such as a ferroelectric memory, or the like can be used. In addition, a mask ROM (Read Only Memory) that cannot be rewritten, a write once write-once memory in which an organic substance or an inorganic substance is provided between electrodes, and the like may be used. Non-rewritable non-volatile memory can prevent tampering of unique information.

  The storage circuit 707 included in the nonvolatile memory card 701 stores personal information such as name, address, telephone number, date of birth, and the like after encryption. In addition, it is also possible to store individual biometric features (fingerprints, voiceprints, DNA information) as data. In addition, since the biometric feature is processed as two-dimensional pattern data and has a large amount of information compared to a name, an address, and the like, it is preferable to mount a storage element that can secure a sufficient capacity.

  The RF circuit 716 has a function of transmitting / receiving radio waves to / from the reader / writer 715 and can generate supply power for the nonvolatile memory card 701.

  The CPU 713 accesses the storage circuit 707 based on information sent from the RF circuit 716. Further, the CPU 713 has an encryption function, and when the personal information is recorded in the storage circuit 707, it is not stored in plain text but is encrypted and stored.

  The reader / writer 715 is connected to a terminal 712 having a display unit such as a computer. The reader / writer 715 and the terminal 712 may be connected by wireless communication or wired communication. The terminal 712 is also connected to the server 714 using a wired or wireless network.

  Next, the exchange between the nonvolatile memory card 701 and the reader / writer 715 will be described. As the reader / writer 715, a portable type or a fixed type can be used.

  A reader / writer 715 illustrated in FIG. 3 includes an antenna. A terminal 712 connected to the reader / writer 715 can control the reader / writer 715. In the nonvolatile memory card 701, when the resonance circuit 702 receives a radio wave emitted from the antenna of the reader / writer 715, a power supply potential is generated by the power supply circuit 703. Further, the demodulation circuit 705 demodulates information from the received radio wave. Transmission of information to the reader / writer 715 is performed by the modulation circuit 709. In this manner, the reader / writer 715 and the nonvolatile memory card 701 can transmit and receive information by wireless communication. Note that the terminal 712 may include a storage device.

  The reader / writer 715 is connected to the terminal 712 via the communication line 711 and can transmit / receive information to / from the nonvolatile memory card 701 under the control of the terminal 712. Note that a wireless communication line such as infrared communication may be used as the communication line 711 between the reader / writer 715 and the terminal 712 to exchange information.

  The resonance circuit 702 has a function of receiving radio waves emitted from the antenna of the reader / writer 715 and generating AC signals at both ends of the antenna. The generated AC signal becomes power of the nonvolatile memory card 701 and includes information such as a command transmitted from the reader / writer 715 antenna. The power supply circuit 703 has a function of generating a power supply potential by rectifying an AC signal generated in the resonance circuit 702 with a diode and smoothing it using a capacitor, and supplying the power supply potential to each circuit. The clock generation circuit 704 has a function of generating clock signals having various frequencies based on the AC signal generated in the resonance circuit 702. The demodulation circuit 705 has a function of demodulating information included in the AC signal generated in the resonance circuit 702.

  The information processing circuit 706 has a function of executing a series of operations in accordance with the instruction by extracting the instruction from the demodulated signal and controlling the storage circuit 707 and the A / D conversion circuit 708. Further, the information processing circuit 706 may have a function of checking whether there is an error in the demodulated signal. In addition, the information processing circuit 706 has a function of sending a write command to the storage circuit 707 and storing information stored in a register or the like in a storage area of the storage circuit 707. Of course, it can be performed without using a register. Similarly, the information processing circuit 706 can send a read command to the memory circuit 707 and read data. Then, a signal encoded by the encoding circuit in the information processing circuit 706 is generated and output to the modulation circuit 709.

  The memory circuit 707 can be provided with a rewritable nonvolatile memory such as a flash memory, an EEPROM, or a ferroelectric memory. The memory circuit 707 may be provided with a write-once memory. The write-once memory is a write-once and non-rewritable nonvolatile memory. Such a storage circuit 707 can hold information unique to the nonvolatile memory card 701.

  The modulation circuit 709 has a function of modulating a carrier wave based on the encoded signal.

  In this embodiment mode, an example in which the nonvolatile memory card 701 receives power supply from the antenna of the reader / writer 715 is described; however, the present invention is not limited to this mode. For example, the nonvolatile memory card 701 can supply power with a battery or the like inside, and can also transmit and receive information wirelessly with the antenna of the reader / writer 715. Further, a rechargeable battery can be provided as a battery to be mounted on the nonvolatile memory card 701, and a battery that can be charged by a wireless signal from the reader / writer 715 can be provided.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

(Embodiment 3)
In the present embodiment, a specific usage pattern of the personal information management system of the present invention will be described with reference to the drawings.

  First, a case where a service or the like is provided according to user information recorded in the nonvolatile memory card shown in the above embodiment will be described with reference to FIG.

  It is assumed that encrypted user information (name, address, sex, age, height, weight, etc.) is recorded in the storage circuit 504 of the nonvolatile memory card 500.

  When the user holds the nonvolatile memory card 500 over the terminal 510 equipped with a reader / writer, the encrypted information is transmitted to the server 520 via the terminal 510. Subsequently, after the information encrypted in the server 520 is decrypted by the decryption means 522, the personal identification data that is the key of the information is determined by using the comparison reference means 523, so that the personal identification data recording unit of the server 520 If it is recorded in 525, it is authenticated.

  After the authentication is completed in the server 520, the decrypted information is transmitted from the server 520 to the terminal 510, and service information with reference to the personal information of the user is displayed on the display unit 513 of the terminal 510. The service information can be provided through the display unit of the terminal by the company or the like according to the personal information recorded on the nonvolatile memory card. Further, by recording information such as services used by the user in the past as a history in the nonvolatile memory card 500, it becomes possible to provide more appropriate services for each user.

  In particular, if you have played the same game etc. many times at game centers or theme parks, various information optimized for each user can be recorded by recording the information you have experienced so far on a non-volatile memory card. Services can be provided. For example, when participating in the same online game a plurality of times, it is possible to record information acquired by past users in a nonvolatile memory card. In this case, it is possible to participate in the online game by taking over the previous information.

  In addition, by recording biometric information (information such as fingerprints, voiceprints, veins, retinas, DNA, etc.) in addition to an individual's name, address, age, etc. in a non-volatile memory card, the personal information of the present invention in the medical field Management system can be applied. This case will be described with reference to FIG.

  When the user holds the nonvolatile memory card 500 over the terminal 510 equipped with a reader / writer, the information recorded in the nonvolatile memory card 500 is transmitted to the server 520 via the terminal 510 in an encrypted state. Then, after the personal information encrypted by the server 520 is decrypted, the authentication is completed when the password data corresponding to the information is recorded in the password data recording unit 525 of the server 520 in the comparison and reference means 523. .

  After the authentication is completed, the decrypted information is transmitted from the server 520 to the terminal 510, and the personal biometric information can be confirmed on the display unit 513 of the terminal 510. In addition, a password may be requested before displaying biometric information on the display unit 513. By requesting a password, it is possible to effectively prevent the use of a third party who illegally obtained a non-volatile memory card of another person. Further, here, it is preferable to use the user's biometric information (fingerprint, voiceprint, vein) recorded on the nonvolatile memory card as the password.

  In hospitals or the like, when it is desired to record treatment data, prescription drug information, etc., the information is updated by the input means 514 provided in the terminal 510, and the updated information is encrypted in the nonvolatile memory card 500. Can be remembered. That is, the user can own and manage the medical record (electronic medical record).

  In recent years, attempts have been made to prevent unauthorized use by third parties by performing personal authentication using biometric information such as fingerprints and voiceprints. On the other hand, because the individual's biometric features can only identify an individual, the damage caused by leaking information is immeasurable. Therefore, when a large amount of individual biometric information is managed in a lump, various problems such as a management method are included. However, by using the management system described above, it is possible to prevent the risk of leakage of a large amount of personal information due to unauthorized access to a server via a network, reading illegal data inside a company, and the like. Even if the secret data stored in the server leaks, they are merely random numbers that do not make sense by themselves, and the risk of misuse of the data is low. In addition, if the user loses the nonvolatile memory card 500, the data stored in the nonvolatile memory card 500 may be read illegally, but it is encrypted and stored in the nonvolatile memory card 500. Decoding of information is not easy, and high security can be ensured in terms of security.

  Next, a management system in exchange with a financial institution using a nonvolatile memory card will be described with reference to FIG.

  In FIG. 5, the storage circuit 504 of the nonvolatile memory card 500 owned by the user includes personal information such as name, address, age, and telephone number, deposit information such as a deposit balance, and a unique ID of the nonvolatile memory card 500. Numbers etc. are recorded. Also, in the server 520, password data is recorded in the password data recording unit 525, and deposit information not including personal information is recorded in the deposit information recording unit 527 separately from the password data recording unit 525. Personal information such as name and deposit information are encrypted and stored.

  When the user holds the nonvolatile memory card 500 over a terminal 510 equipped with a reader / writer, the terminal 510 recognizes a unique ID number recorded in the nonvolatile memory card 500 and transmits the ID number to the server 520. Subsequently, in the server 520, the password code recorded in the password data recording unit 525 is compared with the received ID number, and if the corresponding ID number is stored in the password data recording unit 525 of the server 520, non-volatile Personal information such as name, deposit information and the like encrypted and stored in the storage circuit 504 of the memory card 500 are decrypted by the decryption means 522. Then, the comparison reference unit 526 determines whether the decrypted deposit information matches the deposit information stored in the deposit information recording unit 527 of the server 520. The authentication is completed only when the deposit information corresponding to the deposit information read from the nonvolatile memory card 500 exists in the deposit information recording unit 527.

  After the authentication is completed, the decrypted information is transmitted from the server 520 to the terminal 510, and the deposit information and the like are displayed on the display unit 513 of the terminal 510. The user can perform processing such as deposit and withdrawal using the input means 514 with reference to the information displayed on the display unit 513. Subsequently, when information is updated by processing such as depositing or withdrawing, the updated information is transmitted from the terminal 510 to the nonvolatile memory card 500, encrypted by the encryption unit 502, and then passed through the information processing unit 503. Is recorded in the memory circuit 504. On the other hand, the information recorded in the storage circuit 504 is transmitted to the server 520 via the terminal 510, and the deposit information recorded in the deposit information recording unit 527 of the server 520 is also updated. Note that the information updated in the terminal 510 may be transmitted to the nonvolatile memory card 500 and simultaneously transmitted to the server 520 to update the deposit information recorded in the deposit information recording unit 527 of the server 520.

  The personal information management system shown in FIG. 5 is effective when the company wants to store information such as deposit information. This is because if the deposit information or the like is stored only in the personal non-volatile memory card, there is a possibility that the company side may be damaged if it is illegally rewritten. However, the deposit information recorded in the deposit information recording unit 527 of the server 520 is information that does not include personal information. As a result, even if the deposit information is leaked, an individual is not specified and the risk of misuse of data is low.

  The personal identification code stored in the server and the deposit information are not linked to each other. In other words, it is preferable that a comparison is made with the deposit information recorded in the deposit information recording unit 527 based on the decrypted information only when the information encrypted by the user's use is decrypted. . In this case, even if the ID number and the deposit information are leaked due to unauthorized access to the server, the possibility that an individual can be specified is reduced.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

(Embodiment 4)
In this embodiment, a structure of a nonvolatile memory element included in a memory circuit included in a nonvolatile memory card and an operation method thereof will be described.

  FIG. 16 is a cross-sectional view for explaining the main configuration of the memory circuit included in the nonvolatile memory card according to the present invention. FIG. 16 particularly shows a main part of a nonvolatile memory element included in the memory circuit. This nonvolatile memory element is manufactured using a substrate 10 having an insulating surface. As the substrate 10 having an insulating surface, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate having an insulating film formed on the surface, or the like can be used.

  A semiconductor layer 14 is formed over the substrate 10 having the insulating surface. A base insulating film 12 may be provided between the substrate 10 and the semiconductor layer 14. The base insulating film 12 prevents impurities such as alkali metals from diffusing from the substrate 10 to the semiconductor layer 14 and is contaminated, and may be appropriately provided as a blocking layer.

  As the base insulating film 12, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like, using a CVD method, a sputtering method, or the like. It forms using. For example, in the case where the base insulating film 12 has two structures, a silicon nitride oxide film may be formed as the first insulating film, and a silicon oxynitride film may be formed as the second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film.

  The semiconductor layer 14 is preferably formed using a single crystal semiconductor or a polycrystalline semiconductor. For example, after the semiconductor layer formed on the entire surface of the substrate 10 is crystallized on the substrate 10 by a sputtering method, a plasma CVD method, or a low pressure CVD method, the semiconductor layer 14 can be formed by selective etching. That is, for the purpose of element isolation, it is preferable to form an island-shaped semiconductor layer on the insulating surface and to form one or more nonvolatile memory elements on the semiconductor layer. As the semiconductor material, silicon is preferable, and a silicon germanium semiconductor can also be used. As a method for crystallizing a semiconductor layer, laser crystallization, rapid thermal annealing (RTA), crystallization by heat treatment using a furnace annealing furnace, crystallization using a metal element that promotes crystallization, or a combination of these methods Can be adopted. Further, instead of such a thin film process, a so-called SOI (Silicon on Insulator) substrate in which a single crystal semiconductor layer is formed on an insulating surface may be used.

  Thus, by separating and forming the semiconductor layer formed on the insulating surface in an island shape, even when the memory element array and the peripheral circuit are formed on the same substrate, the element can be effectively separated. That is, a memory element array that needs to be written and erased at a voltage of about 10V to 20V and a peripheral circuit that operates at a voltage of about 3V to 7V and mainly performs data input / output and command control on the same substrate. Even when formed, mutual interference due to a difference in voltage applied to each element can be prevented.

A p-type impurity may be implanted into the semiconductor layer 14. For example, boron is used as the p-type impurity, and may be added at a concentration of about 5 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ . This is for controlling the threshold voltage of the transistor, and acts effectively when added to the channel formation region. The channel formation region is formed in a region substantially coinciding with the gate 26 described later, and is located between the pair of impurity regions 18 of the semiconductor layer 14.

The pair of impurity regions 18 are regions functioning as a source region and a drain region in the nonvolatile memory element. The pair of impurity regions 18 is formed by adding phosphorus or arsenic which is an n-type impurity at a peak concentration of about 10 ²¹ atoms / cm ³ .

  A first insulating film 16, a floating gate electrode 20, a second insulating film 22, and a control gate electrode 24 are formed on the semiconductor layer 14. In this specification, from the floating gate electrode 20 to the control gate electrode 24. This stacked structure may be referred to as a gate 26.

  The first insulating film 16 is formed of silicon oxide or a stacked structure of silicon oxide and silicon oxynitride. The first insulating film 16 may be formed by depositing an insulating film by a plasma CVD method or a low pressure CVD method, but is preferably formed by solid phase oxidation or solid phase nitridation by plasma treatment. This is because an insulating film formed by oxidizing or nitriding a semiconductor layer (typically a silicon layer) by plasma treatment is dense, has high withstand voltage, and is excellent in reliability. Since the first insulating film 16 is used as a tunnel insulating film for injecting charges into the floating gate electrode 20, it is preferable that the first insulating film 16 be strong as described above. The first insulating film 16 is preferably formed to a thickness of 1 nm to 20 nm, preferably 3 nm to 6 nm. For example, when the gate length is 600 nm, the first insulating film 16 can be formed to a thickness of 3 nm to 6 nm.

As solid-phase oxidation treatment or solid-phase nitridation treatment by plasma treatment, the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less when excited by microwaves (typically 2.45 GHz), and It is preferable to use plasma having an electron temperature of 0.5 eV to 1.5 eV. This is because in the solid phase oxidation treatment or solid phase nitridation treatment, a dense insulating film is formed at a temperature of 500 ° C. or lower and a practical reaction rate is obtained.

When the surface of the semiconductor layer 14 is oxidized by this plasma treatment, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr, Xe) are used in an oxygen atmosphere. Or in an atmosphere of oxygen or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas). In the case of performing nitridation by plasma treatment, nitrogen and hydrogen are used in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere). Plasma treatment is performed in a rare gas atmosphere or in a rare gas atmosphere with NH ₃ . As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used.

  FIG. 15 shows a configuration example of an apparatus for performing plasma processing. This plasma processing apparatus includes a support base 88 for arranging the substrate 10, a gas supply unit 84 for introducing gas, an exhaust port 86 connected to a vacuum pump for exhausting gas, an antenna 80, and a dielectric plate. 82, a microwave supply unit 92 for supplying microwaves for plasma generation. In addition, the temperature of the substrate 10 can be controlled by providing the temperature control unit 90 on the support base 88.

  Hereinafter, the plasma treatment will be described. Note that plasma treatment includes oxidation treatment, nitridation treatment, oxynitridation treatment, hydrogenation treatment, and surface modification treatment for a semiconductor layer, an insulating film, and a conductive film. For these processes, a gas supplied from the gas supply unit 84 may be selected according to the purpose.

The oxidation treatment or nitridation treatment may be performed as follows. First, the processing chamber is evacuated and a plasma processing gas containing oxygen or nitrogen is introduced from the gas supply portion 84. The substrate 10 is heated to 100 ° C. to 550 ° C. by the room temperature or the temperature control unit 90. The interval between the substrate 10 and the dielectric plate 82 is about 20 mm to 80 mm (preferably 20 mm to 60 mm). Next, the microwave is supplied from the microwave supply unit 92 to the antenna 80. Then, plasma 94 is generated by introducing the microwave from the antenna 80 through the dielectric plate 82 into the processing chamber. When plasma excitation is performed by introduction of microwaves, plasma with a low electron temperature (3 eV or less, preferably 1.5 eV or less) and a high electron density (1 × 10 ¹¹ cm ⁻³ or more) can be generated. The surface of the semiconductor layer can be oxidized or nitrided by oxygen radicals (which may include OH radicals) and / or nitrogen radicals (which may include NH radicals) generated by this high-density plasma. When a rare gas such as argon is mixed with the plasma processing gas, oxygen radicals or nitrogen radicals can be efficiently generated by the excited species of the rare gas. This method can perform oxidation, nitridation, or oxynitridation by solid-phase reaction at a low temperature of 500 ° C. or lower by effectively using active radicals excited by plasma.

  In FIG. 16, an example of a suitable first insulating film 16 formed by plasma treatment is that the semiconductor layer 14 is formed with a thickness of 3 nm to 6 nm by plasma treatment under an oxidizing atmosphere, and then nitrogen is added. This is a stacked structure in which the silicon oxide layer surface is nitrided in an atmosphere to form a silicon layer containing oxygen and nitrogen (silicon oxynitride layer 16b). By oxidizing the surface of a silicon layer as a typical example of the semiconductor layer 14 by plasma treatment, a dense oxide film without distortion at the interface can be formed. Further, the oxide film can be further densified by nitriding the oxide film by plasma treatment to form a nitridation treatment layer by replacing oxygen in the surface layer portion with nitrogen. Thereby, an insulating film having a high withstand voltage can be formed.

  In any case, the heat formed at 950 ° C. to 1050 ° C. even when a glass substrate having a heat resistant temperature of 700 ° C. or less is used by using the solid phase oxidation treatment or solid phase nitridation treatment by the plasma treatment as described above. An insulating film equivalent to the oxide film can be obtained. That is, a highly reliable tunnel insulating film can be formed as the tunnel insulating film of the nonvolatile memory element.

  The floating gate electrode 20 is formed on the first insulating film 16. The floating gate electrode 20 is preferably formed of a semiconductor material such as silicon (Si) or germanium (Ge). In addition, as the floating gate electrode 20, an insulating film such as silicon nitride (SiNx), silicon nitride oxide (SiNxOy (x> y)), germanium nitride (GeNx), or the like that can accumulate charges may be used.

  Further, the band gap of the semiconductor material forming the floating gate electrode 20 is preferably smaller than the band gap of the semiconductor layer 14. For example, the band gap of the semiconductor material forming the floating gate and the band gap of the semiconductor layer have a difference of 0.1 eV or more, and the former is preferably smaller. In order to improve the charge (electron) injection property and the charge retention characteristics by lowering the energy level of the bottom of the conduction band of the floating gate electrode 20 from the energy level of the bottom of the conduction band of the semiconductor layer 14. is there.

  The semiconductor material forming the floating gate electrode 20 is a barrier against electrons of the floating gate electrode 20 formed by the first insulating film 16 against barrier energy against electrons of the semiconductor layer 14 formed by the first insulating film 16. It is preferable that energy becomes high. This is for facilitating injection of charges (electrons) from the semiconductor layer 14 to the floating gate and preventing the charges from disappearing from the floating gate electrode 20.

  Typically, the floating gate electrode 20 can be formed of germanium or a germanium compound as satisfying such conditions. A typical example of the germanium compound is silicon germanium. In this case, it is preferable that germanium is contained at 10 atomic% or more with respect to silicon. This is because if the concentration of germanium is less than 10 atomic%, the effect as a constituent element is reduced, and the band gap is not effectively reduced.

  The floating gate is applied to the nonvolatile memory card according to the present invention for the purpose of accumulating electric charges, but other semiconductor materials can be applied as long as they have similar functions. For example, a ternary semiconductor containing germanium may be used. Further, the semiconductor material may be hydrogenated. Further, as a function of a charge storage layer of a nonvolatile memory element, an oxide or nitride of the germanium or germanium compound, or an oxide or nitride layer containing the germanium or germanium compound can be used. .

  The second insulating film 22 is formed of a single layer of silicon oxide, silicon oxynitride (SiOxNy) (x> y), silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), aluminum oxide (AlxOy), or the like. A plurality of layers are formed by a low pressure CVD method, a plasma CVD method, or the like. The thickness of the second insulating film 22 is 1 nm to 20 nm, preferably 5 to 10 nm. For example, a silicon nitride layer 22a having a thickness of 3 nm and a silicon oxide layer 22b having a thickness of 5 nm can be used. Alternatively, plasma treatment may be performed on the floating gate electrode 20 to form a nitride film (for example, germanium nitride when germanium is used as the floating gate electrode 20) by nitriding the surface of the floating gate electrode 20. In any case, the first insulating film 16 and the second insulating film 22 are either a nitride film or a nitrided layer on one or both sides in contact with the floating gate electrode 20, so that the floating gate electrode 20 Oxidation can be prevented.

  The control gate electrode 24 is a metal selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), niobium (Nb), or the like, or contains these metals as a main component. It is preferable to form with an alloy material or a compound material. Alternatively, polycrystalline silicon to which an impurity element such as phosphorus is added can be used. Further, the control gate electrode 24 may be formed by a laminated structure of one or more metal nitride layers 24a and the metal layer 24b. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride layer 24a, the adhesion of the metal layer 24b can be improved and peeling can be prevented. Further, since the metal nitride such as tantalum nitride has a high work function, the thickness of the first insulating film 16 can be increased by a synergistic effect with the second insulating film 22.

  By the way, in order to inject electrons into the floating gate electrode 20, there are a method using thermal electrons and a method using FN tunnel current. When thermoelectrons are used, a positive voltage is applied to the control gate electrode 24, and a high voltage is applied to the drain to generate thermoelectrons. Thereby, thermoelectrons can be injected into the floating gate electrode 20. When an FN type tunnel current is used, a positive voltage is applied to the control gate electrode 24 and injected from the semiconductor layer 14 into the floating gate electrode 20 by the FN type tunnel current.

  FIG. 6A shows an applied voltage when injecting into the floating gate electrode 20 by the FN type tunnel current. A positive high voltage (10V to 20V) is applied to the control gate electrode 24, and the source region 18a and the drain region 18b are set to 0V. Electrons in the semiconductor layer 14 are injected into the first insulating film 16 by the high electric field, and an FN tunnel current flows.

  This data “0” is detected by detecting that the transistor does not turn on when a gate voltage that turns on the nonvolatile memory element is applied in a state where no electric charge is held in the floating gate electrode 20. Is possible. Alternatively, as shown in FIG. 6B, it is determined whether or not the nonvolatile memory element is conductive when a bias is applied between the source region 18a and the drain region 18b and the control gate electrode 24 is set to 0V. Can do.

  FIG. 7A shows a state in which charges are released from the floating gate electrode 20 and data is erased from the nonvolatile memory element. In this case, a negative bias is applied to the control gate electrode 24 and an FN tunnel current is caused to flow between the semiconductor layer 14 and the floating gate electrode 20. Alternatively, as shown in FIG. 7B, a negative bias is applied to the control gate electrode 24, and a positive high voltage is applied to the source region 18a, thereby generating an FN type tunnel current. Electrons may be extracted to the 18a side.

  Various types of memory circuits can be obtained using such a nonvolatile memory element. FIG. 8 shows an example of an equivalent circuit of a nonvolatile memory cell array. The memory cell MS01 that stores 1-bit information includes a selection transistor S01 and a nonvolatile memory element M01. The selection transistor S01 is inserted in series between the bit line BL0 and the nonvolatile memory element M01, and the gate is connected to the word line WL1. The gate of the nonvolatile memory element M01 is connected to the word line WL11. When data is written to the nonvolatile memory element M01, when the word line WL1 and the bit line BL0 are set to the H level and the BL1 is set to the L level and a high voltage is applied to the word line WL11, charges are accumulated in the floating gate as described above. The When erasing data, the word line WL1 and the bit line BL0 are set to H level, and a negative high voltage is applied to the word line WL11.

  In this memory cell MS01, the select transistor S01 and the non-volatile memory element M01 are formed by the semiconductor layers 30 and 32 formed in an island shape on the insulating surface, respectively, so that no element isolation region is provided. Interference with other selection transistors or nonvolatile memory elements can be prevented. Further, since both the select transistor S01 and the nonvolatile memory element M01 in the memory cell MS01 are n-channel type, by forming both of them in a semiconductor layer separated into one island shape, a wiring for connecting the two elements is formed. Can be omitted.

  FIG. 9 shows a NOR-type equivalent circuit in which a nonvolatile memory element is directly connected to a bit line. In this memory cell array, word lines WL and bit lines BL are arranged so as to intersect with each other, and nonvolatile memory elements are arranged at each intersection. In the NOR type, the drain of each nonvolatile memory element is connected to the bit line BL. The sources of the nonvolatile memory elements are commonly connected to the source line SL.

  Also in this case, in the memory cell MS01, the non-volatile memory element M01 is formed of the semiconductor layer 32 formed on the insulating surface so as to be separated into islands, so that other non-volatile elements can be provided without providing an element isolation region. Interference with the memory element can be prevented. Further, a plurality of nonvolatile memory elements (for example, M01 to M23 shown in FIG. 9) are handled as one block, and these nonvolatile memory elements are formed by a semiconductor layer separated into one island shape, thereby making a block unit. The erase operation can be performed with.

  The NOR type operation is, for example, as follows. In data writing, the source line SL is set to 0 V, a high voltage is applied to the word line WL selected for writing data, and a potential corresponding to data “0” and “1” is applied to the bit line BL. For example, H level and L level potentials are applied to the bit line BL for “0” and “1”, respectively. In order to write “0” data, in the nonvolatile memory element to which H level is given, hot electrons are generated in the vicinity of the drain, and this is injected into the floating gate. In the case of “1” data, such electron injection does not occur.

  In a memory cell to which “0” data is given, hot electrons are generated in the vicinity of the drain due to a strong lateral electric field between the drain and the source, and this is injected into the floating gate electrode. As a result, the state where electrons are injected into the floating gate and the threshold voltage becomes high is “0”. In the case of “1” data, hot electrons are not generated, electrons are not injected into the floating gate, and a low threshold voltage state, that is, an erased state is maintained.

  When erasing data, a positive voltage of about 10 V is applied to the source line SL, and the bit line BL is left floating. Then, a negative high voltage is applied to the word line (a negative high voltage is applied to the control gate), and electrons are extracted from the floating gate. As a result, the data “1” is erased.

  For data reading, the source line SL is set to 0V and the bit line BL is set to about 0.8V, and the selected word line WL is set to an intermediate value between the threshold values of data “0” and “1”. A voltage is applied, and the presence / absence of current draw in the nonvolatile memory element is determined by a sense amplifier connected to the bit line BL.

  FIG. 10 shows an equivalent circuit of the NAND memory cell array. A NAND cell NS1 in which a plurality of nonvolatile memory elements are connected in series is connected to the bit line BL. A plurality of NAND cells gather to constitute a block BLK. The block BLK1 shown in FIG. 10 has 32 word lines (word lines WL0 to WL31). The nonvolatile memory elements located in the same row of the block BLK1 are commonly connected to word lines corresponding to this row.

  In this case, since the select transistors S1 and S2 and the nonvolatile memory elements M0 to M31 are connected in series, these may be formed as a single semiconductor layer 34. Accordingly, wiring for connecting the nonvolatile memory elements can be omitted, so that integration can be achieved. Further, it is possible to easily separate the adjacent NAND cells. Further, the semiconductor layer 36 of the select transistors S1 and S2 and the semiconductor layer 38 of the NAND cell may be formed separately. When performing an erasing operation for extracting charges from the floating gates of the nonvolatile memory elements M0 to M31, the erasing operation can be performed in units of the NAND cells. Further, the nonvolatile memory elements (for example, the row of M30) commonly connected to one word line may be formed by one semiconductor layer 40.

  The write operation is executed after the NAND cell NS1 is in the erased state, that is, the threshold value of each nonvolatile memory element of the NAND cell NS1 is in a negative voltage state. Writing is performed in order from the memory element M0 on the source line SL side. An example of writing to the memory element M0 is as follows.

  In FIG. 11A, when "0" is written, for example, Vcc (power supply voltage) is applied to the selection gate line SG2 to turn on the selection transistor S2 and to set the bit line BL0 to 0 V (ground voltage). The selection gate line SG1 is set to 0V, and the selection transistor S1 is turned off. Next, the word line WL0 of the memory element M0 is set to the high voltage Vpgm (about 20V), and the other word lines are set to the intermediate voltage Vpass (about 10V). Since the voltage of the bit line BL is 0V, the potential of the channel formation region of the selected memory element M0 is 0V. Since the potential difference between the word line WL0 and the channel formation region is large, electrons are injected into the floating gate of the memory element M0 by the FN tunnel current as described above. As a result, the threshold voltage of the memory element M0 becomes positive (a state in which “0” is written).

  On the other hand, when "1" is written, the bit line BL is set to Vcc (power supply voltage), for example, as shown in FIG. Since the voltage of the selection gate line SG2 is Vcc, the selection transistor S2 is cut off when Vcc minus Vth (Vcc−Vth) with respect to the threshold voltage Vth of the selection transistor S2. Accordingly, the channel formation region of the memory element M0 is in a floating state. Next, when the high voltage Vpgm (20 V) is applied to the word line WL0 and the intermediate voltage Vpass (10 V) is applied to the other word lines, the capacitive coupling between each word line and the channel formation region causes the channel formation region. The voltage rises from Vcc-Vth and becomes about 8V, for example. Since the voltage of the channel formation region is boosted to a high voltage, the potential difference between the word line WL0 and the channel formation region is small unlike the case of writing “0”. Therefore, electron injection due to the FN tunnel current does not occur in the floating gate of the memory element M0. Therefore, the threshold value of the memory element M1 is maintained in a negative state (a state in which “1” is written).

  When performing the erase operation, as shown in FIG. 12A, a negative high voltage (Vers) is applied to all the word lines in the selected block. The bit line BL and the source line SL are brought into a floating state. Thereby, electrons in the floating gate are emitted to the semiconductor layer by the tunnel current in all the memory elements of the block. As a result, the threshold voltages of these memory elements shift in the negative direction.

  In the reading operation shown in FIG. 12B, the voltage Vr (for example, 0 V) of the word line WL0 of the memory element M0 selected for reading is used, and the word lines WL1 to WL31 and the selection gate line SG1 of the non-selected memory elements are selected. SG2 is set to a read intermediate voltage Vread that is slightly higher than the power supply voltage. That is, as shown in FIG. 13, the memory elements other than the selected memory element function as transfer transistors. Thus, it is detected whether or not a current flows through the memory element M0 selected for reading. That is, when the data stored in the memory element M0 is “0”, the memory element M0 is off, and the bit line BL is not discharged. On the other hand, in the case of “1”, since the memory element M0 is turned on, the bit line BL is discharged.

  FIG. 14 shows an example of a block diagram of a memory circuit in the nonvolatile memory card. In the memory circuit, the memory cell array 52 and the peripheral circuit 54 are formed on the same substrate. The memory cell array 52 has a configuration as shown in FIG. 8, FIG. 9, and FIG. The configuration of the peripheral circuit 54 is as follows.

  A row decoder 62 for selecting a word line and a column decoder 64 for selecting a bit line are provided around the memory cell array 52. The address is sent to the control circuit 58 via the address buffer 56, and the internal row address signal and the internal column address signal are transferred to the row decoder 62 and the column decoder 64, respectively.

  For writing and erasing data, a potential obtained by boosting the power supply potential is used. Therefore, a booster circuit 60 controlled by the control circuit 58 according to the operation mode is provided. The output of the booster circuit 60 is supplied to the word line W and the bit line BL via the row decoder 62 and the column decoder 64. The sense amplifier 66 receives the data output from the column decoder 64. Data read by the sense amplifier 66 is held in the data buffer 68, and the data is randomly accessed under the control of the control circuit 58 and output via the data input / output buffer 70. The write data is temporarily held in the data buffer 68 via the data input / output buffer 70 and transferred to the column decoder 64 under the control of the control circuit 58.

  Thus, in the memory cell array 52, it is necessary to use a potential different from the power supply potential. Therefore, it is desirable that at least the memory cell array 52 and the peripheral circuit 54 are electrically isolated from each other. In this case, as in the embodiment described below, the non-volatile memory element and the peripheral circuit transistor are formed using a semiconductor layer formed over an insulating surface, whereby the insulation can be easily separated. Thereby, it is possible to obtain a non-volatile memory card with no malfunction and low power consumption.

  Hereinafter, the nonvolatile memory card according to the present invention will be described in detail by the following embodiments. In the structure of the present invention described below, reference numerals indicating the same elements are used in common in different drawings, and repetitive description in that case may be omitted.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

(Embodiment 5)
In this embodiment, an example of a nonvolatile memory card will be described with reference to the drawings. Here, in the non-volatile memory card, a non-volatile memory element that constitutes a memory portion, and an element such as a transistor that constitutes a logic portion that is provided on the same substrate as the memory portion and controls the memory portion. In the case of forming simultaneously.

  First, a schematic diagram of a memory unit in a nonvolatile memory card is shown in FIG.

  The memory portion described in this embodiment includes a plurality of memory cells each including a control transistor S and a nonvolatile memory element M. In FIG. 8, one memory cell is formed by the control transistor S01 and the nonvolatile memory element M01. Similarly, the control transistor S02 and the nonvolatile memory element M02, the control transistor S03 and the nonvolatile memory element M03, the control transistor S11 and the nonvolatile memory element M11, the control transistor S12 and the nonvolatile memory element M12, the control A memory cell is formed by the transistor S13 and the nonvolatile memory element M13.

  The gate electrode of the control transistor S01 is connected to the word line WL1, one of the source and the drain is connected to the bit line BL0, and the other is connected to the source or the drain of the nonvolatile memory element M01. The gate electrode of the nonvolatile memory element M01 is connected to the word line WL11, one of the source and the drain is connected to the source or the drain of the control transistor S01, and the other is connected to the source line SL.

  Note that the control transistor provided in the memory portion has a higher driving voltage than the transistor provided in the logic portion. Therefore, the gate insulating film of the transistor provided in the memory portion and the transistor provided in the logic portion are formed with different thicknesses. It is preferable to do. For example, it is preferable to provide a thin film transistor with a thin gate insulating film when the driving voltage is small and it is desired to reduce the variation in threshold voltage. When the driving voltage is large and the gate insulating film is required to have a withstand voltage, the gate insulating film is It is preferable to provide a thick thin film transistor.

  Therefore, in this embodiment, an insulating film with a small thickness is formed for a transistor in the logic portion where the driving voltage is small and the threshold voltage variation is small, and the withstanding voltage of the gate insulating film is large. A case where an insulating film having a large film thickness is formed for a required transistor of a memory portion will be described below with reference to the drawings. 22 to 24 are top views, and FIGS. 18 to 21 are cross-sectional views taken along lines AB, CD, EF, and GH in FIGS. In addition, a thin film transistor provided in the logic portion is shown between AB and CD, a non-volatile memory element provided in the memory portion is shown between EF, and a thin film transistor provided in the memory portion is shown between GH. Show. In this embodiment mode, a thin film transistor provided between A and B is a p-channel type, a thin film transistor provided between C and D, a thin film transistor provided between GH is an n channel type, and a carrier of a nonvolatile memory element provided between EF However, the nonvolatile memory card of the present invention is not limited to this.

First, island-shaped semiconductor layers 104, 106, 108, and 110 are formed over the substrate 100 with the insulating film 102 interposed therebetween, and the first insulating film is formed so as to cover the island-shaped semiconductor layers 104, 106, 108, and 110. 112, 114, 116, and 118 are formed, respectively. Then, a charge storage layer (here, a film containing germanium (Ge) as a main component) 120 functioning as a floating gate in the nonvolatile memory element is formed so as to cover the first insulating films 112, 114, 116, and 118. (See FIG. 18A). The island-shaped semiconductor layers 104, 106, 108, and 110 are formed using silicon (Si) as a main component by using a sputtering method, an LPCVD method, a plasma CVD method, or the like over the insulating film 102 formed in advance on the substrate 100. An amorphous semiconductor layer can be formed using (for example, Si _x Ge _1-x ) or the like, and the amorphous semiconductor layer can be crystallized and then selectively etched. The crystallization of the amorphous semiconductor layer may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. Can be performed.

In the case where the semiconductor layer is crystallized or recrystallized by laser light irradiation, an LD-excited continuous wave (CW) laser (YVO ₄ , second harmonic (wavelength 532 nm)) is used as a laser light source. Can be used. The second harmonic is not particularly limited to the second harmonic, but the second harmonic is superior to higher harmonics in terms of energy efficiency. When the semiconductor layer is irradiated with the CW laser, energy is continuously given to the semiconductor layer. Therefore, once the semiconductor layer is in a molten state, the molten state can be continued. Furthermore, the solid-liquid interface of the semiconductor layer can be moved by scanning with a CW laser, and crystal grains that are long in one direction can be formed along the direction of this movement. The solid laser is used because the output stability is higher than that of a gas laser or the like, and stable processing is expected. Note that not only the CW laser but also a pulse laser having a repetition frequency of 10 MHz or more can be used. If a pulse laser with a high repetition frequency is used, the semiconductor layer can always remain in a molten state if the laser pulse interval is shorter than the time from when the semiconductor layer melts until it solidifies. A semiconductor layer including crystal grains that are long in one direction can be formed. Other CW lasers and pulse lasers with a repetition frequency of 10 MHz or more can also be used. For example, examples of the gas laser include an Ar laser, a Kr laser, and a CO ₂ laser. Examples of the solid-state laser include a YAG laser, a YLF laser, a YAlO ₃ laser, a GdVO ₄ laser, a KGW laser, a KYW laser, an alexandrite laser, a Ti: sapphire laser, a Y ₂ O ₃ laser, and a YVO ₄ laser. Further, there are ceramic lasers such as YAG laser, Y ₂ O ₃ laser, GdVO ₄ laser, and YVO ₄ laser. Examples of the metal vapor laser include a helium cadmium laser. In addition, it is preferable to emit laser light in TEM ₀₀ (single transverse mode) in a laser oscillator because energy uniformity of a linear beam spot obtained on the irradiated surface can be improved. In addition, a pulsed excimer laser may be used.

  The substrate 100 is selected from a glass substrate, a quartz substrate, a metal substrate (for example, a ceramic substrate or a stainless steel substrate), and a semiconductor substrate such as a Si substrate. In addition, a substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or acrylic can be selected as the plastic substrate.

  The insulating film 102 is formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y) by a CVD method, a sputtering method, or the like. Form. For example, in the case where the insulating film 102 has a two-layer structure, a silicon nitride oxide film may be formed as the first insulating film and a silicon oxynitride film may be formed as the second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film. In this manner, by forming the insulating film 102 functioning as a blocking layer, alkali metal such as Na or alkaline earth metal from the substrate 100 can be prevented from adversely affecting the element formed thereon. Note that the insulating film 102 may be omitted when quartz is used for the substrate 100.

  The first insulating films 112, 114, 116, and 118 can be formed by performing heat treatment, plasma treatment, or the like on the semiconductor layers 104, 106, 108, and 110. For example, by performing oxidation treatment, nitridation treatment, or oxynitridation treatment on the semiconductor layers 104, 106, 108, and 110 by high-density plasma treatment, an oxide film and a nitride film are formed on the semiconductor layers 104, 106, 108, and 110, respectively. Alternatively, first insulating films 112, 114, 116, and 118 that are to be oxynitride films are formed. In addition, you may form by plasma CVD method or a sputtering method.

  For example, in the case where a semiconductor layer containing Si as a main component is used as the semiconductor layers 104, 106, 108, and 110 and oxidation treatment or nitridation treatment is performed by high-density plasma treatment, the first insulating films 112, 114, 116, and 118 are performed. As a result, a silicon oxide (SiOx) film or a silicon nitride (SiNx) film is formed. Further, after the semiconductor layers 104, 106, 108, and 110 are oxidized by high-density plasma treatment, nitriding treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the semiconductor layers 104, 106, 108, and 110, and a film containing oxygen and nitrogen (hereinafter referred to as a “silicon oxynitride film”) is formed over the silicon oxide film. The first insulating films 112, 114, 116, and 118 are films in which a silicon oxide film and a silicon oxynitride film are stacked.

  Here, the first insulating films 112, 114, 116, and 118 are formed with a thickness of 1 to 10 nm, preferably 1 to 5 nm. For example, the semiconductor layers 104, 106, 108, and 110 are oxidized by high-density plasma treatment to form a silicon oxide film with a thickness of about 5 nm on the surfaces of the semiconductor layers 104, 106, 108, and 110, and then the high-density plasma treatment. Nitriding is performed to form a silicon oxynitride film having a thickness of about 2 nm on the surface of the silicon oxide film. In this case, the film thickness of the silicon oxide film formed on the surface of the semiconductor layers 104, 106, 108, 110 is approximately 3 nm. This is because the silicon oxynitride film is reduced by the amount formed. At this time, it is preferable that the oxidation treatment and the nitridation treatment by the high-density plasma treatment are continuously performed without being exposed to the atmosphere. By continuously performing the high-density plasma treatment, it is possible to prevent contamination from entering and improve production efficiency.

Note that in the case where the semiconductor layer is oxidized by high-density plasma treatment, an atmosphere containing oxygen (for example, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr And at least one of Xe), oxygen, or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas atmosphere. On the other hand, in the case of nitriding a semiconductor layer by high-density plasma treatment, an atmosphere containing nitrogen (for example, an atmosphere containing nitrogen (N ₂ ) and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe)) Under nitrogen, hydrogen, and rare gas atmosphere, or NH ₃ and rare gas atmosphere).

  As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. When the high-density plasma treatment is performed in a rare gas atmosphere, the first insulating films 112, 114, 116, and 118 are formed of at least one of the rare gases (He, Ne, Ar, Kr, and Xe) used for the plasma treatment. In the case where Ar is used, the first insulating films 112, 114, 116, and 118 may contain Ar.

The high-density plasma treatment is performed in an atmosphere of the above gas at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the plasma electron temperature is 0.5 eV to 1.5 eV. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor layers 104, 106, 108, and 110) formed on the substrate 100 is low, the object to be processed is damaged by the plasma. Can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point of the glass substrate, the oxidation or nitriding treatment can be sufficiently performed. As a frequency for forming plasma, a high frequency such as a microwave (eg, 2.45 GHz) can be used.

In this embodiment, when an object to be processed is oxidized by high-density plasma treatment, a mixed gas of oxygen (O ₂ ), hydrogen (H ₂ ), and argon (Ar) is introduced. The mixed gas used here may be introduced with 0.1 to 100 sccm of oxygen, 0.1 to 100 sccm of hydrogen, and 100 to 5000 sccm of argon. Note that the mixed gas is preferably introduced at a ratio of oxygen: hydrogen: argon = 1: 1: 100. For example, oxygen may be introduced at 5 sccm, hydrogen at 5 sccm, and argon at 500 sccm.

In addition, when performing nitriding treatment by high-density plasma treatment, a mixed gas of nitrogen (N ₂ ) and argon (Ar) is introduced. The mixed gas used here may be introduced at 20 to 2000 sccm of nitrogen and 100 to 10,000 sccm of argon. For example, nitrogen may be introduced at 200 sccm and argon at 1000 sccm.

  In this embodiment mode, the first insulating film 116 formed over the semiconductor layer 108 provided in the memory portion functions as a tunnel oxide film in a nonvolatile memory element completed later. Therefore, the thinner the first insulating film 116 is, the easier it is for the tunnel current to flow and the higher speed operation of the memory becomes possible. In addition, as the first insulating film 116 is thinner, charges can be accumulated in a floating gate formed later at a lower voltage, so that power consumption of the nonvolatile memory card can be reduced. Therefore, the first insulating films 112, 114, 116, and 118 are preferably formed thin.

  In general, there is a thermal oxidation method as a method for forming a thin insulating film over a semiconductor layer. However, when a substrate having a sufficiently low melting point such as a glass substrate is used as the substrate 100, the first method is performed by the thermal oxidation method. It is very difficult to form the insulating films 112, 114, 116, and 118. In addition, an insulating film formed by a CVD method or a sputtering method includes defects inside the film, so that the film quality is not sufficient, and there is a problem that defects such as pinholes occur when the film thickness is thin. In addition, in the case where an insulating film is formed by a CVD method or a sputtering method, the end of the semiconductor layer is not sufficiently covered, and the conductive layer and the like that are formed later on the first insulating film 116 and the semiconductor layer leak. There is a case. Therefore, as shown in this embodiment mode, by forming the first insulating films 112, 114, 116, and 118 by high-density plasma treatment, an insulating film denser than an insulating film formed by a CVD method, a sputtering method, or the like. In addition, end portions of the semiconductor layers 104, 106, 108, and 110 can be sufficiently covered with the first insulating films 112, 114, 116, and 118. As a result, high-speed operation and charge retention characteristics as a memory can be improved. Note that in the case where the first insulating films 112, 114, 116, and 118 are formed by CVD or sputtering, high-density plasma treatment is performed after forming the insulating film, and the surface of the insulating film is oxidized or nitrided. Alternatively, oxynitriding treatment is preferably performed.

The charge storage layer 120 can be formed of a film containing germanium such as germanium (Ge) or a silicon germanium alloy. Here, as the charge storage layer 120, a film containing germanium as a main component is formed with a thickness of 1 to 20 nm, preferably 5 to 10 nm, by performing a plasma CVD method in an atmosphere containing a germanium element (for example, GeH ₄ ). . In this manner, a film containing germanium having a smaller energy gap than Si is formed on the semiconductor layer with the first insulating film functioning as a tunnel oxide film formed using a material containing Si as a main component. When the charge storage layer is provided, the second barrier formed by the insulating film for the charge of the charge storage layer is energetically higher than the first barrier formed by the insulating film for the charge of the semiconductor layer. As a result, charge can be easily injected from the semiconductor layer into the charge storage layer, and the charge can be prevented from disappearing from the charge storage layer. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. In addition, the charge storage layer 120 formed over the semiconductor layer 108 provided in the memory portion functions as a floating gate in a nonvolatile memory element completed later.

  Next, the first insulating films 112, 114, 118 and the charge storage layer 120 formed over the semiconductor layers 104, 106, 110 are selectively removed, and the first insulating film formed over the semiconductor layer 108 is The insulating film 116 and the charge storage layer 120 are left. Here, the semiconductor layer 108, the first insulating film 116, and the charge storage layer 120 provided in the memory portion are selectively covered with a resist, and the first insulating film formed over the semiconductor layers 104, 106, and 110 is formed. 112, 114, 118 and the charge storage layer 120 are selectively removed by etching (see FIG. 18B).

  Next, a resist 122 is formed so as to selectively cover the semiconductor layers 104, 106, 110 and part of the charge storage layer 120 formed above the semiconductor layer 108, and the charges not covered by the resist 122. By selectively removing the storage layer 120 by etching, a part of the charge storage layer 120 is left to form the charge storage layer 121 (see FIGS. 18C and 24).

  Next, an impurity region is formed in a specific region of the semiconductor layer 110. Here, after the resist 122 is removed, a resist 124 is formed so as to selectively cover the semiconductor layers 104, 106, and 108 and part of the semiconductor layer 110, and impurities are added to the semiconductor layer 110 that is not covered with the resist 124. By introducing the element, the impurity region 126 is formed (see FIG. 19A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is introduced into the semiconductor layer 110 as the impurity element.

  Next, a second insulating film 128 is formed so as to cover the semiconductor layers 104, 106, and 110, the first insulating film 116 formed above the semiconductor layer 108, and the charge storage layer 121 (FIG. 19B). )reference).

  The second insulating film 128 is formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y) by using a CVD method, a sputtering method, or the like. A single layer or a stacked layer is formed using materials. For example, in the case where the second insulating film 128 is provided as a single layer, a silicon oxynitride film or a silicon nitride oxide film is formed with a thickness of 5 to 50 nm by a CVD method. In the case where the second insulating film 128 is provided in a three-layer structure, a silicon oxynitride film is formed as the first insulating film, a silicon nitride film is formed as the second insulating film, and the third insulating film 128 is formed. A silicon oxynitride film is formed as the insulating film. Alternatively, germanium oxide or nitride may be used for the second insulating film 128.

  Note that the second insulating film 128 formed above the semiconductor layer 108 functions as a control insulating film in a nonvolatile memory element to be completed later, and the second insulating film 128 formed above the semiconductor layer 110 is It functions as a gate insulating film in a transistor to be completed later.

  Next, a resist 130 is selectively formed so as to cover the second insulating film 128 formed above the semiconductor layers 108 and 110, and the second insulating film 128 formed on the semiconductor layers 104 and 106 is formed. This is selectively removed (see FIG. 19C).

  Next, third insulating films 132 and 134 are formed so as to cover the semiconductor layers 104 and 106, respectively (see FIG. 20A).

  The third insulating films 132 and 134 are formed by using any one of the methods described for forming the first insulating films 112, 114, 116, and 118. For example, by performing oxidation treatment, nitridation treatment, or oxynitridation treatment on the semiconductor layers 104, 106, 108, and 110 by high-density plasma treatment, a silicon oxide film, nitride film, or oxynitride is formed on the semiconductor layers 104 and 106, respectively. Third insulating films 132 and 134 to be films are formed.

  Here, the third insulating films 132 and 134 are formed with a thickness of 1 to 20 nm, preferably 1 to 10 nm. For example, after oxidizing the semiconductor layers 104 and 106 by high-density plasma treatment to form a silicon oxide film on the surfaces of the semiconductor layers 104 and 106, nitriding treatment is performed by high-density plasma treatment and the surface of the silicon oxide film is oxidized. A silicon nitride film is formed. In this case, the surface of the second insulating film 128 formed above the semiconductor layers 108 and 110 is also oxidized or nitrided to form an oxide film or an oxynitride film. The third insulating films 132 and 134 formed above the semiconductor layers 104 and 106 function as a gate insulating film in a transistor to be completed later.

  Next, a conductive film is formed so as to cover the third insulating films 132 and 134 formed above the semiconductor layers 104 and 106 and the second insulating film 128 formed above the semiconductor layers 108 and 110 (see FIG. (See FIG. 20B). Here, an example is shown in which a conductive film 136 and a conductive film 138 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

  The conductive films 136 and 138 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

  Here, the conductive film 136 is formed using tantalum nitride, and the conductive film 138 is formed using tungsten over the stacked structure. In addition, a single layer or stacked film selected from tungsten nitride, molybdenum nitride, or titanium nitride is used as the conductive film 136, and a single layer or stacked film selected from tantalum, molybdenum, or titanium is used as the conductive film 138. Can be used.

  Next, the conductive films 136 and 138 provided in a stacked manner are selectively etched and removed, so that the conductive films 136 and 138 are left over part of the semiconductor layers 104, 106, 108, and 110. Conductive films 140, 142, 144, and 146 that function as gate electrodes are formed (see FIGS. 20C and 23). Note that the conductive film 144 formed over the semiconductor layer 108 provided in the memory portion functions as a control gate in a nonvolatile memory element to be completed later. In addition, the conductive films 140, 142, and 146 function as gate electrodes in transistors that are completed later.

  Next, a resist 148 is selectively formed so as to cover the semiconductor layer 104, and an impurity element is introduced into the semiconductor layers 106, 108, and 110 using the resist 148 and the conductive films 142, 144, and 146 as masks. (See FIG. 21A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as the impurity element.

  In FIG. 21A, an impurity element 152 and a channel formation region 150 which form a source region or a drain region are formed in the semiconductor layer 106 by introducing an impurity element. In the semiconductor layer 108, an impurity region 156 that forms a source region or a drain region, a low-concentration impurity region 158 that forms an LDD region, and a channel formation region 154 are formed. In the semiconductor layer 110, an impurity region 162 that forms a source region or a drain region, a low-concentration impurity region 164 that forms an LDD region, and a channel formation region 160 are formed.

  Further, the low-concentration impurity region 158 formed in the semiconductor layer 108 is formed by the impurity element introduced in FIG. 21A penetrating through the charge accumulation layer 121 functioning as a floating gate. Accordingly, in the semiconductor layer 108, a channel formation region 154 is formed in a region overlapping with both the conductive film 144 and the charge storage layer 121, and a low-concentration impurity region 158 is formed in a region overlapping with the charge storage layer 121 and not overlapping with the conductive film 144. Thus, a high concentration impurity region 156 is formed in a region that does not overlap with both the charge storage layer 121 and the conductive film 144.

  Next, a resist 166 is selectively formed so as to cover the semiconductor layers 106, 108, and 110, and an impurity region is formed by introducing an impurity element into the semiconductor layer 104 using the resist 166 and the conductive film 140 as a mask ( (See FIG. 21B). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the semiconductor layers 106, 108, and 110 in FIG. 21A is introduced. As a result, an impurity region 170 and a channel formation region 168 that form a source region or a drain region are formed in the semiconductor layer 104.

  Next, an insulating film 172 is formed so as to cover the second insulating film 128, the third insulating films 132 and 134, and the conductive films 140, 142, 144, and 146, and the semiconductor layers 104 and 106 are formed over the insulating film 172. , 108, and 110, conductive films 174 that are electrically connected to the impurity regions 152, 156, 162, and 170, respectively, are formed (see FIGS. 21C and 22).

  The insulating film 172 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like by CVD or sputtering. Single layer made of an insulating film containing oxygen or nitrogen, a film containing carbon such as DLC (diamond-like carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin Alternatively, a stacked structure can be provided. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The conductive film 174 is formed by a CVD method, a sputtering method, or the like by aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper ( Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy material containing these elements as a main component or The compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive film 174 may employ, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. . Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the conductive film 174 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, so that the crystalline semiconductor layer is in good condition. Contact can be made.

  Next, an insulating film 176 is formed so as to cover the conductive film 174, and a conductive film 178 functioning as an antenna is formed over the insulating film 176 (see FIG. 36).

  The conductive film 178 functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  For the insulating film 176, any of the materials described in the description of the insulating film 172 can be used.

  In addition, as a signal transmission method in the nonvolatile memory card of the present invention, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like can be used. The transmission method may be appropriately selected by the practitioner in consideration of the intended use, and an optimal antenna may be provided according to the transmission method.

  Note that in the above structure, a plurality of nonvolatile memory elements may be provided in one island-like semiconductor layer. This case will be described with reference to FIGS. 17 shows a top view, and FIG. 25 shows a cross-sectional view between EF and GH in FIG.

  The memory circuit of the nonvolatile memory card illustrated in FIGS. 17 and 25 includes island-shaped semiconductor layers 200a and 200b that are electrically connected to the bit lines BL0 and BL1, respectively. A plurality of nonvolatile memory elements are provided in each of 200b (see FIGS. 17 and 25). Specifically, in the semiconductor layer 200a, a NAND cell 202a having a plurality of nonvolatile memory elements M0 to M30 and M31 is provided between the select transistors S01 and S02. In the semiconductor layer 200b, a NAND cell 202b having a plurality of nonvolatile memory elements is provided between the select transistors. Further, by providing the semiconductor layers 200a and 200b separately, the adjacent NAND cells 202a and NAND cells 202b can be insulated and separated.

  Further, by providing a plurality of nonvolatile memory elements in one island-like semiconductor layer, the nonvolatile memory elements can be more integrated and a large-capacity nonvolatile memory card can be formed.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

(Embodiment 6)
In this embodiment, a method for manufacturing a nonvolatile memory card different from that in the above embodiment will be described with reference to drawings. 26 to 28 are top views, FIGS. 30 to 35 are cross-sectional views taken along lines AB and EF in FIGS. 26 to 28, and FIG. 29 is FIGS. 26 to 28. Sectional drawing between CD in FIG. A line between A and B shows a transistor and a non-volatile memory element provided in the memory part, a line between CD and a non-volatile memory element provided in the memory part, and a line between E and F a transistor provided in the logic part. Show. In this embodiment, a transistor provided in the region 212 of the substrate 200 between E and F is a p-channel type, a transistor provided in the region 213 is an n-channel type, and a region of the substrate 200 between A and B is used. The case where the transistor provided in 214 is an n-channel transistor and the carrier of the nonvolatile memory element is moved by electrons will be described; however, the nonvolatile memory card of the present invention is not limited to this.

  First, an insulating film is formed over the substrate 200. Here, single crystal Si having n-type conductivity is used as the substrate 200, and the insulating film 202 and the insulating film 204 are formed over the substrate 200 (see FIG. 30A). For example, heat treatment is performed on the substrate 200 to form silicon oxide (SiOx) as the insulating film 202, and silicon nitride (SiNx) is formed over the insulating film 202 by a CVD method.

  The substrate 200 is not particularly limited as long as it is a semiconductor substrate. For example, a single crystal Si substrate having an n-type or p-type conductivity, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.), bonding method or SIMOX (Separation by IMplanted) An SOI (Silicon on Insulator) substrate manufactured using an OXygen method or the like can be used.

  Alternatively, the insulating film 204 may be provided by nitriding the insulating film 202 by high-density plasma treatment after the insulating film 202 is formed. Note that the insulating film provided over the substrate 200 may have a single layer structure or a stacked structure including three or more layers.

  Next, a pattern of a resist mask 206 is selectively formed over the insulating film 204, and selective etching is performed using the resist mask 206 as a mask, whereby a recess 208 is selectively formed in the substrate 200 (FIG. 30). (See (B)). Etching of the substrate 200 and the insulating films 202 and 204 can be performed by dry etching using plasma.

  Next, after removing the pattern of the resist mask 206, an insulating film 210 is formed so as to fill the recess 208 formed in the substrate 200 (see FIG. 30C).

  The insulating film 210 is formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y) by a CVD method, a sputtering method, or the like. Form. Here, as the insulating film 210, a silicon oxide film is formed using TEOS (tetraethylorthosilicate) gas by an atmospheric pressure CVD method or a low pressure CVD method.

  Next, the surface of the substrate 200 is exposed by performing a grinding process, a polishing process, or a CMP (Chemical Mechanical Polishing) process. Here, regions 212, 213, and 214 are provided between the insulating films 211 formed in the recesses 208 of the substrate 200 by exposing the surface of the substrate 200. The insulating film 211 is obtained by removing the insulating film 210 formed on the surface of the substrate 200 by grinding, polishing, or CMP. Subsequently, by selectively introducing an impurity element having p-type conductivity, p-wells 215 are formed in the regions 213 and 214 of the substrate 200 (FIGS. 31A, 28A, and 28B). ), FIG. 29 (A)).

  As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, boron (B) is introduced into the regions 213 and 214 as the impurity element.

  Note that in this embodiment, a semiconductor substrate having n-type conductivity is used as the substrate 200; therefore, no impurity element is introduced into the region 212; however, an impurity element exhibiting n-type is introduced. Thus, an n-well may be formed in the region 212. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used.

  On the other hand, when a semiconductor substrate having p-type conductivity is used, an n-type impurity element is introduced into the region 212 to form an n-well, and no impurity element is introduced into the regions 213 and 214. It is good.

  Next, first insulating films 216, 218, and 220 are formed over the regions 212, 213, and 214 provided in the substrate 200. Then, a floating gate electrode (a film containing germanium (Ge) as a main component) 222 is formed so as to cover the first insulating films 216, 218, and 220 (see FIG. 31B).

  The first insulating films 216, 218, and 220 can be formed of a silicon oxide film by performing heat treatment to oxidize the surfaces of the regions 212, 213, and 214 provided in the substrate 200. In addition, after a silicon oxide film is formed by a thermal oxidation method, the surface of the silicon oxide film is nitrided by performing nitriding treatment, whereby the silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. Can be formed with a structure.

  In addition, as described above, the first insulating films 216, 218, and 220 may be formed by plasma treatment. For example, in the case where the surface of the regions 212, 213, and 214 provided in the substrate 200 is oxidized or nitrided by high-density plasma treatment, a silicon oxide (SiOx) film or a first insulating film 216, 218, or 220 is used. A silicon nitride (SiNx) film is formed. In addition, after performing oxidation treatment on the surfaces of the regions 212, 213, and 214 by high-density plasma treatment, nitridation treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 212, 213, and 214, a silicon oxynitride film is formed over the silicon oxide film, and the first insulating films 216, 218, and 220 are formed of silicon oxide films. This is a film in which a silicon oxynitride film is stacked. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 212, 213, and 214 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

  In this embodiment, the first insulating film 220 formed over the region 214 provided in the memory portion in the substrate 200 functions as a tunnel oxide film in a nonvolatile memory element to be completed later. Therefore, the thinner the first insulating film 220 is, the more easily the tunnel current flows and the higher speed operation as a memory becomes possible. In addition, as the first insulating film 220 is thinner, charges can be accumulated in the floating gate electrode 222 at a lower voltage, so that power consumption of the nonvolatile memory card can be reduced. Therefore, the first insulating film 220 is preferably formed thin.

The floating gate electrode 222 can be formed of a film containing germanium such as germanium (Ge) or a silicon germanium alloy. Here, the floating gate electrode 222 is formed of a film containing germanium as a main component by performing a plasma CVD method in an atmosphere containing a germanium element (eg, GeH ₄ ). In this manner, a single crystal Si substrate is used as the substrate 200, and a film containing germanium having an energy gap smaller than that of Si is formed on a certain region of the Si substrate via a first insulating film functioning as a tunnel oxide film. The second barrier formed by the insulating film for the charge of the floating gate electrode is energetically higher than the first barrier formed by the insulating film for the charge in a certain region of the Si substrate. As a result, it is possible to easily inject charges from a region of the Si substrate into the floating gate electrode, and it is possible to prevent the charge from being lost from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. In addition, the floating gate electrode 222 formed above the region 214 provided in the memory portion in the substrate 200 functions as a floating gate in a nonvolatile memory element completed later.

  Next, a resist mask 223 is formed over the floating gate electrode 222, and the floating gate electrode 222 and the first insulating films 216, 218, and 220 are selectively removed using the resist mask 223 as a mask. Here, a resist mask 223 is formed so as to cover part of the region 214 in the substrate 200, and the floating gate electrode 222 and the first insulating films 216, 218, and 220 that are not covered with the resist mask 223 are removed. Thus, a part of the first insulating film 220 and the floating gate electrode 222 provided in the region 214 are left to form the first insulating film 224 and the floating gate electrode 226 (see FIG. 31C). Specifically, in the region 214, the first insulating film 220 and the floating gate electrode 222 provided in a region where a nonvolatile memory element is to be formed later are left. In addition, a part of the surfaces of the regions 212 and 213 and the region 214 of the substrate 200 is exposed.

  Next, a second insulating film 228 is formed so as to cover the regions 212, 213, and 214 and the floating gate electrode 222 of the substrate 200 (see FIG. 32A).

  The second insulating film 228 is formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y) by using a CVD method, a sputtering method, or the like. A single layer or a stacked layer is formed using materials. For example, in the case where the second insulating film 228 is provided as a single layer, a silicon oxynitride film or a silicon nitride oxide film is formed with a thickness of 5 to 50 nm by a CVD method. In the case where the second insulating film 228 is provided in a three-layer structure, a silicon oxynitride film is formed as the first insulating film, a silicon nitride film is formed as the second insulating film, and the third insulating film is formed. A silicon oxynitride film is formed as the insulating film.

  Note that the second insulating film 228 formed over the floating gate electrode 222 in the region 214 of the substrate 200 functions as a control insulating film in a nonvolatile memory element to be completed later, and is formed in a part of the exposed region 214. The second insulating film functions as a gate insulating film in a transistor to be completed later.

  Next, a resist mask 230 is selectively formed so as to cover the second insulating film 228 formed in the region 214 of the substrate 200, and the second insulating film 228 formed in the regions 212 and 213 of the substrate 200 is formed. This is selectively removed (see FIG. 32B).

  Next, third insulating films 232 and 234 are formed over the surfaces of the regions 212 and 213 of the substrate 200, respectively (see FIG. 32C).

  The third insulating films 232 and 234 are formed by using any one of the methods described for forming the first insulating films 216, 218, and 220. For example, the third insulating films 232 and 234 can be formed using silicon oxide films by performing heat treatment to oxidize the surfaces of the regions 212 and 213 provided in the substrate 200. In addition, after a silicon oxide film is formed by a thermal oxidation method, the surface of the silicon oxide film is nitrided by performing nitriding treatment, whereby the silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. You may form with a structure.

  In addition, as described above, the third insulating films 232 and 234 may be formed by plasma treatment. For example, the surface of the regions 212 and 213 provided in the substrate 200 is subjected to oxidation treatment or nitridation treatment by high-density plasma treatment, whereby a silicon oxide (SiOx) film or silicon nitride (SiNx) is formed as the third insulating films 232 and 234. ) It can be formed with a film. Alternatively, the surface of the regions 212 and 213 may be oxidized by high-density plasma treatment, and then nitridation may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 212 and 213, a silicon oxynitride film is formed over the silicon oxide film, and the third insulating films 232 and 234 include the silicon oxide film and the silicon oxynitride film. Is a laminated film. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 212 and 213 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

  Note that when the third insulating films 232 and 234 are formed by a thermal oxidation method or high-density plasma treatment, an oxide film or a surface of the second insulating film 228 formed over the region 214 of the substrate 200 is also formed. An oxynitride film may be formed. The third insulating films 232 and 234 formed in the regions 212 and 213 of the substrate 200 function as a gate insulating film in a transistor that is completed later.

  Next, a conductive film is formed so as to cover the third insulating films 232 and 234 formed above the regions 212 and 213 provided on the substrate 200 and the second insulating film 228 formed above the region 214. (See FIG. 33A). Here, an example is shown in which a conductive film 236 and a conductive film 238 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

  The conductive films 236 and 238 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

  Here, the conductive film 236 is formed using tantalum nitride, and the conductive film 238 is formed using tungsten in a stacked structure. In addition, the conductive film 236 is a single layer or stacked film selected from tantalum nitride, tungsten nitride, molybdenum nitride, or titanium nitride, and the conductive film 238 is selected from tungsten, tantalum, molybdenum, or titanium. A single layer or a laminated film can be used.

  Next, the conductive films 236 and 238 provided by stacking are selectively etched and removed, so that the conductive films 236 and 238 are left in portions above the regions 212, 213, and 214 of the substrate 200. Conductive films 240, 242, 244, and 246 that function as gate electrodes are formed (see FIGS. 33B and 29B). Here, in the substrate 200, the surfaces of the regions 212, 213, and 214 that do not overlap with the conductive films 240, 242, 244, and 246 are exposed. Note that the conductive film 244 functioning as a gate electrode functions as a control gate in a nonvolatile memory element to be completed later.

  Specifically, in the region 212 of the substrate 200, a portion of the third insulating film 232 formed below the conductive film 240 that does not overlap with the conductive film 240 is selectively removed, so that the conductive film 240 and the third conductive film 240 are removed. The insulating film 232 is formed so that the end portions thereof substantially coincide with each other. In addition, in the region 214 of the substrate 200, a portion of the third insulating film 234 formed below the conductive film 242 that does not overlap with the conductive film 242 is selectively removed, so that the conductive film 242 and the third insulating film are removed. It forms so that the edge part of 234 may correspond substantially. Further, in the region 214 of the substrate 200, a portion of the second insulating film 228 formed below the conductive film 244 that does not overlap with the conductive film 244 is selectively removed, so that the conductive film 244 and the second insulating film 228 are removed. Are formed so that their end portions substantially coincide. Further, in the region 214 of the substrate 200, a portion of the second insulating film 228, the floating gate electrode 226, and the first insulating film 224 formed below the conductive film 246 that does not overlap with the conductive film 246 is selectively selected. The conductive film 246, the second insulating film 228, the floating gate electrode 226, and the first insulating film 224 are formed so that the end portions thereof substantially coincide with each other.

  In this case, a portion of the insulating film that does not overlap with the formation of the conductive films 240, 242, 244, and 246 may be removed, or the resist mask remaining after the formation of the conductive films 240, 242, 244, and 246 or the conductive film may be removed. The insulating film or the like that does not overlap may be removed using the films 240, 242, 244, and 246 as masks.

  Next, an impurity element is selectively introduced into the regions 212, 213, and 214 of the substrate 200 (see FIG. 33C). Here, a low-concentration impurity element imparting n-type conductivity is selectively introduced into the regions 213 and 214 using the conductive films 242, 244 and 246 as masks, and a p-type region is imparted to the regions 212 using the conductive film 240 as a mask. A concentration of impurity elements is selectively introduced. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

  Next, an insulating film 254 (also referred to as a sidewall) in contact with the side surfaces of the conductive films 240, 242, 244, and 246 is formed. Specifically, a film containing an inorganic material such as silicon, silicon oxide, or silicon nitride, or a film containing an organic material such as an organic resin is formed in a single layer or stacked layers by a plasma CVD method, a sputtering method, or the like. Form. Then, the insulating film can be selectively etched by anisotropic etching mainly in the vertical direction so as to be in contact with the side surfaces of the conductive films 240 242 244 246. Note that the insulating film 254 is used as a mask for doping when an LDD (Lightly Doped Drain) region is formed. In addition, here, the insulating film 254 is formed so as to be in contact with the insulating film formed below the conductive films 240, 242, 244, and 246 and the side surface of the floating gate electrode.

  Subsequently, an impurity element functioning as a source region or a drain region is formed by introducing an impurity element into the regions 212, 213, and 214 of the substrate 200 using the insulating film 254 and the conductive films 240, 242, 244, and 246 as masks. (See FIGS. 34A, 27A, and 27B). Here, an impurity element imparting high concentration n-type is introduced into the regions 213 and 214 of the substrate 200 using the insulating film 254 and the conductive films 242, 244 and 246 as masks, and the insulating film 254 and the conductive film 240 are formed in the region 212. An impurity element imparting a high concentration of p-type is introduced as a mask.

  As a result, an impurity region 258 that forms a source region or a drain region, a low-concentration impurity region 260 that forms an LDD region, and a channel formation region 256 are formed in the region 212 of the substrate 200. In the region 213 of the substrate 200, an impurity region 264 that forms a source region or a drain region, a low-concentration impurity region 266 that forms an LDD region, and a channel formation region 262 are formed. In the region 214 of the substrate 200, impurity regions 270 that form source or drain regions, low-concentration impurity regions 272 and 276 that form LDD regions, and channel formation regions 268 and 274 are formed.

  Note that in this embodiment, the impurity element is introduced in a state where the regions 212, 213, and 214 of the substrate 200 that do not overlap with the conductive films 240, 242, 244, and 246 are exposed. Accordingly, the channel formation regions 256, 262, 268, and 274 formed in the regions 212, 213, and 214 of the substrate 200 can be formed in a self-alignment manner with the conductive films 240, 242, 244, and 246, respectively.

  Next, an insulating film 277 is formed so as to cover an insulating film, a conductive film, or the like provided over the regions 212, 213, and 214 of the substrate 200, and an opening 278 is formed in the insulating film 277 (FIG. 34B )reference).

  The insulating film 277 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like by CVD or sputtering. Single layer made of an insulating film containing oxygen or nitrogen, a film containing carbon such as DLC (diamond-like carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin Alternatively, a stacked structure can be provided. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Next, a conductive film 280 is formed in the opening 278 by a CVD method, and conductive films 282a to 282d are selectively formed over the insulating film 277 so as to be electrically connected to the conductive film 280 (FIG. 35). 26 (A), (B), and FIG. 29 (C)).

  The conductive films 280 and 282a to 282d are formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt) by CVD or sputtering. ), Copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or these elements as main components An alloy material or a compound material to be formed is a single layer or a laminated layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive films 280 and 282a to 282d include, for example, a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, and a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. Should be adopted. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are suitable as materials for forming the conductive films 280 and 282a to 282d because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, so that the crystalline semiconductor layer is in good condition. Contact can be made. Here, the conductive film 280 can be formed by selectively growing tungsten (W) by a CVD method.

  Through the above steps, a p-type transistor formed in the region 212 of the substrate 200, an n-type transistor formed in the region 213, and an n-type transistor and a nonvolatile memory element formed in the region 214 are provided. A non-volatile memory card can be obtained.

  Note that this embodiment can be freely combined with any of the other embodiments in this specification.

The figure which shows an example of the personal information management system of this invention. The figure which shows an example of the personal information management system of this invention. The figure which shows an example of the non-volatile memory card of this invention. The figure which shows an example of the personal information management system of this invention. The figure which shows an example of the personal information management system of this invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. The figure which shows an example of a plasma apparatus. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention. 4A and 4B illustrate a memory element in a nonvolatile memory card of the present invention.

Explanation of symbols

10 substrate 12 insulating film 14 semiconductor layer 16 insulating film 18 impurity region 20 floating gate electrode 22 insulating film 24 control gate electrode 26 gate 30 semiconductor layer 32 semiconductor layer 34 semiconductor layer 36 semiconductor layer 38 semiconductor layer 40 semiconductor layer 52 memory cell array 54 periphery Circuit 56 Address buffer 58 Control circuit 60 Boost circuit 62 Row decoder 64 Column decoder 66 Sense amplifier 68 Data buffer 70 Data input / output buffer 80 Antenna 82 Dielectric plate 84 Gas supply part 86 Exhaust port 88 Support base 90 Temperature control part 92 Microwave Supply portion 94 Plasma 100 Substrate 101 Substrate 102 Insulating film 104 Semiconductor layer 106 Semiconductor layer 108 Semiconductor layer 110 Semiconductor layer 112 Insulating film 116 Insulating film 120 Charge accumulating layer 121 Charge accumulating layer 122 Resist 124 Resist 1 26 impurity region 128 insulating film 130 resist 132 insulating film 136 conductive film 138 conductive film 140 conductive film 142 conductive film 144 conductive film 148 resist 150 channel formation region 152 impurity region 154 channel formation region 156 impurity region 158 low concentration impurity region 160 channel formation Region 162 Impurity region 164 Low concentration impurity region 166 Resist 168 Channel formation region 16a Silicon oxide layer 16b Silicon oxynitride layer 170 Impurity region 172 Insulating film 174 Conductive film 176 Insulating film 178 Conductive film 18a Source region 18b Drain region 200 Substrate 202 Insulating film 204 Insulating film 206 Resist mask 208 Recess 210 Insulating film 211 Insulating film 212 Region 213 Region 214 Region 215 P well 216 Insulating film 220 Insulating film 222 Floating gate electrode 2 23 resist mask 224 insulating film 226 floating gate electrode 228 insulating film 22a silicon nitride layer 22b silicon oxide layer 230 resist mask 232 insulating film 234 insulating film 236 conductive film 238 conductive film 240 conductive film 242 conductive film 244 conductive film 246 conductive film 24a metal Nitride layer 24b Metal layer 254 Insulating film 256 Channel forming region 258 Impurity region 260 Low concentration impurity region 262 Channel forming region 264 Impurity region 266 Low concentration impurity region 268 Channel forming region 270 Impurity region 272 Low concentration impurity region 277 Insulating film 278 Opening Unit 280 conductive film 500 personal information recording medium 500 non-volatile memory card 501 communication control means 502 encryption means 503 information processing means 504 storage circuit 510 terminal 511 communication control means 512 control circuit 513 Table Display unit 514 Input unit 520 Server 521 Communication control unit 522 Decoding unit 523 Comparison reference unit 524 Information processing program 525 Password data recording unit 526 Comparison reference unit 527 Deposit information recording unit 701 Non-volatile memory card 702 Resonance circuit 703 Power supply circuit 704 Clock Generation circuit 705 Demodulation circuit 706 Information processing circuit 707 Memory circuit 708 A / D conversion circuit 709 Modulation circuit 710 Antenna 711 Communication line 712 Terminal 713 CPU
714 Server 715 Reader / Writer 716 RF circuit 200a Semiconductor layer 200b Semiconductor layer 202a NAND cell 202b NAND cell 282a Conductive film

Claims (7)

A personal information recording medium, a terminal, and a server;
The personal information recording medium is
First communication control means for transmitting and receiving information to and from the terminal;
An encryption means for encrypting the received information;
A nonvolatile memory for storing the encrypted information,
The terminal
Second communication control means for transmitting and receiving information to and from the personal information recording medium and the server;
A display for displaying the received information;
Input means,
The server
Third communication control means for transmitting and receiving information to and from the terminal;
Decryption means for decrypting the encrypted information;
A password data recording unit;
A personal information management system comprising means for comparing and referring to the decrypted information and the information stored in the personal identification data recording unit. In claim 1,
The first communication control means provided in the personal information recording medium and the second communication control means provided in the terminal have an antenna,
A personal information management system for performing transmission / reception of information between the first communication control means provided in the personal information recording medium and the second communication control means provided in the terminal by wireless communication. In claim 1 or claim 2,
A personal information management system for performing transmission / reception of information between a second communication control means provided in the terminal and a third communication control means provided in the server by wired communication. In any one of Claims 1 thru | or 3,
The personal information management system, wherein the personal information recording medium transmits encrypted information to the terminal and receives plain text from the terminal. In any one of Claims 1 thru | or 3,
Information stored encrypted in the personal information management system is not stored in the server. Communication control means for transmitting / receiving information to / from a reader / writer;
An encryption means for encrypting the received information;
Information processing means for processing the encrypted information;
A nonvolatile memory for storing the encrypted information,
The non-volatile memory card, wherein the communication control means includes an antenna, and transmits / receives information to / from the reader / writer by wireless communication. In claim 6,
The non-volatile memory card, wherein the communication control means transmits encrypted information to the reader / writer.

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