JP2008026105A - Connection-use board and method for manufacturing semiconductor device - Google Patents

Connection-use board and method for manufacturing semiconductor device Download PDF

Info

Publication number
JP2008026105A
JP2008026105A JP2006197934A JP2006197934A JP2008026105A JP 2008026105 A JP2008026105 A JP 2008026105A JP 2006197934 A JP2006197934 A JP 2006197934A JP 2006197934 A JP2006197934 A JP 2006197934A JP 2008026105 A JP2008026105 A JP 2008026105A
Authority
JP
Japan
Prior art keywords
connection
terminals
semiconductor device
terminal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006197934A
Other languages
Japanese (ja)
Inventor
Takayuki Seki
隆行 関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2006197934A priority Critical patent/JP2008026105A/en
Publication of JP2008026105A publication Critical patent/JP2008026105A/en
Withdrawn legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a connection-use board capable of inspecting two or more kinds of semiconductor devices by using the same probe card, and capable of preventing a probe pin from hardly connecting with an external connection terminal even in the case a plurality of external connection terminals are spaced widely from another. <P>SOLUTION: The connection-use board 20 which is a connection-use board for connecting a semiconductor device to a probe card, comprises: a first plurality of terminals 22 which are formed on one surface and disposed at positions respectively facing a plurality of probe pins of the probe card; a second plurality of terminals 21 which are formed on the other surface and disposed at positions respectively facing a plurality of external connection terminals of the semiconductor device; and a plurality of interconnections 23a, 23b for respectively connecting the first plurality of terminals 22 to the second plurality of terminals 21 differing from another. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置とプローブカードを接続する接続用基板及び半導体装置の製造方法に関する。特に本発明は、複数種類の半導体装置を同一のプローブカードで検査することができる接続用基板及び半導体装置の製造方法に関する。また本発明は、複数の外部接続端子の相互間隔が大きくてもプローブピンと外部接続端子が電気的に接続できなくなることを抑制できる接続用基板及び半導体装置の製造方法に関する。   The present invention relates to a connection substrate for connecting a semiconductor device and a probe card, and a method for manufacturing the semiconductor device. In particular, the present invention relates to a connection substrate capable of inspecting a plurality of types of semiconductor devices with the same probe card and a method for manufacturing the semiconductor device. The present invention also relates to a connection substrate and a method for manufacturing a semiconductor device that can prevent a probe pin and an external connection terminal from being unable to be electrically connected even if the interval between a plurality of external connection terminals is large.

図６は、半導体装置を検査する従来の方法を説明する為の断面概略図である。この半導体装置は、半導体チップ１０１をＣＯＦ（Ｃｈｉｐ Ｏｎ Ｆｉｌｍ）又はＴＣＰ（Ｔａｐｅ Ｃａｒｒｉｅｒ Ｐａｃｋａｇｅ）構造により配線基板１１０に実装したものである。そして、配線基板１１０が有する複数の外部接続端子１１１それぞれに、プローブカード１５０が有するプローブピン１５１を接続することにより、半導体装置を検査する（例えば特許文献１参照）。
特開平０６−１９６５３６号公報（図１） FIG. 6 is a schematic cross-sectional view for explaining a conventional method for inspecting a semiconductor device. In this semiconductor device, a semiconductor chip 101 is mounted on a wiring substrate 110 with a COF (Chip On Film) or TCP (Tape Carrier Package) structure. Then, the semiconductor device is inspected by connecting the probe pins 151 included in the probe card 150 to each of the plurality of external connection terminals 111 included in the wiring board 110 (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 06-196536 (FIG. 1)

半導体装置の種類ごとに外部接続端子の配列は異なる。このため、従来は半導体装置ごとにプローブカードを設計する必要があった。   The arrangement of external connection terminals varies depending on the type of semiconductor device. For this reason, conventionally, it has been necessary to design a probe card for each semiconductor device.

また、半導体装置によっては複数の外部接続端子の相互間が大きい場合がある。このような半導体装置において配線基板が熱膨張した場合、外部接続端子の位置ずれが大きくなり、プローブピンと外部接続端子が接続できない場合が出てくる。   In addition, depending on the semiconductor device, the distance between the plurality of external connection terminals may be large. In such a semiconductor device, when the wiring board is thermally expanded, the positional displacement of the external connection terminal becomes large, and the probe pin and the external connection terminal may not be connected.

本発明は上記のような事情を考慮してなされたものであり、その目的は、複数種類の半導体装置を同一のプローブカードで検査することができる接続用基板及び半導体装置の製造方法を提供することにある。また本発明の他の目的は、複数の外部接続端子の相互間隔が大きくてもプローブピンと外部接続端子が電気的に接続できなくなることを抑制できる接続用基板及び半導体装置の製造方法を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a connection substrate and a semiconductor device manufacturing method capable of inspecting a plurality of types of semiconductor devices with the same probe card. There is. Another object of the present invention is to provide a connection substrate and a method for manufacturing a semiconductor device that can prevent the probe pins and the external connection terminals from being unable to be electrically connected even if the interval between the plurality of external connection terminals is large. It is in.

上記課題を解決するため、本発明に係る接続用基板は、半導体装置とプローブカードを接続する接続用基板であって、
一面に形成され、前記プローブカードが有する複数のプローブピンそれぞれに対向する位置に配置された複数の第１の端子と、
他面に形成され、前記半導体装置が有する複数の外部接続端子それぞれに対向する位置に配置された複数の第２の端子と、
前記複数の第１の端子それぞれを互いに異なる前記第２の端子に接続する複数の接続用配線とを具備する。 In order to solve the above problems, a connection substrate according to the present invention is a connection substrate for connecting a semiconductor device and a probe card,
A plurality of first terminals formed on one surface and disposed at positions facing each of the plurality of probe pins of the probe card;
A plurality of second terminals formed on the other surface and arranged at positions facing each of the plurality of external connection terminals of the semiconductor device;
And a plurality of connection wirings for connecting the plurality of first terminals to the second terminals different from each other.

この接続用基板によれば、前記プローブピンの配置間隔と前記外部接続端子の配置間隔が異なっている場合においても、前記接続用基板を介することにより、前記プローブピンと前記外部接続端子を電気的に接続することができる。このため、半導体装置の種類ごとに前記接続用基板を形成することにより、同一のプローブカードで複数種類の半導体装置の検査を行うことができる。   According to this connection substrate, even when the arrangement interval of the probe pins and the arrangement interval of the external connection terminals are different, the probe pins and the external connection terminals are electrically connected via the connection substrate. Can be connected. Therefore, by forming the connection substrate for each type of semiconductor device, a plurality of types of semiconductor devices can be inspected with the same probe card.

また、前記外部接続端子の配置間隔が広い場合、前記半導体装置が熱膨張しても、前記接続用基板も同様に熱膨張するため、前記第２の端子と前記外部接続端子を接続することができる。そして前記プローブピンの配置間隔を前記外部接続端子の配置間隔より狭すると、前記接続用基板の熱膨張によって生じる前記第２の端子の位置ずれの大きさは、前記半導体装置の熱膨張によって生じる前記外部接続端子の位置ずれより小さい。従って、従来と比較して、前記プローブピンと前記外部接続端子が電気的に接続できなくなることを抑制できる。   In addition, when the arrangement interval of the external connection terminals is wide, even if the semiconductor device is thermally expanded, the connection substrate is also thermally expanded, so that the second terminal and the external connection terminal can be connected. it can. When the arrangement interval of the probe pins is narrower than the arrangement interval of the external connection terminals, the displacement of the second terminal caused by the thermal expansion of the connection substrate is caused by the thermal expansion of the semiconductor device. Less than misalignment of external connection terminals. Therefore, it is possible to prevent the probe pin and the external connection terminal from being electrically connected as compared with the conventional case.

前記複数の第１の端子の相互間隔は、前記複数の第２の端子の相互間隔より小さくてもよい。   An interval between the plurality of first terminals may be smaller than an interval between the plurality of second terminals.

前記一面から前記他面に貫通する複数の貫通孔を更に具備し、前記複数の接続用配線は、それぞれ前記貫通孔を介して前記第１の端子と前記第２の端子を接続していてもよい。また、前記複数の接続用配線は、それぞれ前記接続用基板の側面を介して前記第１の端子と前記第２の端子を接続していてもよい。   A plurality of through holes penetrating from the one surface to the other surface, wherein the plurality of connection wirings connect the first terminal and the second terminal via the through holes, respectively. Good. Further, each of the plurality of connection wirings may connect the first terminal and the second terminal via a side surface of the connection substrate.

また、前記接続用基板の内部に設けられた複数の中間配線と、前記複数の中間配線それぞれと前記一面を接続する複数の第１の接続孔と、前記複数の中間配線それぞれと前記他面を接続する複数の第２の接続孔とを具備し、前記複数の接続用配線それぞれは、前記中間配線と、前記第１の接続孔を介して前記第１の端子を前記中間配線に接続する第１の配線と、前記第２の接続孔を介して前記第２の端子を前記中間配線に接続する第２の配線とにより形成されていてもよい。   In addition, a plurality of intermediate wirings provided inside the connection substrate, a plurality of first connection holes that connect the one surface with each of the plurality of intermediate wires, each of the plurality of intermediate wires, and the other surface A plurality of second connection holes to be connected, wherein each of the plurality of connection wirings connects the intermediate terminal and the first terminal to the intermediate wiring via the first connection hole. 1 wiring and the 2nd wiring which connects the said 2nd terminal to the said intermediate wiring through the said 2nd connection hole may be formed.

本発明に係る半導体装置の製造方法は、半導体基板に半導体装置を形成する工程と、
前記半導体装置の検査を行う工程と、
を具備し、
前記半導体装置の検査を行う工程において、
プローブカードが有する複数のプローブピンそれぞれに対向する位置に配置された複数の第１の端子を一面に有し、前記半導体装置が有する複数の外部接続端子それぞれに対向する位置に配置された複数の第２の端子を他面に有し、かつ前記複数の第１の端子それぞれを互いに異なる前記第２の端子に接続する複数の接続用配線を具備する接続用基板を準備する工程と、
前記半導体装置に前記接続用基板の一面を取り付けることにより、前記複数の外部接続端子を前記複数の第２の端子に接続する工程と、
前記複数のプローブピンを前記接続用基板の前記複数の第１の端子に接続することにより、前記接続用基板を介して前記半導体装置を検査する工程とを具備する。 A method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor device on a semiconductor substrate,
A step of inspecting the semiconductor device;
Comprising
In the step of inspecting the semiconductor device,
A plurality of first terminals arranged at positions facing each of a plurality of probe pins included in the probe card are provided on one surface, and a plurality of terminals disposed at positions facing each of the plurality of external connection terminals included in the semiconductor device. Providing a connection board having a plurality of connection wirings having a second terminal on the other surface and connecting each of the plurality of first terminals to the second terminal different from each other;
Attaching the plurality of external connection terminals to the plurality of second terminals by attaching one surface of the connection substrate to the semiconductor device;
Connecting the plurality of probe pins to the plurality of first terminals of the connection substrate, thereby inspecting the semiconductor device through the connection substrate.

前記半導体装置は、半導体チップと、前記半導体チップが実装され、前記複数の外部接続端子を有する配線基板とを具備してもよい。   The semiconductor device may include a semiconductor chip and a wiring board on which the semiconductor chip is mounted and having the plurality of external connection terminals.

以下、図面を参照して本発明の実施形態に係る半導体装置の製造方法について説明する。本実施形態においてシリコンウェハには、所定の製造工程を経ることにより、複数の半導体装置が形成される。そしてシリコンウェハがダイシングされることにより半導体チップが切り出される。そして、半導体チップを例えばＣＯＦ又はＴＣＰにより配線基板に実装することにより、半導体装置が製造される。そして、半導体装置はプローブ検査装置によって検査される。   A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, a plurality of semiconductor devices are formed on a silicon wafer through a predetermined manufacturing process. Then, the semiconductor chip is cut out by dicing the silicon wafer. And a semiconductor device is manufactured by mounting a semiconductor chip on a wiring board by COF or TCP, for example. Then, the semiconductor device is inspected by a probe inspection device.

図１は、半導体装置をプローブ検査装置によって検査するときの断面概略図である。図２（Ａ）は半導体装置の平面図であり、図２（Ｂ）は半導体装置に接続用基板２０を実装した状態を説明する為の平面図である。半導体装置の半導体チップ１は配線基板１０上に実装され、配線基板１０に設けられた複数の外部接続端子１１に、図示しない配線を介して電気的に接続されている。複数の外部接続端子１１は、それぞれ接続用基板２０を介してプローブカード５０のプローブピン５１に接続されている。本実施例においてプローブピン５１の配置間隔は外部接続端子１１の配置間隔より狭いが、接続用基板２０を介することにより、プローブピン５１と外部接続端子１１は互いに電気的に接続することができる。   FIG. 1 is a schematic cross-sectional view when a semiconductor device is inspected by a probe inspection apparatus. 2A is a plan view of the semiconductor device, and FIG. 2B is a plan view for explaining a state where the connection substrate 20 is mounted on the semiconductor device. A semiconductor chip 1 of a semiconductor device is mounted on a wiring board 10 and is electrically connected to a plurality of external connection terminals 11 provided on the wiring board 10 via wirings (not shown). The plurality of external connection terminals 11 are respectively connected to the probe pins 51 of the probe card 50 via the connection substrate 20. In this embodiment, the arrangement interval of the probe pins 51 is narrower than the arrangement interval of the external connection terminals 11, but the probe pins 51 and the external connection terminals 11 can be electrically connected to each other through the connection substrate 20.

図３（Ａ）は接続用基板２０の上面図であり、図３（Ｂ）は接続用基板２０の下面図である。接続用基板２０は長方形の両面基板であり、上面には複数の第１の端子２２が、下面には複数の第２の端子２１が、それぞれ同一の長辺に沿う位置に形成されている。複数の第１の端子２２は、それぞれ互いに異なるプローブピン５１に対向するように配置されており、その配置間隔は、プローブピン５１の配置間隔に等しい。複数の第２の端子２１は、それぞれ互いに異なる外部接続端子１１に対向するように配置されており、その配置間隔は、外部接続端子１１の配置間隔に等しい。第１の端子２２の個数は第２の端子２１の個数に等しく、第１の端子２２の配置間隔は第２の端子２１の配置間隔より大きい。   FIG. 3A is a top view of the connection substrate 20, and FIG. 3B is a bottom view of the connection substrate 20. The connection substrate 20 is a rectangular double-sided substrate, and a plurality of first terminals 22 are formed on the upper surface, and a plurality of second terminals 21 are formed on the lower surface along the same long side. The plurality of first terminals 22 are arranged so as to face different probe pins 51, and the arrangement interval is equal to the arrangement interval of the probe pins 51. The plurality of second terminals 21 are arranged so as to face different external connection terminals 11, and the arrangement interval is equal to the arrangement interval of the external connection terminals 11. The number of the first terminals 22 is equal to the number of the second terminals 21, and the arrangement interval of the first terminals 22 is larger than the arrangement interval of the second terminals 21.

接続用基板２０には接続用の貫通孔２４が、第１の端子２２が沿っている長辺とは異なる長辺に沿って複数形成されている。貫通孔２４の数は第１の端子２２と同数である。接続用基板２０は、上面に複数の配線２３ａが設けられており、下面に複数の配線２３ｂが設けられている。配線２３ａはそれぞれ互いに異なる第１の端子２２に接続しており、配線２３ｂはそれぞれ互いに異なる第２の端子２１に接続している。そして、配線２３ａ，２３ｂは貫通孔２４を介して互いに接続している。このように、第１の端子２２と第２の端子２１は、配線２３ａ，２３ｂを介して互いに接続している。   A plurality of through holes 24 for connection are formed in the connection substrate 20 along long sides different from the long sides along which the first terminals 22 are along. The number of through holes 24 is the same as that of the first terminals 22. The connection substrate 20 is provided with a plurality of wirings 23a on the upper surface and a plurality of wirings 23b on the lower surface. The wirings 23a are connected to different first terminals 22, and the wirings 23b are connected to different second terminals 21, respectively. The wirings 23 a and 23 b are connected to each other through the through hole 24. Thus, the first terminal 22 and the second terminal 21 are connected to each other via the wirings 23a and 23b.

接続用基板２０を用いて半導体装置をプローブ検査するとき、接続用基板２０の下面を半導体装置の外部接続端子１１上に配置し、複数の外部接続端子１１それぞれを互いに異なる第２の端子２１に接続させる。そして、プローブカード５０が有する複数のプローブピン５１を、接続用基板２０の複数の第１の端子２２に接続する。これにより、プローブピン５１と外部接続端子１１は、第１の端子２２、配線２３ａ，２３ｂ、及び第２の端子２１を介して互いに電気的に接続する。次いで、半導体装置のプローブ検査を行う。その後、接続用基板２０を半導体装置から取り除き、取り除いた接続用基板２０を他の半導体装置に取り付ける。   When the semiconductor substrate is probe-inspected using the connection substrate 20, the lower surface of the connection substrate 20 is disposed on the external connection terminal 11 of the semiconductor device, and each of the plurality of external connection terminals 11 is a second terminal 21 different from each other. Connect. Then, the plurality of probe pins 51 included in the probe card 50 are connected to the plurality of first terminals 22 of the connection substrate 20. Thereby, the probe pin 51 and the external connection terminal 11 are electrically connected to each other via the first terminal 22, the wirings 23 a and 23 b, and the second terminal 21. Next, a probe inspection of the semiconductor device is performed. Thereafter, the connection substrate 20 is removed from the semiconductor device, and the removed connection substrate 20 is attached to another semiconductor device.

以上、本実施形態によれば、プローブピン５１の配置間隔は外部接続端子１１の配置間隔より狭いが、接続用基板２０を介することにより、プローブピン５１と外部接続端子１１は互いに電気的に接続することができる。このため、半導体装置の種類ごとに接続用基板２０を形成することにより、同一のプローブカード５０で複数種類の半導体装置の検査を行うことができる。   As described above, according to the present embodiment, the arrangement interval of the probe pins 51 is narrower than the arrangement interval of the external connection terminals 11, but the probe pins 51 and the external connection terminals 11 are electrically connected to each other through the connection substrate 20. can do. For this reason, a plurality of types of semiconductor devices can be inspected with the same probe card 50 by forming the connection substrate 20 for each type of semiconductor device.

また、配線基板１０が熱膨張した場合においても、接続用基板２０も同様に熱膨張するため、第２の端子２１と配線基板１０の外部接続端子１１を接続することができる。この場合において、第１の端子２２の配置間隔は外部接続端子１１の配置間隔より狭く、プローブピン５１の配置間隔に等しいため、配線基板１０の熱膨張によって生じる第１の端子２２の位置ずれの大きさは、配線基板１０の熱膨張によって生じる外部接続端子１１の位置ずれより小さい。従って、従来と比較して、プローブピン５１と外部接続端子１１が電気的に接続できなくなることを抑制できる。   Further, even when the wiring substrate 10 is thermally expanded, the connection substrate 20 is also thermally expanded, so that the second terminal 21 and the external connection terminal 11 of the wiring substrate 10 can be connected. In this case, since the arrangement interval of the first terminals 22 is narrower than the arrangement interval of the external connection terminals 11 and is equal to the arrangement interval of the probe pins 51, the displacement of the first terminals 22 caused by the thermal expansion of the wiring board 10 is eliminated. The size is smaller than the positional deviation of the external connection terminal 11 caused by the thermal expansion of the wiring board 10. Therefore, it is possible to suppress the probe pin 51 and the external connection terminal 11 from being unable to be electrically connected as compared with the conventional case.

図４（Ａ）は、第２の実施形態に係る接続用基板２０の上面図である。図４（Ｂ）及び（Ｃ）は、それぞれ本実施形態に係る接続用基板２０の下面図及び側面図である。本実施形態煮において、接続用基板２０は貫通孔２４が設けられていない点、及び接続用基板２０の側面に設けられた配線２３ｃによって配線２３ａ，２３ｂが互いに接続されている点を除いて、第１の実施形態と同様である。また、接続用基板２０を用いて半導体装置を検査する方法も、第１の実施形態と同様である。
本実施形態によっても第１の実施形態と同様の効果を得ることができる。 FIG. 4A is a top view of the connection substrate 20 according to the second embodiment. 4B and 4C are a bottom view and a side view of the connection substrate 20 according to the present embodiment, respectively. In this embodiment, the connecting substrate 20 is not provided with the through hole 24, and the wiring 23a and 23b are connected to each other by the wiring 23c provided on the side surface of the connecting substrate 20, This is the same as in the first embodiment. The method for inspecting the semiconductor device using the connection substrate 20 is the same as that in the first embodiment.
According to this embodiment, the same effect as that of the first embodiment can be obtained.

図５（Ａ）及び（Ｂ）は、第３の実施形態に係る接続用基板２０の上面図及び下面図である。図５（Ｃ）は図５（Ａ）のＡ−Ａ断面図であり、図５（Ｄ）は図５（Ｂ）のＢ−Ｂ断面図である。本実施形態において、接続用基板２０は内部に配線層２３ｄを有している点、貫通孔２４の代わりに接続孔２５ａ，２５ｂが設けられている点、及び配線２３ａ，２３ｂが接続孔２５ａ、配線層２３ｄの配線、及び接続孔２５ｂを介して互いに接続されている点を除いて、第１の実施形態と同様である。すなわち配線２３ａと配線層２３ｄの配線は、接続孔２５ａを介して接続しており、配線２３ｂと配線層２３ｄの配線は、接続孔２５ｂを介して接続している。また、接続用基板２０を用いて半導体装置を検査する方法も、第１の実施形態と同様である。
本実施形態によっても第１の実施形態と同様の効果を得ることができる。 FIGS. 5A and 5B are a top view and a bottom view of the connection substrate 20 according to the third embodiment. 5C is a cross-sectional view taken along line AA in FIG. 5A, and FIG. 5D is a cross-sectional view taken along line BB in FIG. 5B. In the present embodiment, the connection substrate 20 has a wiring layer 23d therein, connection holes 25a and 25b are provided instead of the through holes 24, and the wirings 23a and 23b are connection holes 25a, Except for the point that they are connected to each other via the wiring of the wiring layer 23d and the connection hole 25b, this is the same as in the first embodiment. That is, the wiring 23a and the wiring layer 23d are connected via the connection hole 25a, and the wiring 23b and the wiring layer 23d are connected via the connection hole 25b. The method for inspecting the semiconductor device using the connection substrate 20 is the same as that in the first embodiment.
According to this embodiment, the same effect as that of the first embodiment can be obtained.

尚、本発明は上述した実施形態に限定されるものではなく、本発明の主旨を逸脱しない範囲内で種々変更して実施することが可能である。例えば第１〜第３の実施形態において、プローブカード５０にプローブピン５１が一列ではなく複数列に配置されている場合、第１の端子２２も接続用基板２０の長辺に沿って複数列に配置される。また、第３の実施形態において接続用基板２０は更に多くの配線層を内部に有していてもよい。   Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the first to third embodiments, when the probe pins 51 are arranged in a plurality of rows instead of one row in the probe card 50, the first terminals 22 are also arranged in a plurality of rows along the long side of the connection substrate 20. Be placed. In the third embodiment, the connection substrate 20 may have more wiring layers inside.

半導体装置をプローブ検査装置によって検査するときの断面概略図。Sectional schematic when test | inspecting a semiconductor device with a probe test | inspection apparatus. （Ａ）は半導体装置の平面図、（Ｂ）は半導体装置の接続用基板を取り付けた状態を示す平面図。FIG. 4A is a plan view of a semiconductor device, and FIG. 4B is a plan view illustrating a state where a connection substrate of the semiconductor device is attached. （Ａ）、（Ｂ）は、それぞれ接続用基板２０の上面図、下面図。FIGS. 4A and 4B are a top view and a bottom view of the connection substrate 20, respectively. （Ａ）、（Ｂ）、（Ｃ）は、それぞれ第２の実施形態に係る接続用基板２０の上面図、下面図、側面図。(A), (B), (C) is a top view, a bottom view, and a side view of the connection substrate 20 according to the second embodiment, respectively. （Ａ）、（Ｂ）は、それぞれ接続用基板２０の上面図、下面図であり、（Ｃ）は（Ａ）のＡ−Ａ断面図、（Ｄ）は（Ｂ）のＢ−Ｂ断面図。(A) and (B) are a top view and a bottom view, respectively, of the connection substrate 20, (C) is a sectional view taken along line AA in (A), and (D) is a sectional view taken along line BB in (B). . 半導体装置を検査する従来の方法を説明する為の断面概略図。Sectional schematic for demonstrating the conventional method of test | inspecting a semiconductor device.

符号の説明Explanation of symbols

１，１０１…半導体チップ、１０，１１０…配線基板、１１，１１１…外部接続端子、２０…接続用基板、２１…第２の端子、２２…第1の端子、２１ａ〜２３ｃ…配線、２３ｄ…配線層、２４…貫通孔、２５ａ，２５ｂ…接続孔、５０，１５０…プローブカード、５１，１５１…プローブピン
DESCRIPTION OF SYMBOLS 1,101 ... Semiconductor chip, 10, 110 ... Wiring board, 11, 111 ... External connection terminal, 20 ... Connection board, 21 ... Second terminal, 22 ... First terminal, 21a-23c ... Wiring, 23d ... Wiring layer, 24 ... through hole, 25a, 25b ... connection hole, 50,150 ... probe card, 51,151 ... probe pin

Claims (7)

半導体装置とプローブカードを接続する接続用基板であって、
一面に形成され、前記プローブカードが有する複数のプローブピンそれぞれに対向する位置に配置された複数の第１の端子と、
他面に形成され、前記半導体装置が有する複数の外部接続端子それぞれに対向する位置に配置された複数の第２の端子と、
前記複数の第１の端子それぞれを互いに異なる前記第２の端子に接続する複数の接続用配線と、
を具備する接続用基板。 A connection substrate for connecting a semiconductor device and a probe card,
A plurality of first terminals formed on one surface and disposed at positions facing each of the plurality of probe pins of the probe card;
A plurality of second terminals formed on the other surface and arranged at positions facing each of the plurality of external connection terminals of the semiconductor device;
A plurality of connection wires for connecting the plurality of first terminals to the second terminals different from each other;
A connection board comprising: 前記複数の第１の端子の相互間隔は、前記複数の第２の端子の相互間隔より小さい請求項１に記載の接続用基板。   2. The connection substrate according to claim 1, wherein an interval between the plurality of first terminals is smaller than an interval between the plurality of second terminals. 前記一面から前記他面に貫通する複数の貫通孔を更に具備し、
前記複数の接続用配線は、それぞれ前記貫通孔を介して前記第１の端子と前記第２の端子を接続している請求項１又は２に記載の接続用基板。 A plurality of through holes penetrating from the one surface to the other surface;
3. The connection board according to claim 1, wherein each of the plurality of connection wirings connects the first terminal and the second terminal via the through hole. 前記複数の接続用配線は、それぞれ前記接続用基板の側面を介して前記第１の端子と前記第２の端子を接続している請求項１又は２に記載の接続用基板。   3. The connection substrate according to claim 1, wherein the plurality of connection wirings connect the first terminal and the second terminal via side surfaces of the connection substrate, respectively. 前記接続用基板の内部に設けられた複数の中間配線と、
前記複数の中間配線それぞれと前記一面を接続する複数の第１の接続孔と、
前記複数の中間配線それぞれと前記他面を接続する複数の第２の接続孔と、
を具備し、
前記複数の接続用配線それぞれは、
前記中間配線と、
前記第１の接続孔を介して前記第１の端子を前記中間配線に接続する第１の配線と、
前記第２の接続孔を介して前記第２の端子を前記中間配線に接続する第２の配線と、
により形成されている請求項１又は２に記載の接続用基板。 A plurality of intermediate wires provided inside the connection board;
A plurality of first connection holes connecting each of the plurality of intermediate wires and the one surface;
A plurality of second connection holes connecting each of the plurality of intermediate wirings and the other surface;
Comprising
Each of the plurality of connection wirings is
The intermediate wiring;
A first wiring for connecting the first terminal to the intermediate wiring through the first connection hole;
A second wiring connecting the second terminal to the intermediate wiring via the second connection hole;
The connection substrate according to claim 1, wherein the connection substrate is formed by the following. 半導体装置を形成する工程と、
前記半導体装置の検査を行う工程と、
を具備し、
前記半導体装置の検査を行う工程において、
プローブカードが有する複数のプローブピンそれぞれに対向する位置に配置された複数の第１の端子を一面に有し、前記半導体装置が有する複数の外部接続端子それぞれに対向する位置に配置された複数の第２の端子を他面に有し、かつ前記複数の第１の端子それぞれを互いに異なる前記第２の端子に接続する複数の接続用配線を具備する接続用基板を準備する工程と、
前記半導体装置に前記接続用基板の一面を取り付けることにより、前記複数の外部接続端子を前記複数の第２の端子に接続する工程と、
前記複数のプローブピンを前記接続用基板の前記複数の第１の端子に接続することにより、前記接続用基板を介して前記半導体装置を検査する工程と、
を具備する半導体装置の製造方法。 Forming a semiconductor device;
A step of inspecting the semiconductor device;
Comprising
In the step of inspecting the semiconductor device,
A plurality of first terminals arranged at positions facing each of a plurality of probe pins included in the probe card are provided on one surface, and a plurality of terminals disposed at positions facing each of the plurality of external connection terminals included in the semiconductor device. Providing a connection board having a plurality of connection wirings having a second terminal on the other surface and connecting each of the plurality of first terminals to the second terminal different from each other;
Attaching the plurality of external connection terminals to the plurality of second terminals by attaching one surface of the connection substrate to the semiconductor device;
Inspecting the semiconductor device through the connection substrate by connecting the plurality of probe pins to the plurality of first terminals of the connection substrate;
A method for manufacturing a semiconductor device comprising: 前記半導体装置は、
半導体チップと、
前記半導体チップが実装され、前記複数の外部接続端子を有する配線基板と、
を具備する請求項６に記載の半導体装置の製造方法。 The semiconductor device includes:
A semiconductor chip;
A wiring board on which the semiconductor chip is mounted and having the plurality of external connection terminals;
A method for manufacturing a semiconductor device according to claim 6.
JP2006197934A 2006-07-20 2006-07-20 Connection-use board and method for manufacturing semiconductor device Withdrawn JP2008026105A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006197934A JP2008026105A (en) 2006-07-20 2006-07-20 Connection-use board and method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006197934A JP2008026105A (en) 2006-07-20 2006-07-20 Connection-use board and method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2008026105A true JP2008026105A (en) 2008-02-07

Family

ID=39116889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006197934A Withdrawn JP2008026105A (en) 2006-07-20 2006-07-20 Connection-use board and method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2008026105A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011064669A (en) * 2009-09-17 2011-03-31 Samsung Electro-Mechanics Co Ltd Space converter for probe card, and method for restoration of space converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011064669A (en) * 2009-09-17 2011-03-31 Samsung Electro-Mechanics Co Ltd Space converter for probe card, and method for restoration of space converter

Similar Documents

Publication Publication Date Title
US7663232B2 (en) Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems
US9455193B2 (en) Integrated circuit interposer and method of manufacturing the same
JP2005322921A (en) Flip-chip semiconductor package for testing bumps and method of fabricating same
JP2005191436A (en) Semiconductor device and manufacturing method for the same
US20170372992A1 (en) Film product, film packages and package modules using the same
US10679912B2 (en) Wafer scale testing and initialization of small die chips
JP2002313864A (en) Semiconductor device
KR20190071488A (en) Semiconductor package and semiconductor module including the same
TW202042362A (en) Device comprising first solder interconnects aligned in a first direction and second solder interconnects aligned in a second direction
JPH1187003A (en) Mounting inspecting system
US6686224B2 (en) Chip manufacturing method for cutting test pads from integrated circuits by sectioning circuit chips from circuit substrate
JP2005251784A (en) Semiconductor module and its manufacturing method
US9365415B2 (en) Compact electronic package with MEMS IC and related methods
JP2008026105A (en) Connection-use board and method for manufacturing semiconductor device
US7595552B2 (en) Stacked semiconductor package in which semiconductor packages are connected using a connector
US20080277661A1 (en) Semiconductor device and method of manufacturing the same
JP2007134427A (en) Module package and its manufacturing method
JP2014120612A (en) Semiconductor device, and semiconductor module using the same
JP2012028519A (en) Semiconductor package
KR101320973B1 (en) Integrated circuit device package and method for manufacturing the same
JP2002237669A (en) Method of forming recognition mark to substrate for kgd
JP2008159815A (en) Manufacturing method for semiconductor device
KR101106607B1 (en) Test device for semiconductor device
US20110074042A1 (en) Electronic device
JP2004260033A (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20091006