JP2008014811A - Data processor and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute an arithmetic process including squaring calculation at a low cost. <P>SOLUTION: A data processor comprises a RAM 22 for storing sampling data D; a write pointer for writing the sampling data D to a write position in the RAM 22; and a readout pointer for specifying the readout position for reading out the sampling data D from a readout position in the RAM 22, and further comprising a memory controller 23 for controlling writing and reading out the sampling data D by FIFO, and a product-sum computing unit 11a for executing the arithmetic process by using the readout sampling data D. The memory controller 23 makes the readout pointer move so that the writing position of the sampling data D, which has been written in the RAM 22 after the read out sampling data D, is identifiable, when one of the sampling data D is read out twice from the RAM 22 by the product-sum computing unit 11a (CPU 11). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data processing apparatus and a data processing method for writing measurement data into a memory and executing predetermined arithmetic processing using the measurement data read from the memory.

  As a data processing apparatus for processing measurement data according to this type of data processing method, recording of measurement data (digital data) sampled at a predetermined cycle with respect to an input signal (input data), and a signal waveform based on the recorded measurement data Japanese Patent Application Laid-Open No. 2002-250745 discloses a two-channel waveform recording apparatus (hereinafter also referred to as “waveform recording apparatus”) configured to be capable of display. This waveform recording apparatus includes an A / D converter that performs A / D conversion (sampling) on an input signal to generate measurement data, a memory that stores the generated measurement data, writing measurement data to the memory, and A memory controller that manages reading of measurement data from the memory; a display controller that displays a signal waveform based on the measurement data on a display; and a CPU that reads the measurement data to be displayed on the signal waveform from the memory and outputs the data to the display controller; And a trigger detector for detecting a trigger for specifying timing for starting measurement data recording and signal waveform display.

In this waveform recording apparatus, at the start of measurement, an A / D converter first A / D converts an input signal to generate measurement data. The memory controller sequentially writes measurement data generated according to the control of the trigger detector to the memory. On the other hand, the trigger detector monitors the measurement data written in the memory, and when it is determined that an event satisfying a predetermined standard has occurred, the trigger detector identifies the memory address (data number) of the measurement data and reports it to the CPU. . In response to this, the CPU reads out the measurement data generated at the occurrence of the event and the measurement data generated before and after the event based on the memory address reported by the trigger detector from the memory and outputs them to the display controller. Thereby, the signal waveform of the input signal at the time of the event occurrence is displayed on the display device under the control of the display controller.
JP 2002-250745 A (page 3, FIG. 1-3)

  However, the conventional waveform recording apparatus has the following problems. That is, the conventional waveform recording apparatus employs a configuration in which the CPU reads measurement data from the memory and outputs it to the display controller based on the memory address reported by the trigger detector. Therefore, in this waveform recording device, when the CPU reads out the measurement data written in the memory, the memory address at which the target measurement data is recorded is reported to the memory controller between the memory controller and the CPU. It is necessary to provide an address line. On the other hand, in this type of waveform recording apparatus, a recording apparatus main body provided with a display, a display controller, a CPU, and the like, and a data recording unit including an A / D converter, a memory, a memory controller, and the like are separated. There are configured types of devices. In this case, an interface circuit such as a level conversion circuit or an insulation circuit is required between the recording apparatus main body and the data recording unit to absorb the difference in power supply voltage between them. Therefore, as a result of the complexity of the interface circuit required for the address lines, the conventional waveform recording apparatus has a problem that its manufacturing cost has increased.

  In this case, instead of the memory controller in the conventional waveform recording apparatus, an FIFO (First-In First-Out) controller (a memory controller that manages writing and reading of measurement data to and from the memory by a first-in first-out method) is adopted. It is possible to simplify the interface circuit as much as the line becomes unnecessary. On the other hand, in this type of waveform recording apparatus, the CPU performs RMS (Root Mean Square) conversion processing (measurement value) using measurement data sequentially generated by an A / D converter in order to obtain an effective value for an input signal. A process of executing a process of calculating a square root of an average value of values obtained by squaring. In this case, when the CPU reads the measurement data from the memory under the control of the FIFO controller, the FIFO controller reads the measurement data written in the memory next to the read measurement data, and the FIFO controller reads the measurement data from the memory. A pointer for specifying a reading position for reading data is moved.

  For this reason, after the CPU reads out one measurement data, the one measurement data (the same measurement data as the already read out measurement data) can be read out again from the memory in order to execute the RMS conversion process (double multiplication). Therefore, when a normal FIFO controller is adopted in the waveform recording apparatus that executes the RMS conversion process, a cache memory for temporarily storing the measurement data read from the memory by the CPU is separately provided, and the CPU memory It is necessary to execute processing for expanding the measurement data read from the memory in the space. For this reason, even if the FIFO controller is adopted to simplify the configuration of the interface circuit, the manufacturing cost increases as much as the cache memory is required, and it takes time to develop the measurement data read from the memory. There arises a problem that high-speed data processing (product-sum operation processing) becomes difficult.

  The present invention has been made in view of such a problem, and a main object of the present invention is to provide a data processing apparatus and a data processing method capable of executing arithmetic processing including double multiplication at low cost and at high speed.

  In order to achieve the above object, the data processing apparatus according to claim 1, wherein a memory for storing measurement data, a write pointer for specifying a write position for writing the measurement data to the memory, and the measurement data are read from the memory. A memory controller having a read pointer for specifying a read position and managing writing and reading of the measurement data by a first-in first-out method, and an operation for executing a predetermined calculation process including a double multiplication using the measurement data read from the memory The memory controller, when the one measurement data is read twice from the memory by the arithmetic unit, the memory controller next to the read measurement data The reading position can be specified to write the measurement data written in the memory. The pointer is moved out. Note that the process of “moving the read pointer” in the present invention means a process of changing the value (information) about the read position specified by the read pointer.

  According to a second aspect of the present invention, there is provided a data processing method using a write pointer for specifying a write position for writing measurement data to the memory and a read pointer for specifying a read position for reading the measurement data from the memory. A data processing method for managing writing and reading by a first-in first-out method, and executing predetermined arithmetic processing including double multiplication using the measurement data read from the memory, wherein two pieces of the measurement data from the memory are When the data is read once, the read pointer is moved so as to be able to specify the write position of the measurement data written in the memory next to the read measurement data.

  According to the data processing device according to claim 1 and the data processing method according to claim 2, when the writing and reading of the measurement data are managed by the first-in first-out method, and when one measurement data is read from the memory twice By moving the read pointer so that the write position of the measurement data written in the memory next to the read measurement data can be specified, an address line for reading the measurement data from the memory becomes unnecessary. It is possible to simplify the interface circuit to be disposed between the memory controller and the arithmetic unit rather than the waveform recording device. Further, since it is not necessary to expand the measurement data in the memory space of the arithmetic unit in order to execute the double multiplication, a cache memory for expanding the measurement data becomes unnecessary. Therefore, the manufacturing cost of the data processing device can be sufficiently reduced. In addition, since the development process of the measurement data read from the memory can be eliminated, high-speed data processing (product-sum operation processing such as RMS conversion processing) can be realized correspondingly.

  The best mode of a data processing apparatus and data processing method according to the present invention will be described below with reference to the accompanying drawings.

  First, the configuration of the measuring apparatus 1 will be described with reference to the drawings.

  A measuring apparatus 1 shown in FIG. 1 is an apparatus (for example, a waveform recording apparatus) that records sampling data D for an input signal S to be measured and displays a signal waveform or the like based on the recorded sampling data D on a display unit (not shown). Thus, the measuring device main body 2 and the measuring unit 3 are electrically connected via the interface circuit 4. The measuring apparatus body 2 includes a CPU 11 and a display unit. In this case, the CPU 11 includes a product-sum calculator 11a corresponding to the calculation unit in the present invention. In this case, the product-sum calculator 11a calculates an effective value for the input signal S based on the sampling data D.

  On the other hand, the measurement unit 3 includes an A / D converter 21, a RAM 22, and a memory controller 23. The A / D converter 21 A / D converts (samples) the input signal S at a predetermined cycle to generate sampling data D corresponding to the measurement data in the present invention. The RAM 22 corresponds to a memory in the present invention, and stores sampling data D under the management of the memory controller 23. The memory controller 23 is a so-called FIFO controller, and manages writing of the sampling data D generated by the A / D converter 21 into the RAM 22 and reading of the sampling data D from the RAM 22 by the CPU 11 by a first-in first-out method. Specifically, as shown in FIG. 2, the memory controller 23 sets a write pointer (Write Pointer) WP for specifying a write position for writing the sampling data D to the RAM 22 and a read position for reading the sampling data D from the RAM 22. A reading pointer (Read Pointer) RP for identification is provided.

  In FIG. 2 and FIGS. 3, 4, 6 and 7 to be referred to later, in order to facilitate understanding of the present invention, a data management method using the write pointer WP and the read pointer RP is conceptually illustrated. In practice, however, both pointers WP and RP are configured by a register or the like that stores a value (information) that can specify a predetermined memory address on the RAM 22. 2, 4, 6, and 7 illustrate an example in which 10 sections (areas where one sampling data D is recorded) of “section 01” to “section 10” are managed by both WP and RP. However, the number of sections is merely an example. Actually, when the sampling speed of the input signal S is 10 kHz and the CPU 11 performs processing 20 times per second, 500 sampling data D are processed once. Therefore, management by the first-in first-out method is executed for about 1000 sections. In addition to the pointers WP and RP, the memory controller 23 includes a full flag, an empty flag, and the like. Since these functions are the same as those of a known FIFO controller, Illustration and detailed description are omitted.

  The interface circuit 4 includes an insulating circuit and a level conversion circuit that allow transmission and reception of various control signals and sampling data D between the CPU 11 and the memory controller 23 while insulating the measuring apparatus body 2 and the measuring unit 3 from each other. Yes. Further, the interface circuit 4 includes a control line for the CPU 11 to access the memory controller 23, a data line (both not shown) for reading the sampling data D from the RAM 22, and the like. In the measurement apparatus 1, the RAM 22, the memory controller 23, the interface circuit 4, and the CPU 11 (product-sum calculator 11a) are combined to constitute a data processing apparatus according to the present invention.

  Next, a method of recording the sampling data D by the measuring apparatus 1 and a calculation processing method using the sampling data D will be described with reference to the drawings.

  In the measurement apparatus 1, the A / D conversion unit 21 generates the sampling data D (sampling process for the input signal S) and the RMS conversion process based on the generated sampling data D are executed in parallel. A signal waveform based on the effective value of the input signal S is displayed on a display unit (not shown). Specifically, first, the A / D conversion unit 21 performs A / D conversion on the input signal S at a predetermined cycle, thereby generating sampling data D and sequentially outputting them to the memory controller 23. At this time, as shown in FIG. 2, the write pointer WP in the memory controller 23 points to the first “partition 01” and the read pointer RP points to the last “partition 10”.

  In the memory controller 23, the position (partition) where the sampling data D is to be written to the RAM 22 is indicated by the write pointer WP, and the position at which the reading of the sampling data D from the RAM 22 is completed (partition: the sampling data D from the RAM 22). A management method is adopted in which a section immediately preceding a section to be read out) is indicated by a read pointer RP. Accordingly, the memory controller 23 stores the sampling data D (“D01” in FIG. 3) output from the A / D conversion unit 21 in the RAM 22 in correspondence with the position (in this example, “partition 01”) pointed to by the write pointer WP. And the write pointer WP is moved to the next “section 02” as shown in FIG.

  On the other hand, as the empty flag is rewritten from “value = 1” to “value = 0” by the sampling data D being written to the RAM 22 by the memory controller 23, the CPU 11 starts the RMS conversion processing for the sampling data D To do. Specifically, the CPU 11 accesses the FIFO memory address defined in advance (the memory address assigned for accessing the RAM 22 in the memory space of the CPU 11) and reads the sampling data D. At this time, the memory controller 23 responds to an access request to the RAM 22 by the CPU 11 (a request to read the sampling data D) (partition: “partition 10” in this example) indicated by the read pointer RP. In this example, a memory address corresponding to “partition 01”) is specified, and access to the specified memory address is permitted. As a result, the first sampling data D (“D01” in the figure) is read by the CPU 11 from the memory address corresponding to “partition 01” of the RAM 22.

  Next, the CPU 11 accesses the above FIFO memory address and reads the sampling data D that is the same as the sampling data D read immediately before from the RAM 22. In this case, in a general FIFO controller, the read pointer RP is moved to a position indicating the next section when the predetermined sampling data D is read once from the RAM 22 by the CPU 11, whereas this memory controller 23, when the predetermined sampling data D (“D01” in this example) is read once by the CPU 11, the read pointer RP is maintained at the same position. Therefore, the memory controller 23 specifies the memory address corresponding to the next partition (in this example, “partition 01”) of the position (partition: “partition 10” in this example) indicated by the read pointer RP, and specifies the specified memory. Allow access to the address. Thereby, the CPU 11 reads from the RAM 22 the same sampling data D (that is, “D01”) as the sampling data D (“D01” in the figure) read immediately before. In the CPU 11, the product-sum calculator 11 a executes double multiplication for the measurement value using the two read sampling data D.

  Further, as shown in FIG. 4, the memory controller 23 completes the reading as the same sampling data D in the RAM 22 (“D01” in this example) is read twice by the CPU 11. The read pointer RP is moved to a section corresponding to the sampling data D (in this example, “section 01”). In this way, when the CPU 11 first reads one sampling data D from the RAM 22, the reading pointer RP is maintained at the same position, and the reading pointer RP is changed to the next with the second reading of the one sampling data D. As shown in FIG. 5, whether the same sampling data D (in this example, “D01”) is continuously written in the same FIFO memory address by being moved to the partition. As perceived.

  On the other hand, when the next sampling data D (in this example, “D02”) is output by the A / D conversion unit 21, the memory controller 23, as shown in FIG. In this case, the sampling data D ("D02" in the figure) output from the A / D conversion unit 21 is written into the RAM 22 corresponding to "partition 02"), and the write pointer WP is set to the next "partition 03". To "". Further, the CPU 11 reads the sampling data D by accessing the above FIFO memory address. At this time, the memory controller 23 specifies the memory address corresponding to the next partition (in this example, “partition 02”) of the position (partition: in this example “partition 01”) indicated by the read pointer RP. Allow access to the specified memory address. As a result, the second sampling data D (“D02” in the figure) is read by the CPU 11 from the memory address corresponding to the “partition 02” of the RAM 22.

  Next, the CPU 11 accesses the FIFO memory address again and reads the sampling data D (in this example, “D02”) that is the same as the sampling data D read immediately before from the RAM 22. In this case, as described above, In the memory controller 23, when the predetermined sampling data D (in this example, “D02”) is read once by the CPU 11, the read pointer RP is maintained at the same position. A memory address corresponding to the next partition (in this example, “partition 02”) of the position (partition: “partition 01” in this example) indicated by the read pointer RP is specified, and access to the specified memory address is permitted. As a result, the CPU 11 reads the sampling data read immediately before. The same sampling data D (that is, “D02”) as the data D (“D02” in the figure) is read from the RAM 22. Further, the CPU 11 uses the two sampling data D read by the product-sum calculator 11a. Then, a double multiplication is performed on the measured value, and an average value with the solution of the double multiplication calculated immediately before is calculated.

  Further, as shown in FIG. 7, the memory controller 23 completed the reading as the same sampling data D in the RAM 22 (“D02” in this example) is read twice by the CPU 11. The read pointer RP is moved to a section corresponding to the sampling data D (in this example, “section 02”). Thereafter, the sampling data D (“D03”, “D04”,...) Sequentially generated by the A / D converter 21 is also similar to the sampling data D (“D01” and “D02”). Writing to the RAM 22 by the memory controller 23 and reading from the RAM 22 and arithmetic processing by the CPU 11 are executed. Thereby, the effective value for the input signal S is calculated, and a signal waveform based on the calculated effective value is displayed on the display unit (not shown).

  As described above, according to the measurement apparatus 1 and the data processing method by the measurement apparatus 1, writing and reading of the sampling data D are managed by the first-in first-out method, and one sampling data D is read from the RAM 22 twice. Further, by moving the read pointer RP so that the writing position of the sampling data D written in the RAM 22 next to the read sampling data D can be specified, an address line for reading the sampling data D from the RAM 22 is not necessary. Therefore, the interface circuit 4 can be simplified more than the conventional waveform recording apparatus. Further, since it is not necessary to expand the sampling data D in the memory space of the CPU 11 in order to execute the double multiplication, a cache memory for expanding the sampling data D becomes unnecessary. Therefore, the manufacturing cost of the measuring device 1 can be sufficiently reduced. In addition, since the development process of the sampling data D read from the RAM 22 can be made unnecessary, high-speed data processing (RMS conversion process: product-sum operation process) can be realized.

  In addition, this invention is not limited to said structure and method. For example, in the measurement apparatus 1 described above, as shown in FIG. 5, the same sampling data D (in this example, “D01”) is continuously written at the same FIFO memory address in the memory space of the CPU 11. Although the structure recognized as if is adopted, the present invention is not limited to this.

  Specifically, as an example, as shown in FIG. 8, one sampling data D (in this example) is identical to two FIFO memory addresses (in this example, “FIFO memory addresses A and B”) in the memory space of the CPU 11. Then, it is possible to adopt a configuration in which “D01”) is recognized as if it were written one by one. When this configuration is adopted, the CPU 11 is configured to permit access to the same memory address on the RAM 22 when memory access to any of the “FIFO memory addresses A and B” is requested by the CPU 11. When the reading of the sampling data D corresponding to “address A” is completed, the position is maintained without moving the reading pointer RP, and the reading of the sampling data D corresponding to “FIFO memory address B” is completed. The memory controller 23 may be configured to move the read pointer RP to the next section. In this configuration as well, the interface circuit 4 can be simplified as compared with the conventional waveform recording apparatus, and the cache memory for developing the sampling data D is not required, similarly to the measurement apparatus 1 described above. it can. Therefore, the manufacturing cost of the measuring device 1 can be sufficiently reduced. In addition, since the development process of the sampling data D read from the RAM 22 can be made unnecessary, high-speed data processing (RMS conversion process: product-sum operation process) can be realized.

1 is a block diagram showing a configuration of a measuring device 1. FIG. It is explanatory drawing for demonstrating the management method of writing and reading of the sampling data D by the memory controller 23 using the write pointer WP and the read pointer RP. 6 is an explanatory diagram for explaining a position of a write pointer WP when first sampling data D (“D01”) is written in a RAM 22 by the memory controller 23. FIG. FIG. 10 is an explanatory diagram for explaining a position of a read pointer RP when one sampling data D (“D01”) is read twice by the CPU 11. 3 is an explanatory diagram for explaining a memory space of a CPU 11; FIG. 6 is an explanatory diagram for explaining a position of a write pointer WP when second sampling data D (“D02”) is written to a RAM 22 by the memory controller 23. FIG. FIG. 6 is an explanatory diagram for explaining a position of a read pointer RP when one sampling data D (“D02”) is read twice by the CPU 11. FIG. 10 is another explanatory diagram for explaining a memory space of the CPU 11.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Measuring apparatus 2 Measuring apparatus main body 3 Measuring unit 4 Interface circuit 11 CPU
11a Multiply-accumulator 22 RAM
23 Memory Controller D Sampling Data RP Read Pointer S Input Signal WP Write Pointer

Claims (2)

A memory for storing measurement data, a write pointer for specifying a write position for writing the measurement data to the memory, and a read pointer for specifying a read position for reading the measurement data from the memory; A data processing apparatus comprising: a memory controller that manages reading by a first-in first-out method; and a calculation unit that executes predetermined calculation processing including double multiplication using the measurement data read from the memory,
The memory controller, when one piece of measurement data is read from the memory by the arithmetic unit twice, writes a write position of the measurement data written in the memory next to the read measurement data. A data processing apparatus for moving the read pointer in an identifiable manner. The writing and reading of the measurement data are managed by a first-in first-out method using a write pointer for specifying a write position for writing measurement data to the memory and a read pointer for specifying a read position for reading the measurement data from the memory. A data processing method for executing predetermined arithmetic processing including double multiplication using the measurement data read from a memory,
A data processing method for moving the read pointer so as to be able to specify a write position of the measurement data written in the memory next to the read measurement data when one measurement data is read out from the memory twice.

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