JP2008010882A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device using a reliable TFT structure. <P>SOLUTION: In a CMOS circuit formed on a substrate 101, sub gate wiring (first wiring) 102a and main gate wiring (second gate wiring) 107a are provided in an N-channel type TFT. An LDD region 113 overlaps the first wiring 102a and does not overlap the second wiring 107a. Consequently, if gate voltage is applied to the first wiring, a GOLD structure is obtained, and if gate voltage is not applied to the first wiring, the LDD structure is obtained. The GOLD structure and the LDD structure can be used appropriately for circuit specifications. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs). For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and a configuration of an electronic apparatus in which such an electro-optical device is mounted as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are also semiconductor devices.

  Since a thin film transistor (hereinafter referred to as TFT) can be formed on a transparent glass substrate, application development to an active matrix liquid crystal display (hereinafter referred to as AM-LCD) has been actively promoted. Since a TFT using a crystalline semiconductor film (typically a polysilicon film) has high mobility, a high-definition image display can be realized by integrating functional circuits on the same substrate. Yes.

  An active matrix type liquid crystal display device requires 1 million TFTs with only pixels as the screen resolution becomes higher. If a functional circuit is further added, a larger number of TFTs are required, and in order to stably operate the liquid crystal display device, it is necessary to ensure the reliability of individual TFTs and to operate them stably.

  However, TFTs are not necessarily equivalent to MOSFETs manufactured on a single crystal semiconductor substrate in terms of reliability. As in the case of MOSFETs, when TFTs are operated for a long period of time, a phenomenon such as a decrease in mobility and on-current occurs. One of the causes of such a phenomenon is deterioration of characteristics due to hot carriers generated with an increase in channel electric field.

  On the other hand, in a MOSFET, an LDD (Lightly Doped Drain) structure is well known as a technique for improving reliability. In this structure, a low concentration impurity region is provided inside the source / drain region, and this low concentration impurity region is called an LDD region. This structure is also adopted in the TFT.

  Further, in MOSFETs, a structure is known in which an LDD region overlaps (overlaps) with a gate electrode to some extent via a gate insulating film. There are several methods for forming this structure. For example, structures called GOLD (Gate-drain Overlapped LDD) and LATID (Large-tilt-angle implanted drain) are known. With such a structure, hot carrier resistance could be increased.

  Attempts have also been made to apply such MOSFET structures to TFTs. However, in the case of a GOLD structure (in this specification, a structure having an LDD region to which a gate voltage is applied is referred to as a GOLD structure. Conversely, a structure having only an LDD region to which a gate voltage is not applied is referred to as an LDD structure). There is a problem that off current (current that flows when the TFT is in an off state) becomes large as compared with the LDD structure. Therefore, it is not suitable for use in a circuit that wants to suppress the off current as much as possible, such as a pixel matrix circuit of an AM-LCD.

  An object of the present invention is to provide an AM-LCD having high reliability by forming each circuit of the AM-LCD with a TFT having an appropriate structure according to the function. Accordingly, it is an object to improve the reliability of a semiconductor device (electronic device) having such an AM-LCD.

  The structure of the invention disclosed in this specification is a semiconductor device including a CMOS circuit formed of an N-channel TFT and a P-channel TFT, and the CMOS circuit includes only the N-channel TFT through an insulating layer. The active layer is sandwiched between one wiring and a second wiring, the active layer includes a low concentration impurity region in contact with a channel formation region, and the low concentration impurity region overlaps the first wiring, And it is formed so that it may not overlap with said 2nd wiring.

  In the above configuration, the first wiring and the second wiring may be electrically connected. That is, the first wiring and the second wiring have the same potential, and the same voltage can be applied (applied) to the active layer.

  According to another aspect of the invention, there is provided a semiconductor device including a CMOS circuit formed of an N-channel TFT and a P-channel TFT, wherein the CMOS circuit includes only the N-channel TFT and a first wiring through an insulating layer. And an active layer sandwiched between the second wirings, the second wiring including a portion having a laminated structure of a first conductive layer and a second conductive layer, the first conductive layer, and the second conductive layer. And a portion having a structure in which the third conductive layer is wrapped with the layer.

  In the above configuration, the third conductive layer uses a material having a lower resistance value than the first conductive layer or the second conductive layer. Specifically, the first conductive layer or the second conductive layer mainly contains an element selected from tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), or silicon (Si). It is preferable to use a conductive film as a component, or an alloy film or a silicide film in which the above elements are combined. The third conductive layer is preferably a film containing aluminum or copper as a main component.

  According to another aspect of the invention, there is provided a semiconductor device including a pixel matrix circuit having a pixel TFT formed of an N-channel TFT and a storage capacitor. The pixel TFT includes a first wiring and a second wiring through an insulating layer. The active layer includes a low-concentration impurity region in contact with a channel formation region, the low-concentration impurity region overlaps the first wiring, and the second wiring It is formed so that it may not overlap.

  Note that in the above structure, the first wiring may be held at a ground potential or a source power supply potential, or may be held at a floating potential.

  According to another aspect of the invention, there is provided a semiconductor device including a pixel matrix circuit having a pixel TFT formed of an N-channel TFT, wherein the pixel TFT has an active layer formed by a first wiring and a second wiring through an insulating layer. The second wiring has a third conductive layer formed of a layered structure of a first conductive layer and a second conductive layer, and the first conductive layer and the second conductive layer. And a portion made of a wrapped structure.

  According to another aspect of the invention, in a semiconductor device having a pixel matrix circuit and a driver circuit formed on the same substrate, a pixel TFT included in the pixel matrix circuit, an N-channel TFT included in the driver circuit, and Has a structure in which an active layer is sandwiched between a first wiring and a second wiring through an insulating layer, and the first wiring connected to the pixel TFT is held at a fixed potential or a floating potential, and is connected to the driver circuit. The first wiring connected to the included N-channel TFT is held at the same potential as the second wiring connected to the N-channel TFT included in the driver circuit.

  In the above structure, the active layer includes a low-concentration impurity region in contact with a channel formation region, and the low-concentration impurity region is formed so as to overlap the first wiring and not the second wiring. Has been.

  In addition, the second wiring includes a portion having a laminated structure of a first conductive layer and a second conductive layer, and a portion having a structure in which the third conductive layer is enclosed by the first conductive layer and the second conductive layer. And have.

  According to another aspect of the invention, there is provided a method for manufacturing a semiconductor device including a CMOS circuit formed of an N-channel TFT and a P-channel TFT, the step of forming a first wiring on a substrate, and the first wiring Forming a first insulating layer on the first insulating layer; forming an active layer on the first insulating layer as an active layer of the N-channel TFT and an active layer of the P-channel TFT; Forming a second insulating layer so as to cover an active layer of the TFT and the active layer of the P-channel TFT, and forming a second wiring on the second insulating layer, One wiring is formed so as to cross only the active layer of the N-channel TFT.

  In the above configuration, the second wiring has a structure in which a third conductive layer is enclosed by a portion having a laminated structure of a first conductive layer and a second conductive layer, and the first conductive layer and the second conductive layer. The part which becomes is formed.

  According to another aspect of the invention, there is provided a method for manufacturing a semiconductor device including a CMOS circuit formed of an N-channel TFT and a P-channel TFT, the step of forming a first wiring on a substrate, and the first wiring Forming a first insulating layer on the first insulating layer; forming an active layer on the first insulating layer as an active layer of the N-channel TFT and an active layer of the P-channel TFT; Forming a second insulating layer over the active layer of the TFT and the active layer of the P-channel TFT, forming a first conductive layer on the second insulating layer, and the first conductive layer Forming a third conductive layer patterned on the first conductive layer; and forming a second conductive layer covering the third conductive layer, wherein the first wiring is formed of the N-channel TFT. Cross only the active layer Characterized in that it is made.

  The present invention is characterized in that an NTFT having the same structure is used as a GOLD structure or an LDD structure by controlling the voltage of the first wiring provided below the active layer. That is, the GOLD structure and the LDD structure can be realized on the same substrate without increasing the number of steps or making it complicated.

  Therefore, in a semiconductor device such as an electronic device having an AM-LCD or an AM-LCD as a display display, it is possible to arrange a circuit having an appropriate performance according to the specifications required by the circuit, and the performance and reliability of the semiconductor device. Was able to greatly improve.

[Embodiment 1]
An embodiment of the present invention will be described by taking as an example a CMOS circuit (inverter circuit) in which an N-channel TFT (hereinafter referred to as NTFT) and a P-channel TFT (hereinafter referred to as PTFT) are combined.

  The cross-sectional structure is shown in FIG. 1A, and the top view is shown in FIG. 1A and 1B will be described using the same reference numerals. 1B is a cross-sectional view taken along the lines AA ′, BB ′, and CC ′ in FIG. 1B. The cross-sectional views taken along the lines AA ′, BB ′, and CC ′ in FIG. Corresponds to each of the cross-sectional views shown in FIG.

  First, in FIG. 1A, 101 is a substrate, 102a, 102b and 102c are first wirings, 103 is a first insulating layer, 104 is an NTFT active layer, 105 is a PTFT active layer, and 106 is a second insulating layer. It is.

  On top of this, the second wiring 107a formed by stacking the first conductive layer 107a1 and the second conductive layer 107a2, the second wiring 107b formed by stacking the first conductive layer 107b1 and the second conductive layer 107b2, and the first A second wiring 107c formed by laminating a conductive layer 107c1 and a second conductive layer 107c2, a first conductive layer 107d1, and a second wiring 107d having a structure in which the third conductive layer d3 is sandwiched by the second conductive layer 107d2.

  Reference numeral 108 denotes a first interlayer insulating layer, 109 to 111 denote third wirings, 109 and 110 denote source wirings (including source electrodes), and 111 denotes drain wirings (including drain electrodes).

  In the CMOS circuit having the above structure, the substrate 101 can be a glass substrate, a quartz substrate, a metal substrate, a stainless steel substrate, a plastic substrate, a ceramic substrate, or a silicon substrate. When a silicon substrate is used, it is preferable to oxidize the surface in advance and provide a silicon oxide film.

  Further, the first wiring is a wiring having the same pattern as shown in FIG. 1B, but for convenience of description, the first wiring is divided into 102a, 102b, and 102c. Here, the first wiring 102a indicates an intersection with the active layer 103, the first wiring 102b indicates a connection part between TFTs, and the first wiring 102c indicates a power supply part common to each circuit.

  At this time, the first wiring 102a functions as a sub-gate electrode of the NTFT. That is, charge control of the channel formation region 112 is performed by the first wiring 102a and the second wiring (main gate electrode) 107a having the same potential as the first wiring 102a, and only the first wiring 102a is gated to the LDD region 113. The structure is such that a voltage (or a predetermined voltage) can be applied.

  Therefore, when only the second wiring 107a is functioned as a gate electrode, the GOLD structure is not obtained (the LDD structure is formed), but the GOLD structure can be realized only by combining with the first wiring 102a. As will be described later, the first wiring 102a also serves as a light shielding layer.

In addition, as long as it has electroconductivity as a material of 1st wiring, you may use what kind of material. However, it is desirable that the material has heat resistance that can withstand the subsequent process temperature. For example, tantalum (Ta), titanium (Ti), tungsten (W)
Alternatively, a conductive film containing an element selected from molybdenum (Mo) or silicon (Si) as a main component (component ratio is 50% or more), or an alloy film or a silicide film in which the elements are combined may be used.

  As a feature of the present embodiment, the first wiring 102a is provided only in the NTFT and not in the PTFT. In the case of FIG. 1A, the PTFT has neither an offset region nor an LDD region, but may have either one or both.

  Due to such a structure, as shown in FIG. 1B, the first wiring reaches the NTFT from the power supply portion through the connection portion, and functions as a sub-gate electrode of the NTFT.

  The second wirings are all wirings having the same pattern, but are distinguished for each part for convenience of explanation. The method of distinction is almost the same as that of the first wiring. In FIG. 1A, 107a is an intersection with the NTFT active layer 104, 107b is an intersection with the PTFT active layer 105, and 107c is a connection between TFTs. Reference numeral 107d denotes a power supply unit.

The second wiring is basically formed by laminating two kinds of conductive layers. It is sufficient that both the upper and lower conductive layers have conductivity, such as a tantalum (Ta) film and titanium (Ti).
A film, a tungsten (W) film, a molybdenum (Mo) film, and a silicon (Si) film can be formed in any combination. Further, these alloy films and silicide films may be used.

  However, it is necessary to select a material that can be patterned into the same shape after lamination. That is, it is desirable to be able to etch in a lump after stacking or a combination in which the lower layer side can be etched using the upper layer side as a mask. In addition, the conductive layer provided in the lower layer must have an etching selectivity with respect to the third conductive layer 107d3.

  The third conductive layer 107d3 is a conductive layer containing aluminum (Al) or copper (Cu) as a main component (having a component ratio of 50% or more), and has a structure in which the first conductive layer 107d1 and the second conductive layer 107d2 are enclosed. The second wiring 107d is formed by adopting (hereinafter referred to as a cladding structure). The second wiring 107d forms a wiring corresponding to the power supply unit.

  The CMOS circuit is an inverter circuit frequently used as a driver circuit for AM-LCD and other signal processing circuits. Since these driver circuits and signal processing circuits are integrated with high density, it is desired to make the wiring width as thin as possible. Therefore, the crossing portion (gate electrode portion) and connection portion (wiring routing portion) with the active layer are designed to be as thin as possible. In addition, since the length of the wiring itself is not so long, these portions are not easily affected by the wiring resistance.

  However, the power supply unit is greatly affected by the wiring resistance because the length of the wiring itself is long. Therefore, in this embodiment, a material mainly composed of aluminum or copper having a low resistance is used to reduce the wiring resistance. Further, if the structure is the second wiring 107d, the wiring width is somewhat thick, but the power supply unit is not a problem because it is formed outside the circuit integrated in a complicated manner.

  Note that when the present invention is used for a semiconductor device in which the circuit is small and there is no extremely long wiring, such as an AM-LCD having a diagonal size of 4 inches or less, the wiring serving as a power supply unit is also short, so that it is not always necessary. The clad structure may not be used. In other words, it can be said that the structure shown in FIG. 1 is effective for an AM-LCD having a diagonal of 4 inches or more.

As described above, there are the following two features of the CMOS circuit of this embodiment.
1. Only the NTFT is provided with a first wiring (sub-gate wiring), and the same voltage as that of the second wiring (main gate wiring) is applied to the first wiring, or the NTFT has a GOLD structure by applying a predetermined voltage. it can.
2. The gate electrode part and the connection part of the second wiring are made highly integrated by narrowing the wiring width, and the power supply part has a structure (cladding structure) in which the low-resistance third conductive layer is sandwiched between the first and second conductive layers. The resistance can be lowered.

[Embodiment 2]
An embodiment of the present invention will be described by taking a pixel matrix circuit using NTFTs as pixel TFTs as an example. Since the pixel matrix circuit is formed on the same substrate as the CMOS circuit described in the “Embodiment 1” at the same time, the description of “Embodiment 1” may be referred to for details regarding the wiring having the same name.

  The cross-sectional structure is shown in FIG. 2A, and the top view is shown in FIG. 2A and 2B will be described using the same reference numerals. A cross-sectional view taken along A-A ′ and B-B ′ in FIG. 2B corresponds to each cross-sectional view indicated by A-A ′ and B-B ′ in FIG.

  2A, 201 is a substrate, 202a, 202b, and 202c are first wirings, 203 is a first insulating layer, 204 is an active layer of a pixel TFT (NTFT), and 205 is a second insulating layer. In addition, although the pixel TFT has illustrated the double gate structure, it may be a single gate structure or a multi-gate structure in which three or more TFTs are connected in series.

  On the second insulating layer 203, a first conductive layer 206a1, a second conductive layer 206a3 sandwiched by a second conductive layer 206a3, a second wiring 206a, a first conductive layer 206b1, and a second conductive layer 206b2 are stacked. A second wiring 206b formed by stacking the first conductive layer 206c1 and the second conductive layer 206c2, a capacitor wiring 207 formed by stacking the first conductive layer 207a and the second conductive layer 207b. .

  At this time, the capacitor wiring 207 forms a storage capacitor with the active layer 204 (specifically, a region extending from the drain region) using the first insulating layer 205 as a dielectric. At this time, if the first insulating layer 205 has a laminated structure in which a silicon oxide film is provided on a silicon nitride film, and the second wiring is formed after selectively removing the silicon oxide film in the portion serving as the storage capacitor, A storage capacitor using only a silicon nitride film having a high relative dielectric constant as a dielectric can be realized.

  Reference numeral 208 denotes a first interlayer insulating layer, reference numerals 209 and 210 denote third wirings, reference numeral 209 denotes a source wiring (including a source electrode), and reference numeral 210 denotes a drain wiring (including a drain electrode). Furthermore, a second interlayer insulating layer 211, a black mask 212, a third interlayer insulating layer 213, and a pixel electrode 214 are provided thereon.

  Further, the first wiring is a wiring having the same pattern as shown in FIG. 2B, but for the sake of convenience of explanation, the first wiring is divided into 202a, 202b, and 202c. Here, the first wiring 202a is a wiring portion that does not function as a gate electrode, and 202b and 202c are intersections with the active layer 204 and are portions that function as a gate electrode portion.

  The first wiring shown here is formed at the same time as the first wiring described in the first embodiment. Therefore, description of materials etc. is omitted.

At this time, the first wirings 202b and 202c function as a light shielding film of the pixel TFT. That is, there is no function as a sub-gate wiring as described in “Embodiment 1,” and it is set at a fixed potential or in a floating state (electrically isolated state).
The fixed potential may be a ground potential or a source power supply potential (the same potential as the source wiring). By doing so, holes generated by hot carrier injection can be extracted from the channel formation region. As a result, charge neutralization is performed and hot carriers disappear.

  As described above, charge control of the channel formation regions 215 and 216 is performed by the first wiring 206b and the first wiring 206c, and operates as an LDD structure. Thereby, an increase in off-current can be effectively suppressed.

  As described above, in the pixel matrix circuit shown in this embodiment, NTFT is used as the pixel TFT, and its structure is the same as that of the TFT of the CMOS circuit described in “Embodiment 1.” However, in the CMOS circuit, a GOLD structure is realized by applying a predetermined voltage to the first wiring and using it as a sub-gate wiring, whereas in the pixel matrix circuit, the first wiring is used as an LDD structure with a fixed potential or a floating potential. There is a difference.

  That is, the greatest feature of the present invention is that NTFTs having the same structure are formed on the same substrate, and the GOLD structure and the LDD structure are selectively used depending on the presence / absence of a voltage applied to the first wiring (sub-gate wiring). This makes it possible to design an optimum circuit without increasing the number of processes.

  In the second wirings 206a, 206b, and 206c, 206b and 206c are gate electrode portions, and 206a is a wiring portion. Since it is desirable for the wiring portion to have a wiring resistance as low as possible, a clad structure is adopted. However, since the wiring width determines the channel length, the gate electrode portion is designed to have a narrow line width as a stack of the first conductive layer and the second conductive layer.

  The contents and effects of the clad structure have already been described in “Embodiment 1”, and a description thereof will be omitted here. Further, as described in “Embodiment 1,” it goes without saying that an AM-LCD having a diagonal of 4 inches or less does not necessarily have a clad structure.

  The configuration of the present invention described above will be described in more detail in the following examples.

  In this example, a method for manufacturing the CMOS circuit described in Embodiment Mode 1 will be described. FIG. 3 is used for the description.

First, a glass substrate was prepared as the substrate 301, and first wirings 302a, 302b, and 302c were formed thereon. As a material for the first wiring, a laminated film in which a tungsten silicide (WSix) film and a silicon film were sequentially laminated by a sputtering method was used.
Needless to say, the stacking order may be reversed, and the CVD method may be used as the film forming means. Further, if an oxide film is formed on the surface after forming the laminated film, it is effective in terms of surface protection.

  Of course, the first wirings 302a, 302b, and 302c may be any conductive film, and other metal films, alloy films, or the like may be used. Note that it is effective to use a chromium film or a tantalum film capable of forming a pattern with a small taper angle because the flatness can be improved.

  Next, a first insulating layer 303 made of an insulating film containing silicon (silicon) was formed. The first insulating layer 303 serves as a base film for protecting the active layer, and also functions as a gate insulating film when the first wiring 302a is used as a sub-gate wiring.

In this embodiment, a structure in which a 50 nm silicon nitride film is first formed and an 80 nm silicon oxide film is laminated thereon is employed. Besides, SiOxNy (x / y = 0.01-100)
Alternatively, a silicon oxynitride film (also referred to as a silicon nitride oxide film) may be used. At that time, the breakdown voltage can be improved by making the nitrogen content higher than the oxygen content.

  Next, an amorphous silicon film (not shown) having a thickness of 50 nm was formed and crystallized by a known laser crystallization technique to form a crystalline silicon film. Then, the crystalline silicon film was patterned to form active layers 304 and 305. In this example, the crystallization process was performed by condensing a pulse oscillation type KrF excimer laser beam into a linear shape and irradiating the amorphous silicon film.

  In this embodiment, a crystalline silicon film obtained by crystallizing an amorphous silicon film is used as the semiconductor film used for the active layer. However, a microcrystalline silicon film may be used as another semiconductor film, and the crystalline film is directly crystalline. A silicon film may be formed. In addition to the silicon film, a compound semiconductor film such as a silicon germanium film can be used.

  Next, a second insulating layer 306 made of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film thereof was formed so as to cover the active layers 304 and 305. Here, a silicon oxynitride film was formed to a thickness of 100 nm by a plasma CVD method. The second insulating layer functions as a gate insulating film when the second wiring is used as the main gate wiring.

  Next, a tantalum film 307 having a thickness of 20 nm was formed as a first conductive layer, and a third conductive layer 308 made of an aluminum film to which scandium was added was formed thereon. Further, a second conductive layer 309 made of a tantalum film having a thickness of 200 nm was formed. These film forming methods may be sputtering or CVD.

  When the state of FIG. 3A is thus obtained, resist masks 310 and 311 are formed, and the first conductive layer 307 and the second conductive layer 309 are etched. Thus, the second wiring 312 having a laminated structure of tantalum films was formed. The second wiring 312 corresponds to the second wiring (main gate wiring) 107a in FIG.

  Next, an element belonging to Group 15 (typically phosphorus or arsenic) was added to form a low concentration impurity region 313. At the same time, an NTFT channel formation region 314 was defined. In this embodiment, phosphorus is used as an element belonging to Group 15, and is added by ion doping without mass separation. (Fig. 3 (B))

As an addition condition, the acceleration voltage is set to 90 keV, and phosphorus is added at a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ (preferably 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ ). The dose was adjusted. Since this concentration later becomes the impurity concentration of the LDD region, it needs to be precisely controlled.

  Next, the resist masks 310 and 311 were removed, and new resist masks 315 to 318 were formed. Then, the first conductive layer 307 and the second conductive layer 309 were etched to form second wirings 319 to 321. The second wirings 319, 320, and 321 correspond to the second wirings 107b, 107c, and 107d in FIG.

  Next, an element belonging to group 13 (typically boron or gallium) was added to form an impurity region 322. At the same time, the channel formation region 323 of the PTFT was defined. In this embodiment, boron is used as an element belonging to Group 13, and is added using an ion doping method without mass separation. (Figure 3 (C))

As an addition condition, the acceleration voltage is set to 75 keV, and boron is added at a concentration of 1 × 10 ^{19 to} 5 × 10 ²¹ atoms / cm ³ (preferably 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ). The dose was adjusted.

  Next, after removing the resist masks 315 to 318, resist masks 324 to 327 were formed again. In this example, these resist masks were formed using a backside exposure method. That is, the resist masks 324, 326, and 327 use the first wiring as a mask, and the resist mask 325 uses the second wiring as a mask. When the first wiring is used as a mask, there is a slight wraparound of light, so that the line width is narrower than that of the first wiring. This line width can be controlled by the exposure conditions.

  Of course, these resist masks can also be formed using a mask. In this case, the degree of freedom in pattern design increases, but the number of masks increases.

When the resist masks 324 to 327 were thus formed, an addition process of an element belonging to Group 15 (phosphorus in this embodiment) was performed. Here, the acceleration voltage is 90 keV, and the dose is set so that phosphorus is added at a concentration of 1 × 10 ^{19 to} 5 × 10 ²¹ atoms / cm ³ (preferably 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ). Adjusted.

  This step defined the NTFT source region 328, drain region 329, and LDD region 330. Further, a source region 331 and a drain region 332 of the PTFT are defined. In this step, phosphorus is also added to the source region and drain region of the PTFT. However, if higher concentration boron is added in the previous step, the P type is maintained because it is not inverted to the N type.

  After adding the impurity element imparting one conductivity to the NTFT and PTFT in this way, the impurity element was activated using the furnace annealing method, the laser annealing method, the lamp annealing method, or a combination thereof.

When the state of FIG. 3D is obtained in this way, a first interlayer insulating layer 333 formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a resin film, or a stacked film thereof is formed.
Then, contact holes were opened to form source wirings 334 and 335 and a drain wiring 336. (Figure 3 (E))

  In this embodiment, the first interlayer insulating layer 333 has a two-layer structure in which a silicon nitride film is first formed to 50 nm and a silicon oxide film is further formed to 950 nm. In this example, the source wiring and the drain wiring were formed by patterning a laminated film having a three-layer structure in which a titanium film 100 nm, an aluminum film 300 nm containing titanium, and a titanium film 150 nm were successively formed by sputtering.

  Thus, a CMOS circuit having a structure as shown in FIG. The CMOS circuit of this example has the structure shown in FIG. 1A, and the description thereof has been described in detail in “Embodiment 1”, and thus description thereof is omitted here. Further, in obtaining the structure of FIG. 1A, it is not necessary to be limited to the manufacturing process of this embodiment. For example, the NTFT may have a double gate structure and the PTFT may have a single gate structure.

  Note that the CMOS circuit described in this embodiment is a driver circuit (shift register circuit, buffer circuit, level shifter circuit, sampling circuit, etc.) and other signal processing circuits (dividing circuit, D / A converter) in the AM-LCD. Circuit, γ correction circuit, operational amplifier circuit, etc.).

  In this embodiment, a substantial GOLD structure can be realized by using the first wiring of the NTFT as the sub-gate wiring, and deterioration due to hot carrier injection can be prevented. Therefore, a highly reliable circuit can be formed.

  In addition, the wiring line width is narrowed in places with high integration, and the cladding structure is used in places where the degree of integration is not very high (power supply section) to reduce wiring resistance and reduce delay time due to wiring resistance. It has become.

  In this example, a method for manufacturing the pixel matrix circuit described in “Embodiment 2” will be described. 4 and 5 are used for the description. Since the pixel matrix circuit is formed on the same substrate at the same time as the CMOS circuit shown in the first embodiment, the description will be made in accordance with the manufacturing process of the first embodiment. Therefore, description will be made using the same reference numerals as in FIG. 3 as necessary.

  First, second wirings 401 a, 401 b, and 401 c were formed on the glass substrate 301. The materials of these second wirings are as described in the first embodiment. Next, referring to Example 1, a first insulating layer 303, an active layer 402 of the pixel TFT, a second insulating layer 306, a first conductive layer 307, a third conductive layer 403, and a second conductive layer 309 were formed. Thus, the state of FIG. 4A is obtained. At this time, the CMOS circuit formed at the same time is in the state of FIG.

  Next, resist masks 404 to 407 were formed, and the first conductive layer 307 and the second conductive layer 309 were etched. In this way, the second wirings 408 and 409 and the capacitor wiring 410 were formed. Note that the second wiring 408 corresponds to the second wiring 206b in FIG. 2A, and the second wiring 409 corresponds to the second wiring 206c in FIG. The capacitor wiring 410 corresponds to the capacitor wiring 207 in FIG.

  Next, a phosphorus addition step for forming an LDD region later was performed to form low concentration impurity regions 411 to 413. At this time, channel formation regions 414 and 415 are defined. This step corresponds to the step of FIG. Therefore, in the process of FIG. 4B, the material and film thickness of the second wiring, and the condition for adding phosphorus are the same as those in the first embodiment.

  Next, a step corresponding to FIG. First, resist masks 416 and 417 were formed, and the first wiring layer 418 was formed by etching the first conductive layer 307 and the second conductive layer 309. The second wiring 418 corresponds to the second wiring 206a in FIG.

Next, a boron addition process was performed in order to produce a PTFT of a CMOS circuit.
In this embodiment, since the pixel TFT is formed of NTFT, the pixel matrix circuit is entirely covered with the resist mask 417. (Fig. 4 (C))

  Next, after removing the resist masks 416 and 417, resist masks 419 to 422 were formed by a backside exposure method. Then, a phosphorus addition step was performed to form a source region 423, a drain region 424, and an LDD region 425. At this time, the back surface exposure conditions, the phosphorus addition conditions, and the like may be in accordance with the step of FIG.

  Note that in FIG. 4D, for convenience of description, the source region and the drain region are described. However, in the case of a pixel TFT, the source region and the drain region are reversed between when the pixel is charged and when the pixel is discharged. Absent.

  When the phosphorus and boron addition steps were completed in this way, the impurity element activation step was performed in the same manner as in Example 1. Then, a first interlayer insulating layer 333 was formed, contact holes were formed, and a source wiring 426 and a drain wiring 427 were formed. In this way, the state of FIG. At this time, the CMOS circuit is in the state shown in FIG.

Next, a second interlayer insulating layer 428 was formed so as to cover the source wiring 426 and the drain wiring 427. In this example, a 30 nm thick silicon nitride film was formed as a passivation film, and an 700 nm thick acrylic film was formed thereon. Of course, an insulating film containing silicon as a main component such as a silicon oxide film may be used, or another resin film may be used. Other resin films include polyimide film, polyamide film, BCB (benzocyclobutene)
A membrane or the like can be used.

  Next, a black mask 429 made of a 100 nm thick titanium film was formed. As the black mask 427, another film may be used as long as it has a light shielding property. Typically, a chromium film, an aluminum film, a tantalum film, a tungsten film, a molybdenum film, a titanium film, or a stacked film thereof may be used.

  Next, a third interlayer insulating layer 430 was formed. In this embodiment, the acrylic film is 1 μm thick, but the same material as that of the second interlayer insulating layer can be used.

  Next, a contact hole was formed in the third interlayer insulating layer 430, and a pixel electrode 431 made of a transparent conductive film (typically an ITO film) was formed. At this time, the pixel electrode 431 is electrically connected to the drain wiring 427. Therefore, since the contact hole becomes very deep, forming the inner side wall with a tapered shape or a curved surface is effective in preventing defects such as disconnection of the pixel electrode.

  Thus, a pixel matrix circuit having a structure as shown in FIG. 5A was completed. Note that although an example in which a transmissive AM-LCD is manufactured using a transparent conductive film as a pixel electrode is shown in this embodiment, a highly reflective metal film (such as a metal film containing aluminum as a main component) is used as a pixel electrode. By using it, it is possible to easily produce a reflective AM-LCD.

  The substrate in the state of FIG. 5A is referred to as an active matrix substrate. In this embodiment, a structure when an AM-LCD is actually manufactured is also described.

  When the state of FIG. 5A was obtained, the alignment film 432 was formed to a thickness of 80 nm. Next, a counter substrate was produced. The counter substrate was prepared by forming a color filter 434, a transparent electrode (counter electrode) 435, and an alignment film 436 on a glass substrate 433. Then, the alignment films 432 and 435 were subjected to rubbing treatment, and the active matrix substrate and the counter substrate were bonded to each other using a sealing material (sealing material). In the meantime, the liquid crystal 436 was held. In addition, what is necessary is just to provide the spacer for maintaining a cell gap as needed.

Thus, the AM-LCD (pixel matrix circuit portion) having the structure shown in FIG.
Was completed. The second interlayer insulating layer 428 and the third interlayer insulating layer 430 shown in this embodiment are actually formed also on the CMOS circuit shown in the first embodiment. In addition, at the same time as forming the black mask 429 and the pixel electrode 431, wiring is formed with the material constituting them, and the wiring is routed wiring (fourth wiring or fifth wiring) of the driver circuit and signal processing circuit of the AM-LCD. Can also be used.

  In this embodiment, the first wirings 401b and 401c provided in the pixel TFT are set to a fixed potential (ground potential or source potential). By doing so, holes generated at the end of the drain due to hot carrier injection can be extracted to the first wiring, so that the structure is suitable for improving reliability. Of course, the first wirings 401b and 401c can be set in a floating state, but in that case, the hole extraction effect cannot be expected.

  Further, as shown in the top view of FIG. 2B, the second wiring 418 located in the wiring portion adopts a clad structure so as to reduce the wiring resistance as much as possible.

  In this embodiment, the appearance of an AM-LCD including a pixel matrix circuit and a CMOS circuit (specifically, a driver circuit and a signal processing circuit formed of a CMOS circuit) of the present invention is shown in FIG.

  The active matrix substrate 601 includes a pixel matrix circuit 602, a signal line driver circuit (source driver circuit) 603, a scanning line driver circuit (gate driver circuit) 604, a signal processing circuit (signal division circuit, D / A converter circuit, and γ correction circuit). Etc.) 605 is formed, and FPC (flexible printed circuit) 606 is attached. Reference numeral 607 denotes a counter substrate.

  FIG. 7 is a block diagram showing in more detail various circuits formed on the active matrix substrate 601.

  In FIG. 7, reference numeral 701 denotes a pixel matrix circuit, which functions as an image display unit. Further, 702a is a shift register circuit, 702b is a level shifter circuit, and 702c is a buffer circuit. A circuit composed of these forms a gate driver circuit as a whole.

  In the block diagram of the AM-LCD shown in FIG. 7, the gate driver circuit is provided across the pixel matrix circuit, and each of them shares the same gate wiring, that is, one of the gate drivers is defective. Even so, redundancy is provided such that a voltage can be applied to the gate wiring.

  Reference numeral 703a denotes a shift register circuit, reference numeral 703b denotes a level shifter circuit, reference numeral 703c denotes a buffer circuit, and reference numeral 703d denotes a sampling circuit. These circuits form a source driver circuit as a whole. A precharge circuit 14 is provided on the opposite side of the source driver circuit across the pixel matrix circuit.

  By using the present invention, the reliability of an AM-LCD having a circuit as shown in FIG. 6 can be greatly improved. At that time, the CMOS circuit for forming the driver circuit and the signal processing circuit may be according to the first embodiment, and the pixel matrix circuit may be according to the second embodiment.

  In this example, a case where the CMOS circuit shown in “Embodiment 1” and the pixel matrix circuit shown in “Embodiment 2” are different in structure will be described. Specifically, an example is shown in which the structure is varied according to the specifications required by the circuit.

  Since the basic structure of the CMOS circuit is the structure shown in FIG. 1A and the basic structure of the pixel matrix circuit is the structure shown in FIG. 2A, only necessary portions are denoted by reference numerals in this embodiment. Will be explained.

  First, the structure shown in FIG. 8A is a structure in which the LDD region 801 is provided only on the drain side without the LDD region on the source side of the NTFT. Since a CMOS circuit used for a driver circuit or a signal processing circuit is required to operate at high speed, it is necessary to eliminate as much as possible a resistance component that may cause a decrease in operating speed.

  In the case of the CMOS circuit of the present invention, a GOLD structure is realized by applying a gate voltage to the first wiring functioning as a sub-gate wiring, thereby preventing deterioration due to hot carrier injection. However, hot carrier injection occurs at the end of the channel formation region on the drain region side, and an LDD region that overlaps (overlaps with) the gate electrode only has to exist there.

  Therefore, it is not always necessary to provide an LDD region at the end of the channel formation region on the source region side, and the LDD region provided on the source region side may work as a resistance component. Therefore, the structure as shown in FIG. 8A is effective in improving the operation speed.

  Note that the structure of FIG. 8A cannot be applied to the case of operation like a pixel TFT in which a source region and a drain region are interchanged. In the case of a CMOS circuit, since the source region and the drain region are usually fixed, a structure as shown in FIG. 8A can be realized.

  Next, FIG. 8B is basically the same as FIG. 8A, but the width of the LDD region 802 is narrower than that of FIG. 8A. Specifically, the thickness is set to 0.05 to 0.5 μm (preferably 0.1 to 0.3 μm). The structure of FIG. 8B is a structure that not only eliminates the resistance component on the source region side but also reduces the resistance component on the drain region side as much as possible.

  Such a structure is actually suitable for a circuit that is driven at a low voltage of 3 to 5 V and requires high-speed operation, such as a shift register circuit. Since the operating voltage is low, the problem of hot carrier injection does not become apparent even if the LDD region (strictly, the LDD region overlapping with the gate electrode) becomes narrow.

  Of course, in some cases, only the shift register circuit can completely eliminate the LDD region of the NTFT. In that case, even in the same driver circuit, the NTFT of the shift register circuit does not have an LDD region, and the structure shown in FIGS. 1A and 8B can be adopted for other circuits.

  Next, FIG. 8C shows an example of a CMOS circuit in which the NTFT has a double gate structure and the PTFT has a single gate structure. In this case, LDD regions 805 and 806 are provided only at the ends of the channel formation regions 803 and 804 on the side close to the drain region.

  As shown in FIG. 3D, the width of the LDD region is determined by the amount of light sneaking in the back surface exposure process. However, if a resist mask is formed by mask alignment, the mask design can be freely performed. Even in the structure shown in FIG. 8C, it is easy to provide an LDD region only on one side if a mask is used.

  However, by forming the gate wirings (second wirings) 807a and 807b and the first wirings 808 and 809 in a shifted manner as in this embodiment, an LDD region can be formed only on one side even if the backside exposure method is used. Is possible.

  With such a structure, the resistance component due to the LDD region on the source region side is eliminated, and the double gate structure has an effect of dispersing and relaxing the electric field applied between the source and the drain.

  Next, the structure of FIG. 8D is an embodiment of a pixel matrix circuit. In the case of the structure in FIG. 8D, LDD regions 809 and 810 are provided only on one side close to the source region or the drain region. In other words, the LDD region is not provided between the two channel formation regions 811 and 812.

  In the case of the pixel TFT, the source region and the drain region are frequently switched because an operation of repeating charging and discharging is performed. Therefore, the structure shown in FIG. 8D has a structure in which an LDD region is provided on the drain region side of the channel formation region, regardless of which is the drain region. Conversely, since the region between the channel formation regions 811 and 812 has no electric field concentration, it is more effective to increase the on-current (current that flows when the TFT is in the on-state) by eliminating the LDD region that is a resistance component. is there.

  8A to 8D, the LDD region is not provided at the end of the channel formation region on the source region side, but may be provided as long as the width is narrow. Absent. In such a structure, a resist mask may be formed by mask alignment, or the back surface exposure method may be used after adjusting the positions of the first wiring and the second wiring.

  Needless to say, the configuration of this embodiment can be combined with the first and second embodiments, and may be used for the AM-LCD shown in the third embodiment.

  In this embodiment, a case where a storage capacitor having a structure different from that of the pixel matrix circuit shown in Embodiment 2 is formed will be described. FIG. 9 is used for the description. Since the basic structure is the same as that shown in FIG. 2A, in this embodiment, only necessary portions will be described with reference numerals.

  First, the structure shown in FIG. 9A has a capacitor wiring 901, a first insulating layer 902, and an active layer (strictly, a portion extending from the drain region) 903 in which a storage capacitor is formed in the same layer as the first wiring. And formed with.

  The advantage of this structure is that an element belonging to Group 13 or 15 is added at a high concentration to the portion of the active layer that functions as the electrode of the storage capacitor, and has a conductivity type. Of course, the elements belonging to Group 13 or Group 15 may be formed simultaneously with the process of forming the source region or the drain region.

  In the case of the structure described in “Embodiment 2,” the active layer functioning as an electrode of the storage capacitor serves as a mask for the second wiring, so that no impurity element imparting conductivity is added, and a voltage is always applied to the capacitor wiring. Thus, the state where the inversion layer is formed in the active layer must be maintained. However, in the structure of FIG. 9A, since the active layer itself that functions as an electrode of the storage capacitor has conductivity, it is not necessary to apply a voltage, and it is only necessary to fix it to a ground potential or the like. It is.

  Thus, it can be said that the structure is effective in suppressing power consumption because it is not necessary to apply an extra voltage.

Further, the structure of FIG. 9B is the same as the structure of the storage capacitor shown in FIG.
This is an example in combination with the storage capacitor structure shown in FIG. Specifically, a first storage capacitor is formed by the first capacitor wiring 904, the first insulating layer 905, and the active layer 906 in the same layer as the first wiring, and the active layer 906, the second insulating layer 907, and the second wiring A second storage capacitor is formed by the second capacitor wiring 908 in the same layer.

  With this structure, it is possible to secure a capacity nearly twice that of the structure of the storage capacity shown in FIGS. 2A and 9A without increasing the number of steps. In particular, if the AM-LCD has a high definition, it is necessary to reduce the area of the storage capacitor in order to increase the aperture ratio. In such a case, the structure of FIG. 9B is effective.

  Note that it is effective to use the structure of this embodiment for the AM-LCD shown in Embodiment 3.

  In this embodiment, an example in which the first conductive layer constituting the second wiring is omitted in the CMOS circuit shown in FIG. 1A and the pixel matrix circuit shown in FIG. 2A is shown in FIG. Note that in FIG. 10A, parts having the same configuration as in FIG. 1A or 2A are denoted with the same reference numerals.

  In the CMOS circuit of FIG. 10A, the second wirings 11 to 13 are all formed of a single-layer tantalum film. That is, in comparison with the structure of FIG. 1A, the first conductive layer is omitted, and the second wiring is formed only by the second conductive layer. The film thickness may be 200 to 400 nm. Needless to say, in addition to tantalum, a conductive film containing an element selected from titanium, tungsten, molybdenum, or silicon as a main component, or an alloy film or a silicide film in which the elements are combined may be used.

  In such a structure, the power supply portion of the second wiring (the portion having the cladding structure in FIG. 1A) has a structure in which the third conductive layer 14a is covered with the second conductive layer 14b. However, in this structure, aluminum or copper, which are constituent elements of the third conductive layer 14a, may diffuse into the second insulating layer 106. Therefore, if a silicon nitride film is provided on the surface of the second insulating layer 106, diffusion of aluminum or copper can be effectively prevented.

  The structure of this embodiment can also be applied to a pixel matrix circuit. In the pixel matrix circuit of FIG. 10B, the second wiring (gate wiring) 16 and 17 and the capacitor wiring are only the second conductive layer (in this embodiment, a tantalum film), and it is desired to suppress wiring resistance among the gate wiring. The part employs a structure in which the third conductive layer 15a is covered with the second conductive layer 15b.

  Of course, it goes without saying that the circuits shown in FIGS. 10A and 10B are simultaneously formed on the same substrate.

  Further, the structure of this embodiment can be realized by simply omitting the step of forming the first conductive layer in the manufacturing steps shown in Embodiments 1 and 2. Further, the present invention can be applied to the AM-LCD of the third embodiment, and can be combined with the configurations shown in the fourth and fifth embodiments.

  In this embodiment, FIG. 11 shows an example in which the gate electrode portion of the NTFT has a clad structure in the CMOS circuit shown in FIG. 1A and the pixel matrix circuit shown in FIG. Note that in FIG. 11A, the same components as those in FIG. 1A or FIG.

  In the CMOS circuit shown in FIG. 11A, the gate electrode 21 of the NTFT has a clad structure in which the third conductive layer 21c is surrounded by the first conductive layer 21a and the second conductive layer 21b. At this time, the length of the channel formation region 22 matches the line width of the third conductive layer 21c.

  The LDD region 23 can be substantially divided into two regions. One overlaps the gate electrode 21 which is a part of the second wiring, and the other does not overlap the gate electrode 21. That is, in the structure of this embodiment, the GOLD structure can be realized only by the gate electrode which is a part of the second wiring. Further, since the LDD region that does not overlap with the gate electrode is provided outside the LDD region that overlaps with the gate electrode, the off-current can be extremely reduced.

  The same applies to the pixel matrix circuit shown in FIG. 11B, and the gate electrodes 24 and 25 of the pixel TFT are both the first conductive layers 24a and 25a and the second conductive layers 24b and 25b. The clad structure envelops 24c and 25c. At this time, the lengths of the channel formation regions 26 and 27 coincide with the line widths of the third conductive layers 24c and 25c. Further, both the LDD regions 28 and 29 can be substantially divided into two regions like the LDD region 23.

  In the case of the structures shown in “Embodiment 1” and “Embodiment 2”, the GOLD structure is realized by applying a gate voltage to the first wiring (sub-gate wiring) in the CMOS circuit, but in the pixel matrix circuit, the off current In order to lower the value, an LDD structure is employed. This is to avoid an increase in off-current, which is a disadvantage of the GOLD structure. Therefore, the advantage of the GOLD structure itself that suppresses deterioration of the on-current cannot be obtained.

  However, in the structure of this embodiment, since the NTFT having the GOLD structure is realized even in the pixel matrix circuit, the reliability can be further improved. Of course, the reason why the pixel TFT can have the GOLD structure is that an LDD region that does not overlap the gate electrode is provided outside the LDD region that overlaps the gate electrode.

  Here, a manufacturing process for realizing the structure of this embodiment will be described with reference to FIGS. However, since it is basically the same as the process described in the first embodiment, only the necessary portions will be described with new reference numerals.

  First, the third conductive layer 308 was formed according to the process of Example 1. In this example, the third conductive layer 31 was formed on the NTFT simultaneously with the formation of the third conductive layer 308. Then, a resist mask 32 was formed and phosphorus was added. This addition condition may be obtained by referring to the step of FIG. By this step, low-concentration impurity regions 33 and 34 were formed, and a channel formation region 35 was defined. (Fig. 12 (A))

Next, after removing the resist mask 32, second conductive layers 36 and 37 were formed.
By this process, the NTFT main gate wiring 38 was formed. (Fig. 12B)
)

Next, resist masks 315 to 318 were formed, and a boron addition step was performed.
The addition conditions may be determined with reference to the step of FIG. When the phosphorus and boron addition steps were completed in this way, the impurity element added was activated by the same means as in Example 1, and the state shown in FIG. 12C was obtained.

  Next, after removing the resist masks 315 to 318, resist masks 324 to 327 were formed again by a backside exposure method, and phosphorus was added. The addition condition may be referred to the step of FIG.

  Through this process, the NTFT source region 39, drain region 40, and low-concentration impurity region (LDD region) 41 were formed. (Fig. 12D)

  At this time, the LDD region 41 has a length of a portion overlapping with the gate electrode 38 of 0.1 to 3.5 μm (typically 0.1 to 0.5 μm, preferably 0.1 to 0. 3 μm), and the length of the portion not overlapping with the gate electrode 38 may be 0.5 to 3.5 μm (typically 1.5 to 2.5 μm).

  Thereafter, through the same steps as in the first embodiment, the first interlayer insulating film 108, the source wirings 109 and 110, and the drain wiring 111 are formed, thereby completing the CMOS circuit having the structure shown in FIG. .

Note that although a manufacturing process of a CMOS circuit has been described as an example in this embodiment, the structure of FIG. 11B can be obtained in a substantially similar manufacturing process in a pixel matrix circuit.
Therefore, the description here is omitted.

  Further, the structure of this embodiment can be applied to the AM-LCD of Embodiment 3, and can be freely combined with the configurations shown in Embodiments 4 to 6.

  In the step of FIG. 3D in Example 1, after forming the resist masks 324 to 327 by the backside exposure method, the second insulating layer 306 is removed by etching, and phosphorus is added to the exposed active layer. It is valid.

  By doing so, the acceleration voltage at the time of adding phosphorus can be reduced to about 10 keV, and the burden on the doping apparatus can be reduced. Further, the throughput can be greatly improved. This also applies to the process shown in FIG.

  The configuration of the present embodiment can be applied to the AM-LCD of the third embodiment, and can be freely combined with the configurations shown in the fourth to seventh embodiments.

  In this embodiment, a structure for reducing the off-current of NTFT in a CMOS circuit used for a driver circuit will be described with reference to FIG.

  In FIG. 13, the LDD region 51 of the NTFT can be distinguished from a portion that does not substantially overlap the first wiring 102a. Accordingly, when a gate voltage is applied to the first wiring 102a, the NTFT of FIG. 13 has a structure having an LDD region that does not overlap the gate electrode outside the LDD region that overlaps the gate electrode.

  As described in the eighth embodiment, such a structure has an effect of preventing deterioration of on-current, which is an advantage of the GOLD structure, and obtains electrical characteristics that suppress an increase in off-current, which is a disadvantage of the GOLD structure. be able to. Therefore, it is possible to realize a CMOS circuit having very excellent reliability.

  Although the case of a CMOS circuit has been described here as an example, the structure of this embodiment may be applied to a pixel matrix circuit.

  Further, in order to realize the structure of this embodiment, the back exposure method may not be used in the process shown in FIG. That is, the structure of this embodiment can be easily obtained by providing a resist mask having a width wider than that of the first wiring by normal mask alignment and then performing a step of adding phosphorus.

  The length of the LDD region (the length of the portion not overlapping with the gate electrode) may be referred to the range shown in the eighth embodiment.

  The configuration of the present embodiment can be applied to the AM-LCD of the third embodiment, and can be freely combined with the configurations shown in the fourth to seventh embodiments.

  In this embodiment, a case where means other than laser crystallization is used to form the active layer shown in Embodiment 1 or Embodiment 2 will be described.

  Specifically, an example in which a crystalline semiconductor film used as an active layer is formed by a thermal crystallization method using a catalytic element is shown. When using a catalytic element, use the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652 (corresponding to US Application No. 08 / 329,644 or US Application No. 08 / 430,623) and Japanese Patent Application Laid-Open No. 8-78329. Is desirable. In particular, nickel is suitable as the catalyst element.

  Note that the configuration of this embodiment can be freely combined with all the configurations of Embodiments 1 to 9.

  This example shows an example in which the thermal crystallization method shown in Example 10 is used as a method for forming the active layer, and the step of removing the catalyst element used therein from the crystalline semiconductor film is performed. In this embodiment, the method is described in JP-A-10-135468 (corresponding to US application No. 08 / 951,193) or JP-A-10-135469 (corresponding to US application No. 08 / 951,819). Technology is used.

The technique described in this publication is a technique for removing a catalytic element used for crystallization of an amorphous semiconductor film using a halogen gettering action after crystallization. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ .

  The configuration of this embodiment can be freely combined with all the configurations of Embodiments 1 to 10.

  This example shows an example in which the thermal crystallization method shown in Example 10 is used as a method for forming the active layer, and the step of removing the catalyst element used therein from the crystalline semiconductor film is performed. In this embodiment, the technique described in Japanese Patent Application Laid-Open No. 10-270363 (corresponding to US Application No. 09 / 050,182) is used as the method.

The technique described in the publication is a technique for removing a catalytic element used for crystallization of an amorphous semiconductor film by using a gettering action of phosphorus after crystallization. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ .

  The configuration of this embodiment can be freely combined with all the configurations of Embodiments 1 to 10.

  In this example, another embodiment of the gettering process using phosphorus shown in Example 12 will be described. Since the basic steps are the same as those shown in FIG. 1, only the differences will be described.

First, the state of FIG. 3D was obtained according to the steps of Example 1. FIG. 14A shows a state in which the resist masks 324 to 327 are removed from the state of FIG.
However, the thermal crystallization technique shown in Example 10 is used to form the semiconductor layer that becomes the active layer of the TFT.

At this time, the source region 328 and drain region 329 of the NTFT and the source region 331 and drain region 332 of the PTFT are 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ (preferably 5 × 10 ²⁰ atoms / cm ³ ). Contains phosphorus at a concentration of.

In this embodiment, in this state, a heat treatment process is performed in a nitrogen atmosphere at 500 to 800 ° C. for 1 to 24 hours, for example, 600 ° C. for 12 hours. By this step, the added impurity element imparting n-type and p-type could be activated. Further, the catalyst element (nickel in this embodiment) remaining after the crystallization process moves in the direction of the arrow, and gettering (capturing) is performed in the region by the action of phosphorus contained in the source region and the drain region. )We were able to. As a result, nickel could be reduced to 1 × 10 ¹⁷ atoms / cm ³ or less from the channel formation region.

  When the process of FIG. 14B is completed, a CMOS circuit as shown in FIG. 3E can be manufactured if the subsequent processes follow the process of Embodiment 1. Of course, it goes without saying that the same applies to the pixel matrix circuit.

  The configuration of this embodiment can be freely combined with all the configurations of Embodiments 1 to 10.

  The TFT structure of the present invention can be applied not only to an electro-optical device such as an AM-LCD but also to any semiconductor circuit. That is, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor, or may be applied from a signal processing circuit such as a D / A converter to a high-frequency circuit for a portable device (mobile phone, PHS, mobile computer). .

  Furthermore, it is possible to realize a semiconductor device having a three-dimensional structure in which an interlayer insulating film is formed on a conventional MOSFET and a semiconductor circuit is fabricated thereon using the present invention. Thus, the present invention can be applied to all semiconductor devices in which LSI is currently used. That is, the present invention may be applied to SOI structures (TFT structures using a single crystal semiconductor thin film) such as SIMOX, Smart-Cut (registered trademark of SOITEC) and ELTRAN (registered trademark of Canon Inc.).

  Further, the semiconductor circuit of the present embodiment can be realized by using any combination of the first, second, and fourth to thirteenth embodiments.

  The CMOS circuit and the pixel matrix circuit formed by implementing the present invention can be applied to various electro-optical devices and semiconductor circuits. That is, the present invention can be implemented in all electronic devices in which these electro-optical devices and semiconductor circuits are incorporated as parts.

  Such electronic devices include video cameras, digital cameras, projectors, projection TVs, head mounted displays (goggles type displays), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) and the like. Can be mentioned. An example of these is shown in FIG.

  FIG. 15A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, operation switches 2005, and an antenna 2006. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and other signal control circuits.

  FIG. 15B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the voice input unit 2103, and other signal control circuits.

  FIG. 15C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.

  FIG. 15D illustrates a goggle type display which includes a main body 2301, a display device 2302, and an arm portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.

  FIG. 15E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403 and other signal control circuits.

  FIG. 15F illustrates a front type projector which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to the display device 2502 and other signal control circuits.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic device of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-14.

The figure which shows the structure of a CMOS circuit. FIG. 6 is a diagram illustrating a structure of a pixel matrix circuit. 10A and 10B illustrate a manufacturing process of a CMOS circuit. 10A and 10B illustrate a manufacturing process of a pixel matrix circuit. 10A and 10B illustrate a manufacturing process of a pixel matrix circuit. The figure which shows the external appearance of AM-LCD. The figure which shows the block structure of AM-LCD. The figure which shows the structure of a CMOS circuit or a pixel matrix circuit. The figure which shows the structure of a pixel matrix circuit (especially storage capacity | capacitance). The figure which shows the structure of a CMOS circuit or a pixel matrix circuit. The figure which shows the structure of a CMOS circuit or a pixel matrix circuit. 10A and 10B illustrate a manufacturing process of a CMOS circuit. The figure which shows the structure of a CMOS circuit. 10A and 10B illustrate a manufacturing process of a CMOS circuit. FIG. 14 illustrates an example of an electronic device.

Claims (11)

A TFT structure in which an active layer is sandwiched between a first wiring and a second wiring via an insulating layer,
The active layer includes a low concentration impurity region in contact with the channel formation region,
The channel formation region overlaps the first wiring and the second wiring;
The semiconductor device according to claim 1, wherein the low concentration impurity region has a portion that overlaps with the first wiring and does not overlap with the second wiring. In claim 1,
The semiconductor device according to claim 1, wherein the low-concentration impurity region has a portion that does not overlap with either the first wiring or the second wiring. In claim 1 or claim 2,
The low-concentration impurity region has a portion overlapping with the first wiring and the second wiring. A semiconductor device having a first N-channel TFT and a second N-channel TFT on the same substrate,
The first N-channel TFT and the second N-channel TFT have a structure in which an active layer is sandwiched between a first wiring and a second wiring through an insulating layer,
The active layer includes a low concentration impurity region in contact with the channel formation region,
The channel formation region overlaps the first wiring and the second wiring;
The low-concentration impurity region has a portion that overlaps the first wiring and does not overlap the second wiring;
The first wiring of the first N-channel TFT is held at a fixed potential or a floating potential,
The semiconductor device, wherein the first wiring of the second N-channel TFT is held at the same potential as the second wiring of the second N-channel TFT. In claim 4,
The semiconductor device according to claim 1, wherein the fixed potential is a ground potential or a source power supply potential. In any one of Claims 1 thru | or 5,
The second wiring is routed to the power supply unit,
The second wiring other than the power supply unit is composed of a laminated structure of a first conductive layer and a second conductive layer,
The second wiring of the power supply unit is formed on the first conductive layer, the third conductive layer formed on the first conductive layer, and the third conductive layer so as to cover the third conductive layer. A semiconductor device comprising: the second conductive layer. In claim 6,
The semiconductor device according to claim 1, wherein the third conductive layer has a lower resistance value than the first conductive layer or the second conductive layer. In claim 6 or claim 7,
The first conductive layer or the second conductive layer is a conductive film whose main component is an element selected from tantalum (Ta), titanium (Ti), tungsten (W), molybdenum (Mo), or silicon (Si). A semiconductor device comprising an alloy film or a silicide film in which the above elements are combined. In any one of Claims 6 to 8,
The semiconductor device, wherein the third conductive layer is a conductive film containing aluminum or copper as a main component.   10. The semiconductor device according to claim 1, wherein the semiconductor device is an active matrix liquid crystal display or an active matrix EL display.   The semiconductor device according to any one of claims 1 to 9 is a video camera, a digital camera, a projector, a projection TV, a goggle type display, a car navigation, a personal computer, or a portable information terminal. A semiconductor device.

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