JP2008010694A - Substrate for mounting semiconductor, manufacturing method thereof, and mounting structure - Google Patents

Substrate for mounting semiconductor, manufacturing method thereof, and mounting structure Download PDF

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Publication number
JP2008010694A
JP2008010694A JP2006180660A JP2006180660A JP2008010694A JP 2008010694 A JP2008010694 A JP 2008010694A JP 2006180660 A JP2006180660 A JP 2006180660A JP 2006180660 A JP2006180660 A JP 2006180660A JP 2008010694 A JP2008010694 A JP 2008010694A
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Prior art keywords
substrate
solder
electrode
mounting
semiconductor component
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Japanese (ja)
Inventor
Takafumi Kashiwagi
隆文 柏木
Yuji Yagi
優治 八木
Tatsuo Sasaoka
達雄 笹岡
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2006180660A priority Critical patent/JP2008010694A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for mounting a semiconductor and a mounting structure therefor which improve the yield of flip chip mounting of a semiconductor component and which can yield high reliability. <P>SOLUTION: The substrate for mounting semiconductor is provided with a via electrode 8 for interlayer connection in the substrate 3 under an electrode land 4, and a projection 9 is formed on the surface of the electrode land 4 by the via electrode 8. The variety of heights of solder bumps 7 of the semiconductor component 1 is absorbed, mounting with a high yield is available, and, on the other hand, the amount of used solder can be reduced, thereby permitting the prevention of outflow of the solder upon remelting of the same. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体部品を実装する回路基板および実装構造に関するものである。   The present invention relates to a circuit board for mounting a semiconductor component and a mounting structure.

近年電子機器には、携帯機器等に代表される薄型化、小型化の要求が高まっており、それらに使用される電子部品の実装構造に対しても低背化要求が強い。   In recent years, demands for thinning and miniaturization represented by portable devices and the like have been increasing for electronic devices, and there is a strong demand for lowering the mounting structure of electronic components used for them.

そのため、使用される半導体部品は、リードを持つパッケージ形態ではなく、半導体部品を基板に向けて実装した、いわゆるフリップチップ実装と呼ばれる形態が使用される。   For this reason, the semiconductor component used is not a package having a lead, but a so-called flip chip mounting in which the semiconductor component is mounted on the substrate.

図4にフリップチップ実装構造の断面図を示す。半導体部品101の表面に設けられた電極102と、基板103上に形成された電極ランド104上のレジスト108の開口部105を、はんだ106で接続したものである。   FIG. 4 shows a cross-sectional view of the flip chip mounting structure. The electrode 102 provided on the surface of the semiconductor component 101 and the opening 105 of the resist 108 on the electrode land 104 formed on the substrate 103 are connected by solder 106.

一般に、半導体部品のはんだ接続によるフリップチップ実装工程は、図5に示すように行われる。   In general, a flip chip mounting process by solder connection of semiconductor components is performed as shown in FIG.

図5(a)に示すように、半導体部品101の接続用電極102表面には予めはんだバンプ107と呼ばれる、はんだからなる突起を設けておく。また、基板103上に形成された接続用電極ランド104において、はんだが所定の範囲にのみ濡れ広がるように、塗布されたはんだレジスト材108によって金属箔が部分的に露出した開口部105を形成しておく。   As shown in FIG. 5A, a protrusion made of solder called a solder bump 107 is provided in advance on the surface of the connection electrode 102 of the semiconductor component 101. In addition, in the connection electrode land 104 formed on the substrate 103, an opening 105 in which the metal foil is partially exposed is formed by the applied solder resist material 108 so that the solder spreads only in a predetermined range. Keep it.

次に、図5(b)に示すように半導体部品のはんだバンプ107を電極ランド104のレジスト開口部105と位置整合させて、配置する。   Next, as shown in FIG. 5B, the solder bumps 107 of the semiconductor component are arranged in alignment with the resist openings 105 of the electrode lands 104.

次に、図5(c)に示すように、基板および半導体部品を加熱し、はんだバンプ107を溶融させ、はんだを基板側の電極ランドの開口部105に濡れ広がらせて後、冷却凝固して接合が終了する。   Next, as shown in FIG. 5C, the substrate and the semiconductor component are heated, the solder bumps 107 are melted, and the solder is wet spread in the openings 105 of the electrode lands on the substrate side, and then cooled and solidified. Joining is completed.

さらに、落下衝撃等に対し耐久性を向上させるために、図5(d)に示すように、半導体部品101と基板103の間隙に補強樹脂109を注入硬化することが一般に行われる。   Further, in order to improve durability against a drop impact or the like, generally, a reinforcing resin 109 is injected and cured in a gap between the semiconductor component 101 and the substrate 103 as shown in FIG.

先行技術文献情報としては、例えば下記特許文献1が知られている。
特開平02−016756号公報
As prior art document information, for example, the following Patent Document 1 is known.
Japanese Patent Laid-Open No. 02-016756

上記のように半導体部品を基板実装する際に、はんだバンプの高さのばらつきによる実装不良が発生するという課題がある。この現象の発生原因を図6に示す。   As described above, when a semiconductor component is mounted on a substrate, there is a problem that a mounting failure occurs due to variations in the height of solder bumps. The cause of this phenomenon is shown in FIG.

図6(a)は、はんだバンプの高さにばらつきがある半導体部品101を、基板103に配置した状態であり、この場合、中央のはんだバンプ110の高さが低い場合である。   FIG. 6A shows a state in which the semiconductor component 101 having a variation in solder bump height is arranged on the substrate 103, and in this case, the height of the central solder bump 110 is low.

中央のはんだバンプ110は高さが低いため、基板上の電極ランドの開口部105から離れた位置にある。   Since the central solder bump 110 is low in height, it is located away from the opening 105 of the electrode land on the substrate.

この状態ではんだを溶融させた場合、基板電極ランドの開口部105の表面にほぼ接している両側のはんだバンプ111は基板電極ランドの開口部105の表面に濡れ広がり、結果的に高さが減少し、中央のバンプ110も基板電極ランドの開口部105の表面に接近する。   When the solder is melted in this state, the solder bumps 111 on both sides almost in contact with the surface of the opening 105 of the substrate electrode land spread out on the surface of the opening 105 of the substrate electrode land, resulting in a decrease in height. The central bump 110 also approaches the surface of the opening 105 of the substrate electrode land.

バンプ高さのばらつきが大きい場合は、高さが低い中央のバンプ110が基板電極ランドの開口部105の表面に接することができなくなり、凝固後も図6(b)に示すように浮いた状態となり、接続不良となってしまう。   When the bump height variation is large, the central bump 110 having a low height cannot be brought into contact with the surface of the opening 105 of the substrate electrode land, and remains floating as shown in FIG. As a result, connection failure occurs.

また、一般的に、温度変化があったとき半導体部品と基板間の熱膨張係数の差から生じる熱応力に対し、半導体部品と基板との接続終了後のはんだの高さは高い方が熱応力に対する歪が少なくなり、信頼性が高い。   Also, in general, when the temperature changes, the higher the solder height after the connection between the semiconductor component and the substrate is, the higher the thermal stress is due to the difference in thermal expansion coefficient between the semiconductor component and the substrate. Less distortion and high reliability.

しかしながら、はんだ高さを高くするために、はんだ量を増大させると、別の課題が発生する。   However, when the amount of solder is increased in order to increase the solder height, another problem occurs.

すなわち、基板にフリップチップ実装された半導体部品は、最終の電子機器製造者において他の部品と共に回路基板へ実装されるが、この実装は一般にはんだリフロー方式で行われるために、半導体部品と基板を接続したはんだも再度溶融することになる。   That is, a semiconductor component flip-chip mounted on a substrate is mounted on a circuit board together with other components in the final electronic device manufacturer. Since this mounting is generally performed by a solder reflow method, the semiconductor component and the substrate are mounted. The connected solder will also melt again.

はんだは加熱されると熱膨張しようとするが、図7に示すように、はんだ112の周囲は補強樹脂109で囲まれているために、融点を超えて加熱されて液状となったはんだの内部圧力が高まり、基板と半導体部品間に充填された樹脂との界面を剥離させて流出し、接続不良となってしまう現象が生じる。113は流出したはんだである。この現象は、半導体部品と基板を接続しているはんだの量が多いほど生じやすい。   The solder tends to expand when heated, but as shown in FIG. 7, since the periphery of the solder 112 is surrounded by the reinforcing resin 109, the solder is heated to a temperature exceeding the melting point and becomes liquid. As pressure increases, the interface between the substrate and the resin filled between the semiconductor components is peeled off and flows out, resulting in a connection failure. Reference numeral 113 denotes the leaked solder. This phenomenon is more likely to occur as the amount of solder connecting the semiconductor component and the substrate increases.

前記課題を解決するために、本発明の半導体実装用基板は、実装される半導体部品上の接続電極と対応した配置の電極を有する基板であり、前記電極下に層間接続用ビア電極が設けられ、このビア電極によって電極表面に突起が形成されたものである。   In order to solve the above problems, a semiconductor mounting substrate of the present invention is a substrate having electrodes arranged corresponding to connection electrodes on a semiconductor component to be mounted, and an interlayer connection via electrode is provided under the electrodes. A projection is formed on the electrode surface by the via electrode.

本発明の半導体実装用基板は、実装される半導体部品に設けられたはんだバンプに高さばらつきがある場合も、基板電極ランドの表面に設けた突起がバンプ高さばらつきを吸収し、接続不良が生じにくい。   In the semiconductor mounting substrate of the present invention, even when the solder bump provided on the semiconductor component to be mounted has a height variation, the protrusion provided on the surface of the substrate electrode land absorbs the bump height variation, and the connection failure is caused. Hard to occur.

また、基板電極ランドの表面にある突起の効果により、半導体部品と基板間の距離を保つのに必要なはんだ量が少なくなり、はんだが再溶融した場合に、溶融はんだの流出が生じにくい。   Further, due to the effect of the protrusions on the surface of the substrate electrode land, the amount of solder necessary to maintain the distance between the semiconductor component and the substrate is reduced, and when the solder is remelted, the molten solder does not easily flow out.

また、基板上の電極ランド表面に突起を形成するにおいて、電極下に設けた層間接続用ビア電極によって電極を形成する金属箔が突起状に成形される方法であるので、基板製造工程において何ら工程が追加されるものでなく、容易に高信頼性の実装構造を提供できるという効果を有するものである。   In addition, in forming a projection on the electrode land surface on the substrate, the metal foil for forming the electrode is formed into a projection shape by the interlayer connection via electrode provided under the electrode. Is not added, and has an effect that a highly reliable mounting structure can be easily provided.

(実施の形態1)
以下、本発明の実施の形態1について、図面を参照しながら説明する。
(Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings.

図1は本発明の実施の形態1の一例である半導体実装用基板と半導体部品の実装構造を説明するための断面図である。   FIG. 1 is a cross-sectional view for explaining a mounting structure of a semiconductor mounting substrate and a semiconductor component, which is an example of the first embodiment of the present invention.

本実施の形態において、図1に示すように、半導体部品1の表面に設けられた接続用電極2と、基板3上に形成された電極ランド4に設けられたはんだレジスト5の開口部6とが、はんだ7によって接続された状態であり、電極ランド4に設けられたはんだレジスト5の開口部6には、基板の層間接続用のビア電極8が押し上げて形成された突起9が存在する。   In the present embodiment, as shown in FIG. 1, the connection electrode 2 provided on the surface of the semiconductor component 1, the opening 6 of the solder resist 5 provided on the electrode land 4 formed on the substrate 3, and However, it is in a state of being connected by the solder 7, and in the opening 6 of the solder resist 5 provided on the electrode land 4, there is a protrusion 9 formed by pushing up the interlayer connection via electrode 8.

この構造を実現する方法を図面を用いて説明する。   A method for realizing this structure will be described with reference to the drawings.

図2は本発明の半導体実装用基板の製造工程を説明するための、工程を追った図である。   FIG. 2 is a diagram illustrating the steps for manufacturing the semiconductor mounting substrate of the present invention.

図2(a)は、絶縁性基板10に貫通孔11を設け、さらに貫通孔11にペースト状電極材12を充填した状態を示す。   FIG. 2A shows a state in which the through hole 11 is provided in the insulating substrate 10 and the paste electrode material 12 is filled in the through hole 11.

ペースト状電極材12は銅ペーストを用い、マスク印刷工法で貫通孔11に充填した。   The paste electrode material 12 was made of copper paste and filled in the through holes 11 by a mask printing method.

ペースト状電極材12は絶縁性基板10の表面から凸状に出た形状をなしており、これは印刷マスクの厚みを利用すれば容易に形成できる。   The paste electrode material 12 has a shape protruding from the surface of the insulating substrate 10 and can be easily formed by utilizing the thickness of the printing mask.

次に、図2(b)に示すように、絶縁性基板10の両面に金属箔、ここでは銅箔13を設置する。   Next, as shown in FIG. 2B, metal foil, here, copper foil 13 is installed on both surfaces of the insulating substrate 10.

次に、図2(c)に前記状態の絶縁性基板10および銅箔13を熱プレス装置(図示せず)に装着し、プレスした状態を示す。   Next, FIG. 2C shows a state where the insulating substrate 10 and the copper foil 13 in the above state are mounted on a hot press apparatus (not shown) and pressed.

本実施の形態において、上面に示す平板材14は柔軟性を有するシートであり、下面に示す平板材15は剛直なシートである。   In the present embodiment, the flat plate material 14 shown on the upper surface is a flexible sheet, and the flat plate material 15 shown on the lower surface is a rigid sheet.

たとえば、柔軟性を有する平板材14には合成ゴムやウレタン樹脂やシリコーン樹脂やフッ素樹脂等のシートを用いることができる。また、剛直な平板材15はステンレス等の金属材やセラミクス材等を用いることができる。これにより、平板材14側が柔軟性を有するためにペースト電極材12は、図2(c)のように平板材14側が盛り上がる状態で積層され、突起を形成する。   For example, a sheet of synthetic rubber, urethane resin, silicone resin, fluorine resin, or the like can be used for the flat plate member 14 having flexibility. The rigid flat plate 15 can be made of a metal material such as stainless steel or a ceramic material. Thus, since the flat plate material 14 side has flexibility, the paste electrode material 12 is laminated with the flat plate material 14 side raised as shown in FIG.

本発明において、前記絶縁性基板10に、半硬化状態のエポキシ樹脂を含むいわゆるプリプレグを用いると、接着材を用いることなく銅箔13を絶縁性基板10と接着することができる。   In the present invention, when a so-called prepreg containing a semi-cured epoxy resin is used for the insulating substrate 10, the copper foil 13 can be bonded to the insulating substrate 10 without using an adhesive.

前記プレス状態で絶縁性基板10およびペースト状電極材12を加熱硬化せしめて後、銅箔13を所定のパターンにエッチング加工し、さらにはんだレジスト5を所定のパターンに形成すると、図2(d)に示すような、電極ランド4に設けられたはんだレジスト5の開口部6に、基板3の層間接続用のビア電極8が銅箔を押し上げて形成した突起9が存在する基板が得られる。   When the insulating substrate 10 and the paste electrode material 12 are cured by heating in the pressed state, the copper foil 13 is etched into a predetermined pattern, and the solder resist 5 is formed into a predetermined pattern. Thus, a substrate is obtained in which the vias 8 for interlayer connection of the substrate 3 are formed with protrusions 9 formed by pushing up the copper foil in the openings 6 of the solder resist 5 provided on the electrode lands 4.

なお、本実施の形態は、図2(c)に示す平板材において、基板3の上面のみすなわち片側の平板材14が柔軟性を有するシートとしたが、基板3の両側の平板材14、15が柔軟性を有するシートであってもよい。基板3の両面に半導体部品を実装する場合、基板3の両面に突起9を有するビア電極8が必要となるため、図2(c)において、両側の平板材14,15は柔軟性を有するシートからなる構成が適用される。   In the present embodiment, in the flat plate material shown in FIG. 2C, only the upper surface of the substrate 3, that is, the flat plate material 14 on one side is a flexible sheet, but the flat plate materials 14 and 15 on both sides of the substrate 3. May be a flexible sheet. When mounting semiconductor components on both sides of the substrate 3, via electrodes 8 having protrusions 9 are required on both sides of the substrate 3. In FIG. 2C, the flat plate members 14 and 15 on both sides are flexible sheets. The configuration consisting of:

図2(d)で得られた基板を半導体実装用として用いることにより、半導体部品のはんだバンプに高さばらつきがある場合も歩留まり良く実装することが可能となる。この効果を図3を用いて説明する。   By using the substrate obtained in FIG. 2D for semiconductor mounting, it is possible to mount with high yield even when the solder bumps of the semiconductor component have height variations. This effect will be described with reference to FIG.

図3は、高さにばらつきがあるはんだバンプを有する半導体部品を、本発明の基板に実装する工程を順を追って説明するものである。   FIG. 3 illustrates the steps of mounting a semiconductor component having solder bumps with variations in height on the substrate of the present invention.

図3(a)は本発明の基板ランドの開口部6と、半導体部品1上のはんだバンプ16乃至18とを位置整合させて配置した状態を示す。ここで、はんだバンプに高さばらつきがあるため、はんだバンプ16と18は基板ランド部の突起9にほぼ接しているが、高さが低いはんだバンプ17は、接していない。   FIG. 3A shows a state in which the opening 6 of the substrate land of the present invention and the solder bumps 16 to 18 on the semiconductor component 1 are aligned and arranged. Here, since the solder bumps vary in height, the solder bumps 16 and 18 are substantially in contact with the protrusion 9 of the board land portion, but the solder bump 17 having a low height is not in contact.

なお、本実施の形態において、図3における基板3のビア電極8は片面に突起9を設けているが、両面に半導体部品を実装する場合は、ビア電極8は両面に突起9を設けている構成となる。   In this embodiment, the via electrode 8 of the substrate 3 in FIG. 3 is provided with the protrusions 9 on one side. However, when the semiconductor component is mounted on both sides, the via electrode 8 is provided with the protrusions 9 on both sides. It becomes composition.

図3(b)は上記状態でリフロー炉に入れてはんだが溶融し始めた時点の様子を図示するものである。はんだが溶融し、はんだバンプ16と18は基板ランド部の突起9に濡れ始めて、半導体部品1と基板3の間隙は狭くなってくる。   FIG. 3B illustrates the state at the time when the solder starts to melt in the above-described state. As the solder melts, the solder bumps 16 and 18 begin to get wet with the protrusions 9 on the board land, and the gap between the semiconductor component 1 and the board 3 becomes narrower.

この時、基板ランド部の突起9の側面にはんだが濡れ広がることにより、前記突起9が無い場合に比べて半導体部品1と基板3の間隙を格段に大きくとることができるとともに、高さが低いはんだバンプ17も確実に基板ランド部の突起9に接するようになる。   At this time, the solder wets and spreads on the side surfaces of the protrusions 9 of the board land portion, so that the gap between the semiconductor component 1 and the substrate 3 can be made significantly larger than that without the protrusions 9 and the height is low. The solder bumps 17 are also surely in contact with the protrusions 9 on the board land portion.

はんだバンプ17と基板ランド部の突起9が接すると、溶融したはんだ7は急激に基板ランド部に濡れ広がり始めて、結果的には図3(c)に示すように、全てのはんだバンプ16〜18が基板ランドの開口部6に広がり、確実な接続が得られる。   When the solder bumps 17 and the projections 9 on the board land portion come into contact with each other, the melted solder 7 starts to spread rapidly on the board land portions, and as a result, as shown in FIG. Spreads to the opening 6 of the substrate land, and a reliable connection is obtained.

また、図3(c)に示すように、実装終了後は、はんだ7の中に基板ランド部の突起9が侵入した状態となり、はんだ7の量が少なくてもはんだ7の高さが保持できるため、はんだ7の高さが同じ場合は、基板ランド部の突起9が無い場合に比較して少ないはんだ量で実装できる。   Further, as shown in FIG. 3C, after the mounting is completed, the protrusion 9 of the board land portion enters the solder 7, and the height of the solder 7 can be maintained even if the amount of the solder 7 is small. Therefore, when the height of the solder 7 is the same, it can be mounted with a smaller amount of solder than when there is no projection 9 on the board land portion.

この結果、はんだ量を増大することなく基板3と半導体部品1の間の距離を拡大することができ、信頼性を向上させることができると共に、はんだ量が少ないため、再度はんだが溶融した時のはんだ流出を防止することができるという効果が生じる。   As a result, the distance between the substrate 3 and the semiconductor component 1 can be increased without increasing the amount of solder, the reliability can be improved, and the amount of solder is small, so that when the solder is melted again The effect that solder outflow can be prevented occurs.

本発明の半導体実装用基板および半導体実装構造は、半導体部品を歩留まり良くはんだ実装でき、さらに、はんだの再溶融にも耐えられる。高信頼性が得られるものであり、小型電子機器用基板および実装構造として有用である。   The substrate for semiconductor mounting and the semiconductor mounting structure of the present invention can mount semiconductor components with high yield and can withstand remelting of solder. High reliability is obtained, and it is useful as a substrate for small electronic devices and a mounting structure.

本発明の実施の形態1における半導体部品実装部の断面図Sectional drawing of the semiconductor component mounting part in Embodiment 1 of this invention 本発明の実施の形態1における半導体部品実装用基板の工程説明図Process explanatory drawing of the semiconductor component mounting board | substrate in Embodiment 1 of this invention 本発明の実施の形態1における半導体部品実装工程説明図Semiconductor component mounting process explanatory drawing in Embodiment 1 of this invention 従来の半導体部品実装部の断面図Sectional view of conventional semiconductor component mounting part 従来の半導体部品実装工程説明図Illustration of conventional semiconductor component mounting process 従来の半導体部品実装工程説明図Illustration of conventional semiconductor component mounting process 従来の実装構造の課題を説明するための断面図Sectional drawing for demonstrating the subject of the conventional mounting structure

符号の説明Explanation of symbols

1 半導体部品
2 接続用電極
3 基板
4 電極ランド
5 はんだレジスト
6 開口部
7 はんだ
8 ビア電極
9 突起
10 絶縁性基板
11 貫通孔
12 ペースト状電極材
13 銅箔
14 平板材
15 平板材
16、17、18 はんだバンプ
DESCRIPTION OF SYMBOLS 1 Semiconductor component 2 Connection electrode 3 Board | substrate 4 Electrode land 5 Solder resist 6 Opening part 7 Solder 8 Via electrode 9 Protrusion 10 Insulating board 11 Through-hole 12 Paste electrode material 13 Copper foil 14 Flat plate material 15 Flat plate material 16, 17, 18 Solder bump

Claims (4)

実装される半導体部品上の接続電極に対応した配置の電極ランドを有する基板であり、前記電極ランド下に前記基板における層間接続用ビア電極が設けられ、このビア電極によって電極ランド表面に突起が形成された半導体実装用基板。 A substrate having an electrode land arranged corresponding to a connection electrode on a semiconductor component to be mounted, and an interlayer connection via electrode in the substrate is provided under the electrode land, and a projection is formed on the surface of the electrode land by the via electrode. Substrate for semiconductor mounting. 前記基板上の電極ランドと半導体部品上の接続電極がはんだによって接続された半導体実装構造。 A semiconductor mounting structure in which an electrode land on the substrate and a connection electrode on a semiconductor component are connected by solder. 絶縁性基板に貫通孔を設ける工程と、この貫通孔に絶縁性基板の表面から凸状に出た形状でペースト状電極材料を充填する工程と、この絶縁性基板の両面に金属箔を押圧しながら接着すると共にペースト状電極材料を硬化させる工程からなる半導体実装用基板の製造方法。 A step of providing a through hole in the insulating substrate, a step of filling the through hole with a paste electrode material in a shape protruding from the surface of the insulating substrate, and pressing a metal foil on both surfaces of the insulating substrate. The manufacturing method of the board | substrate for semiconductor mounting which consists of the process which adhere | attaches while hardening a paste-form electrode material. 前記絶縁性基板の両面に金属箔を押圧しながら接着する工程において、金属箔を押圧する装置における前記両面の金属箔と接する面の、少なくとも片側が柔軟な部材であることを特徴とする半導体実装用基板の製造方法。 In the step of adhering while pressing the metal foil to both surfaces of the insulating substrate, at least one side of the surface in contact with the metal foil on the both surfaces in the apparatus for pressing the metal foil is a flexible member, Manufacturing method for industrial use.
JP2006180660A 2006-06-30 2006-06-30 Substrate for mounting semiconductor, manufacturing method thereof, and mounting structure Pending JP2008010694A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11862586B2 (en) 2021-06-16 2024-01-02 Kioxia Corporation Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11862586B2 (en) 2021-06-16 2024-01-02 Kioxia Corporation Semiconductor device and method of manufacturing the same

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