JP2008010463A - Process for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variation of threshold in a nonvolatile memory module having first and second field effect transistors adjacent to each other. <P>SOLUTION: A first gate 12 is formed by patterning a polysilicon film deposited on the major surface of a substrate 1. A spacer 14 is then formed on the sidewall of the first gate 12 by etching back a silicon oxide film deposited to cover the first gate 12, and the surface of the substrate 1 is exposed. Subsequently, radical oxidation is carried out on the exposed surface of the substrate 1. Thereafter, a second gate 23 is formed to ride on the first gate 12 by patterning the polysilicon film deposited to cover the first gate 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to the manufacture of a nonvolatile memory having first and second field effect transistors adjacent to each other.

  Electrically rewritable non-volatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory) and flash memory can be rewritten on-board, which can shorten development time and improve development efficiency. In addition, the application is expanding to various applications such as small volume, high-mix production, tuning by destination, and program update after shipment. In particular, in recent years, there is a great need for a microcomputer incorporating an MPU (Micro Processing Unit) and an EEPROM (or flash memory).

In such a nonvolatile memory, information is stored depending on the presence or absence of charge in a charge storage layer (charge storage layer), and a MNOS (Metal Nitride) having a nitride film (such as Si ₃ N ₄ ) as a charge storage layer as its structure. Oxide Semiconductor) structure or MONOS (Metal Oxide Nitride Oxide Semiconductor) structure. In this case, the charge that contributes to data storage is accumulated in the discrete trap of the nitride film, which is an insulator. Therefore, even if a defect occurs in some part of the oxide film surrounding the accumulation node and an abnormal leak occurs, the charge Since all the charges in the accumulation layer are not lost, the reliability of data retention can be improved.

  As a configuration of the memory cell, a memory cell having a single transistor structure has been proposed. As a writing / erasing method, writing is performed by whole surface FN (Fowler Nordheim) tunneling injection from a semiconductor substrate, erasing by FN tunneling current to the semiconductor substrate, writing by hot electron injection, semiconductor substrate or source, drain A method of performing erasing by FN tunneling current to the region has been proposed. On the other hand, since the single transistor cell structure is more susceptible to disturbance than the EEPROM cell structure, a two-transistor split-gate memory cell structure provided with a control gate electrode has also been proposed.

Japanese Patent Laying-Open No. 2004-303918 (Patent Document 1) has first and second field effect transistors adjacent to each other as a split gate type memory cell structure, and the first gate electrode of the first field effect transistor. A structure is disclosed in which a part of the second gate electrode of the second field effect transistor is overlaid.
JP 2004-303918 A

  The present inventors have first and second field effect transistors adjacent to each other as disclosed in Patent Document 1, and the second field effect transistor second is disposed on the first gate electrode of the first field effect transistor. We are investigating a manufacturing technique of a semiconductor device including a nonvolatile memory having a structure in which a part of a gate electrode is mounted.

  FIG. 14 shows a memory cell MCx that the present inventors are examining. FIG. 15 shows a cross section of the memory gate MGx of FIG. The MOSFET having the memory gate MGx and the MOSFET having the control gate CGx are adjacent to each other, and a part of the control gate CGx rides on the memory gate MGx. A method for manufacturing the memory cell MCx will be outlined.

  First, after forming the first n-type semiconductor region 6a and the second n-type semiconductor region 6b in a deep region from the surface of the substrate 1, the p-type well 7 is formed. Next, the silicon oxide film 8, the silicon nitride film 9a, and the charge storage layer 9 made of the silicon oxynitride film 9b are formed on the main surface of the substrate 1 by thermal oxidation, and the conductive polysilicon film 10 and insulating film 11 are formed. Then, a memory gate MGx is formed by patterning.

  Next, a silicon oxide film is deposited on the entire surface of the semiconductor substrate 1 so as to cover the memory gate MGx, and then etched back by anisotropic dry etching to form spacers 14 on both side walls of the memory gate MGx. In other cases, the surface of the semiconductor substrate 1 is exposed. Next, the low concentration n-type semiconductor region 13 is formed on one side of the memory gate MGx.

  Next, in order to recover the damage received by the dry etching, sacrificial oxidation is performed on the exposed surface of the substrate 1 to form a silicon oxide film 15 of about 6 nm, for example, as shown in FIG. As the sacrificial oxidation, the present inventors perform wet oxidation. Specifically, the oxidation is performed at about 850 ° C. for about 20 minutes.

  Next, after removing the silicon oxide film 15, a gate insulating film 20 is formed on the semiconductor substrate 1, and a conductive polysilicon film 21 is formed and patterned so as to cover the memory gate MGx. Forms a control gate CGx on the memory gate MGx.

  Next, a low-concentration n-type semiconductor region 24 is formed on one side of the control gate CGx, a silicon oxide film is deposited on the entire surface of the semiconductor substrate 1, and then etched back by anisotropic dry etching. Spacers 29 are formed on both side walls of the CGx, and otherwise the surface of the semiconductor substrate 1 is exposed. Next, the high concentration n-type semiconductor region 30 is formed on one side of each of the memory gate MGx and the control gate CGx, and the silicide layer 35 is formed, thereby completing the memory cell MCx.

  However, in this memory cell MCx, a margin defect has occurred in memory cell characteristics such as erroneous writing / erase, for example. Therefore, the present inventors conducted cross-sectional observation of the memory cell MCx, and as shown in FIGS. 15A and 15B, sacrifices performed for removing the substrate 1 damage by etching back the spacer 14 formation. In the oxidation, a silicon oxide film 15a, which is a bird's beak, is formed under the ends of the spacer 14 and the memory gate MG, and a silicon oxide film 15b is formed on the side surface of the polysilicon film 10. Therefore, the present inventors have determined that the amount of the silicon oxide film 15a that becomes a bird's beak at the end of the memory gate MGx depends on the film thickness of the sacrificial oxidation performed for removing damage to the substrate 1 by etching back the spacer 14 formation. It has been found that the memory cell characteristics are affected by the variation and the shape of the memory gate MGx depending on the amount of the silicon oxide film 15b. As a result, the threshold distribution (variation) in the module after erasure increases due to the erasure characteristic variation in the memory module (memory array), which may contribute to a marginal defect.

  An object of the present invention is to provide a technique capable of reducing threshold variations in a module of a nonvolatile memory having first and second field effect transistors adjacent to each other.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the semiconductor device manufacturing technique according to the present invention, first the first gate of the first field effect transistor is formed by patterning the first electrode material film deposited on the main surface of the semiconductor substrate. Next, by etching back the first insulating film deposited so as to cover the first gate, a first spacer is formed on the side wall of the first gate, and the surface of the semiconductor substrate is exposed. Next, radical oxidation is performed on the exposed surface of the semiconductor substrate. Next, the electrode material film deposited so as to cover the first gate is patterned to form the second gate of the second field effect transistor so that a part of the electrode material film runs on the first gate.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the semiconductor device manufacturing technique of the present invention, it is possible to reduce threshold variation in a module of a nonvolatile memory.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The semiconductor device shown in the first embodiment of the present invention has first and second field effect transistors (for example, MOSFETs: Metal Oxide Semiconductor Field Effect Transistors) adjacent to each other on the first gate electrode of the first field effect transistor. And a non-volatile memory having a structure in which a part of the second gate electrode of the second field effect transistor is mounted. A semiconductor device provided with such a non-volatile memory is used for an IC (Integrated Circuit) card (memory card), for example.

  1 to 11 show the main part of the semiconductor device during the manufacturing process according to the embodiment of the present invention. The main part includes a memory cell part, a low-voltage MOS part, a high-voltage MOS part, and a capacitor part. It is shown. For example, as shown in FIG. 11, memory cells MC1 and MC2 of the non-volatile memory are formed in the memory cell portion, and a low breakdown voltage p-channel MOSFET (Q1) and an n-channel MOSFET (Q2) are formed in the low-voltage MOS portion. ), A high breakdown voltage p-channel MOSFET (Q3) and an n-channel MOSFET (Q4) are formed in the high-voltage MOS portion, and a capacitive element MIM is formed in the capacitor portion.

  First, as shown in FIG. 1, a surface oxide film 2 is formed on a main surface (element formation surface) of a semiconductor substrate (hereinafter abbreviated as “substrate”) 1 made of p-type silicon (Si) single crystal, for example. After the silicon film 3 is formed, the silicon nitride film 3 and the surface oxide film 2 in the element isolation formation region are removed by a photolithography technique and an etching technique, and a groove 4 is formed in the substrate 1 in the element isolation formation area by an etching technique. .

  Subsequently, after the surface of the substrate 1 exposed by forming the grooves 4 is oxidized, a silicon oxide film is deposited on the substrate 1 so as to embed the grooves 4, and the surface is polished. As shown in FIG. 2, an element isolation 5 made of the silicon oxide film is formed. Note that after the element isolation trench 5 is formed, the silicon nitride film 3 and the surface oxide film 2 are removed.

  Subsequently, as shown in FIG. 3, after a first n-type semiconductor region 6a and a second n-type semiconductor region 6b are formed in a deep region from the surface of the substrate 1 by an ion implantation technique, a p-type is formed in a predetermined region by the ion implantation technique. Well 7 is formed. Next, a silicon oxide film 8 is formed on the main surface of the substrate 1 by thermal oxidation, and a charge storage layer 9 made of a silicon nitride film and a silicon oxynitride film is formed on the silicon oxide film 8 by a CVD technique. Next, a polysilicon film 10 as an electrode material film is formed on the charge storage layer 9 by the CVD technique, and an n-type impurity (for example, phosphorus) is implanted into the polysilicon film 10 by an ion implantation technique to form the polysilicon film 10. After ensuring the conductivity, an insulating film 11 is deposited on the polysilicon film 10. Here, after the polysilicon film 10 is formed, an n-type impurity is implanted into the polysilicon film 10 by using an ion implantation technique. However, when the polysilicon film 10 is formed, the n-type impurity may be added. good.

  Subsequently, the insulating film 11 in a region for forming a first gate to be described later is left by photolithography technique and etching technique, the polysilicon film 10 is patterned using the insulating film 11 as a mask, and the charge storage layer 9 and silicon oxide are further patterned. The film 8 is removed and a first gate 12 is formed as shown in FIG. Here, the first gate 12 of the memory cell portion becomes the memory gate MG. Next, a low concentration n-type semiconductor region 13 is formed on one side of the memory gate MG on the substrate 1 of the memory cell portion by photolithography and ion implantation techniques.

  Subsequently, after depositing a silicon oxide film, which is an insulating film, over the entire surface of the substrate 1 so as to cover the memory gate MG, this is etched back by anisotropic dry etching, as shown in FIG. Spacers 14 are formed on both side walls of one gate 12. That is, the silicon oxide film is left on both side walls of the first gate, and otherwise the surface of the substrate 1 is exposed.

  Next, in order to recover the damage received by dry etching, sacrificial oxidation is performed on the exposed surface of the substrate 1 to form a silicon oxide film 15 of about 6 nm, for example, as shown in FIG. In this embodiment, radical oxidation is performed as the sacrificial oxidation. Specifically, in a state where the substrate 1 is heated while being depressurized from the atmospheric pressure, oxidation is performed on the substrate 1 where hydrogen gas and oxygen gas are exposed at about 950 ° C. for about 1 minute, that is, ISSG (In-Situ Steam Generation). ) Oxidize. Note that the silicon oxide film 15 formed by sacrificial oxidation is removed by cleaning before forming the gate insulating film in the high-voltage MOS portion.

  As described above, in the first embodiment, by using ISSG oxidation as the sacrificial oxidation, as shown in FIG. 12B, the formation of the silicon oxide film 15a that is a bird's beak is formed under the end portions of the spacer 14 and the memory gate MG. Can be suppressed. As described with reference to FIG. 15, formation of the silicon oxide film 15a by wet oxidation at the end of the memory gate MG causes erroneous writing / erase. As described above, in the wet oxidation process, the oxide material reaches the end of the memory gate MG via the spacers 14 to advance the oxidation, whereas in the radical oxidation process, the oxide material reaches the end of the memory gate MG. Since it cannot be oxidized, the shape of the silicon oxide film 15a can be reduced without being oxidized. That is, by suppressing the formation of the silicon oxide film 15a below the end portions of the spacer 14 and the memory gate MG by ISSG oxidation, it is possible to prevent erroneous writing / erasing of the nonvolatile memory.

  Further, by using ISSG oxidation as sacrificial oxidation, the formation of the silicon oxide film 15b on the side surface of the polysilicon film 10 can be suppressed as shown in FIG. As described with reference to FIG. 15, the formation of the silicon oxide film 15b on the side surface of the polysilicon film 10 causes variation in the shape of the memory gate MG. As described above, in the wet oxidation process, the oxide material reaches the side wall of the memory gate MG via the spacer 14, and the oxidation progresses, whereas in the radical oxidation process, the oxide material reaches the side wall of the memory gate MG. Since it cannot be oxidized, the shape of the silicon oxide film 15b can be reduced without being oxidized. That is, by suppressing the formation of the silicon oxide film 15b on the side surface of the polysilicon film 10 by ISSG oxidation, it is possible to prevent the occurrence of variation in the shape of the miniaturized memory gate MG.

  Subsequently, as shown in FIG. 6, an n-type well 16 is formed in a predetermined region of the high-voltage system MOS portion, and an n-type well 17 and a p-type well 18 are formed in a predetermined region of the low-voltage system MOS portion by photolithography technique and ion implantation technique. Then, a gate insulating film 19 is formed on the substrate 1 of the high voltage MOS part by photolithography and thermal oxidation. Note that the silicon oxide film 15a is removed by cleaning before the gate insulating film 19 is formed.

  Subsequently, as shown in FIG. 7, a gate insulating film 20 is formed on the substrate 1 of the memory cell portion and the low-voltage MOS portion by photolithography technology and thermal oxidation, and then the first gate 12 is covered by CVD technology. A polysilicon film 21 as an electrode material film is deposited on the substrate 1. Next, in a region excluding a predetermined region (region of the n-type well 17) of the low-voltage MOS portion by photolithography technology and ion implantation technology, an n-type impurity is implanted into the polysilicon film 21 to form a polysilicon film. In a predetermined region of the low-voltage MOS portion, p-type impurities are implanted into the polysilicon film 21 to ensure the conductivity of the polysilicon film 21, and then on the polysilicon film 21. An insulating film 22 is deposited.

  Subsequently, by using a photolithography technique and an etching technique, an insulating film 22 in a region for forming a second gate described later is left, the polysilicon film 21 is patterned using the insulating film 22 as a mask, and the gate insulating films 19 and 20 are further formed. As a result, the second gate 23 is formed as shown in FIG. Here, the second gate 23 of the memory cell portion becomes the control gate CG. Note that in the manufacturing process described in this embodiment mode, a gate electrode formed first is a first gate, and a gate electrode formed next is a second gate.

  Subsequently, as shown in FIG. 9, the low concentration n-type semiconductor region 24 is formed in the p-type well 7 of the memory cell portion and the low concentration n-type is formed in the p-type well 18 of the low-voltage MOS portion by photolithography technique and ion implantation technique. A low-concentration n-type semiconductor region 26 is formed in the semiconductor region 25 and the p-type well 7 of the high-voltage MOS portion. Next, a low-concentration p-type semiconductor region 27 is formed in the n-type well 16 of the high-voltage MOS portion and a low-concentration p-type semiconductor region 28 is formed in the n-type well 17 of the low-voltage MOS portion by photolithography technology and ion implantation technology.

  Next, a silicon oxide film, which is an insulating film, is deposited on the entire surface of the substrate 1 so as to cover the first gate 12 and the second gate 23, and then etched back by anisotropic dry etching. Spacers 29 are formed on both side walls.

  Subsequently, as shown in FIG. 10, a high concentration n-type semiconductor region 30 is formed in the memory cell portion by a photolithography technique and an ion implantation technique, and a high concentration n-type semiconductor region 31 and a high concentration are formed in the low-voltage MOS portion. A p-type semiconductor region 33 is formed, and a high-concentration n-type semiconductor region 32 and a high-concentration p-type semiconductor region 34 are formed in the high-voltage MOS portion. These are formed in a self-aligned manner using the first gate 12, the spacer 14, the second gate 23 and the spacer 29 as a mask. Next, a silicide layer 35 such as cobalt silicide (CoSix) is formed on the surface of the substrate 1, the first gate 12 and the second gate 23 by a salicide (Salicide: Self Align silicide) technique.

  In this manner, the memory cells MC1 and MC2 are formed in the memory cell portion, and the low breakdown voltage p-channel MOSFET (Q1) and the low breakdown voltage n-channel MOSFET (Q2) are formed in the low-voltage MOS portion. A high breakdown voltage p-channel MOSFET (Q3) and a high breakdown voltage n-channel MOSFET (Q4) are formed in the portion, and a capacitive element MIM is formed in the capacitance portion.

  Subsequently, as shown in FIG. 11, the memory cells MC1, MC2, the low breakdown voltage p-channel MOSFET (Q1), the low breakdown voltage n-channel MOSFET (Q2), the high breakdown voltage p-channel MOSFET (Q3), and the high breakdown voltage n-channel. After forming the insulating film 36 so as to cover the type MOSFET (Q4), an interlayer insulating film 37 is formed on the substrate 1 by the CVD technique, and a contact hole 38 is formed in the interlayer insulating film 37. Next, a plug 39 is formed in the contact hole 38. The plug 39 is made of, for example, a thin barrier film made of a laminated film of titanium (Ti) and titanium nitride (TiN), and a relative film made of tungsten (W) or aluminum (Al) formed so as to be enclosed by the barrier film. And a thick conductor film. Thereafter, a first layer wiring M1 made of, for example, tungsten or aluminum (Al) is formed on the interlayer insulating film 37. Thereafter, a semiconductor device having a nonvolatile memory is manufactured through a normal semiconductor device manufacturing process.

  Here, writing, erasing, and reading operations when the memory cell MC1 according to the present embodiment is a selected memory cell will be described. Here, injecting electrons into the charge storage layer 9 is defined as “writing”, and injecting holes is defined as “erasing”. In the memory cell shown in the present embodiment, electrons are injected from the substrate 1 to the charge storage layer 9 to perform a write operation, and electrons are extracted from the charge storage layer 9 to the memory gate MG (polysilicon film 10) to perform an erase operation. Is what you do.

  First, in the data read operation, the source of the selected memory cell MC1 is, for example, about 1 V in the drain region (high-concentration n-type semiconductor region 30) of the selected memory cell MC1, and about 1.5 V, for example, in the control gate CG. For example, 0 (zero) V is applied to the region (high-concentration n-type semiconductor region 30), the memory gate MG, and the substrate 1 to turn on the selection MOSFET having the control gate CG. At this time, the threshold voltage of the memory MOSFET changes depending on the presence or absence of electrons in the charge storage layer 9 of the memory MOSFET having the memory gate MG, and a current flows between the drain region and the source region or does not flow. As a result, the stored data is read out.

  In the data erasing operation, the drain region, the source region, and the substrate 1 of the selected memory cell MC1 are, for example, 0 (zero) V, the control gate CG is, for example, about 1.5 V, and the memory gate MG is, for example, 14 V Apply degree. As a result, electrons in the charge storage layer 9 escape to the memory gate MG side by tunnel emission, and data is erased.

  Further, the data write employs the source side hot electron injection method. In the data write operation, the selected memory cell MC1 has a drain region and the substrate 1, for example, 0 (zero) V, the control gate CG, for example, about 1.5 V, and the memory gate MG, for example, about 12 V, the selected memory. For example, about 6 V is applied to the source region of the cell MC. As a result, hot electrons generated in the channel of the memory cell MC1 are injected into the charge storage layer 9 to write data.

  FIG. 13 shows the threshold value variation ratio in the memory module (memory array) after erasing the memory cell MC1 in the first embodiment of the present invention and the memory cell MCx studied by the present inventors. The threshold value variation ratio in the module after erasure of the memory cell MC1 is shown with the threshold value variation in the module after erasure of the memory cell MCx as 100%. It can be seen that in this threshold value variation ratio, the memory cell MC1 has a threshold variation after erasure reduced by about 7.5% with respect to the memory cell MCx. That is, as described above, in the first embodiment, by using radical oxidation as sacrificial oxidation, it is possible to reduce threshold variation after erasure.

(Embodiment 2)
In the first embodiment, the case where radical oxidation is used as the sacrificial oxidation has been described. In the second embodiment of the present invention, the case where dry oxidation is used as the sacrificial oxidation will be described. Except for sacrificial oxidation, the structure of the nonvolatile memory, for example, is the same as that of the first embodiment.

  As shown in FIG. 12A, in order to recover the damage caused by dry etching, sacrificial oxidation is performed on the exposed surface of the substrate 1 to form, for example, a silicon oxide film 15 of about 6 nm. As this sacrificial oxidation, dry oxidation is performed in the second embodiment. Specifically, rapid thermal oxidation (RTO) is performed at about 1000 ° C. for 60 seconds. Note that the silicon oxide film 15 formed by sacrificial oxidation is removed by cleaning before forming the gate insulating film in the high-voltage MOS portion.

  As described above, in the second embodiment, by using rapid thermal oxidation as sacrificial oxidation, as shown in FIG. 12B, the formation of the silicon oxide film 15a is suppressed under the end portions of the spacer 14 and the memory gate MG. be able to. As described with reference to FIG. 15, the formation of the silicon oxide film 15a at the end of the memory gate MG causes erroneous writing / erase. That is, by suppressing the formation of the silicon oxide film 15a below the end portions of the spacer 14 and the memory gate MG by ISSG oxidation, it is possible to prevent erroneous writing / erasing of the nonvolatile memory.

  Further, by using rapid thermal oxidation as sacrificial oxidation, formation of the silicon oxide film 15b on the side surface of the polysilicon film 10 can be suppressed as shown in FIG. As described with reference to FIG. 15, the formation of the silicon oxide film 15b on the side surface of the polysilicon film 10 causes variation in the shape of the memory gate MG. In other words, by suppressing the formation of the silicon oxide film 15b on the side surface of the polysilicon film 10 by rapid thermal oxidation, it is possible to prevent the variation in shape of the miniaturized memory gate MG.

  Furthermore, by using rapid thermal oxidation as sacrificial oxidation, threshold variation after erasing can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above embodiment, the case where silicon nitride is applied as the charge storage layer has been described. However, a material that can form an insulating trap level, such as alumina (Al ₂ O ₃ ), is applied. Also good.

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor devices.

It is principal part sectional drawing which shows typically the semiconductor device in the manufacturing process in Embodiment 1 of this invention. FIG. 2 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 1; FIG. 3 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 2; FIG. 4 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 3; FIG. 5 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 4; FIG. 6 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 5; FIG. 7 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 6; FIG. 8 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 7; FIG. 9 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 8; FIG. 10 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 9; FIG. 11 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 10; (A) is sectional drawing which shows typically the memory gate of FIG. 5, (b) is an enlarged view of the encircled part of (a). It is explanatory drawing which shows the threshold value variation in a memory module. It is sectional drawing which shows typically the memory cell which the present inventors are examining. (A) is sectional drawing which shows typically the memory gate of FIG. 14, (b) is an enlarged view of the encircled part of (a).

Explanation of symbols

1 Semiconductor substrate (substrate)
2 surface oxide film 3 silicon nitride film 4 groove 5 element isolation 6a first n-type semiconductor region 6b second n-type semiconductor region 7 p-type well 8 silicon oxide film 9 charge storage layer 9a silicon nitride film 9b silicon oxynitride film 10 polysilicon film 11 Insulating film 12 First gate 13 Low-concentration n-type semiconductor region 14 Spacers 15, 15a, 15b Silicon oxide films 16, 17 n-type well 18 p-type wells 19, 20 Gate insulating film 21 Polysilicon film 22 Insulating film 23 Second Gates 24, 25, 26 Low-concentration n-type semiconductor regions 27, 28 Low-concentration p-type semiconductor regions 29 Spacers 30, 31, 32 High-concentration n-type semiconductor regions 33, 34 High-concentration p-type semiconductor regions 35 Silicide layer 36 Insulating film 37 Interlayer insulating film 38 Contact hole 39 Plug CG, CGx Control gate M1 First layer wiring MC1, M 2, MCx memory cell MG, MGx memory gate MIM capacitance element Q1 low withstand voltage p-channel MOSFET
Q2 Low voltage n-channel MOSFET
Q3 High voltage p-channel MOSFET
Q4 High voltage n-channel MOSFET

Claims (4)

(A) forming a first gate of the first field effect transistor by patterning a first electrode material film deposited on the main surface of the semiconductor substrate;
(B) forming a first spacer on the side wall of the first gate by etching back the first insulating film deposited so as to cover the first gate, and exposing the surface of the semiconductor substrate;
(C) forming a second gate of the second field-effect transistor so that a part of the electrode material film is deposited on the first gate by patterning the electrode material film deposited so as to cover the first gate;
A method of manufacturing a semiconductor device including:
Before the step (c), radical oxidation is performed on the surface of the semiconductor substrate exposed in the step (b).   2. The method of manufacturing a semiconductor device according to claim 1, wherein the radical oxidation is ISSG oxidation. (A) forming a first gate of the first field effect transistor by patterning a first electrode material film deposited on the main surface of the semiconductor substrate;
(B) forming a first spacer on the side wall of the first gate by etching back the first insulating film deposited so as to cover the first gate, and exposing the surface of the semiconductor substrate;
(C) forming a second gate of the second field-effect transistor so that a part of the electrode material film is deposited on the first gate by patterning the electrode material film deposited so as to cover the first gate;
A method of manufacturing a semiconductor device including:
Prior to the step (c), a dry oxidation is performed on the surface of the semiconductor substrate exposed in the step (b).   4. The method of manufacturing a semiconductor device according to claim 3, wherein the dry oxidation is rapid thermal oxidation.

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