JP2008003463A - Driving method of display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving method of display panel capable of displaying high-quality image without causing noise. <P>SOLUTION: An execution period of sustain process between sub-fields neighboring each other is varied in accordance with time elapse. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for driving a display panel in which a plurality of pixel cells are arranged.

  Recently, as a two-dimensional image display panel, a plasma display panel (hereinafter referred to as a PDP) in which a plurality of discharge cells are arranged in a matrix is drawing attention. Further, a subfield method is known as a driving method for displaying an image corresponding to an input video signal in such a PDP.

  In the subfield method, one field display period is divided into a plurality of subfields, and the following driving is performed in each subfield. That is, in each subfield, first, each discharge cell is set to one of a lighting mode and a light-off mode in accordance with pixel data for each pixel based on the input video signal (address process). Next, the sustain pulse is repeatedly applied to all the discharge cells a number of times corresponding to the luminance weight of the subfield, thereby causing only the discharge cells in the lighting mode to emit light repeatedly (sustain stroke). According to the driving based on the subfield method, the luminance corresponding to the number of times of light emission of the discharge cells generated in one field display period is visually recognized. At this time, the luminance range from the lowest luminance (black display) to the highest luminance represented by the input video signal is expressed by the number of gradations corresponding to the number of subfields in one field display period.

  In addition, there is a driving method that solves the shortage of the number of gradations by performing multi-gradation processing such as error diffusion and dither processing on the input video signal in combination with the driving based on the subfield method. It has been proposed (see, for example, FIG. 24 of Patent Document 1). In the dither processing, for each of a plurality of adjacent pixel groups, dither coefficients each having a different coefficient value are assigned and added to the error diffusion processing pixel data corresponding to each pixel in the pixel group. According to such dither processing, luminance corresponding to the average luminance of each pixel in the pixel group is visually recognized.

  However, if dither coefficients are regularly added to each pixel data by dither processing in units of pixels, a pseudo pattern that has nothing to do with the input video signal, so-called dither noise, may be seen. As a result, the image quality deteriorates.

  In view of this, there has been proposed a driving method that realizes dither in units of display lines and that is executed in combination with so-called line dither driving (see, for example, FIG. 31 of Patent Document 2). In such line dither driving, each discharge cell is caused to emit light by assigning a different luminance weight to each display line in the display line group for each display line group consisting of n display lines adjacent to each other in the PDP. In the light emission drive sequence shown in FIG. 31 of Patent Document 2, each subfield is further divided into a plurality of subfields (referred to as divided subfields), and each display line is in a lighting mode state within the subfield. The number of divided subfields that cause the discharge cells to emit light is made different.

  By the way, according to the line dither driving, the sustain process of each divided subfield is intermittently and periodically performed because a plurality of divided subfields having substantially the same period are continuous. .

However, if the sustain process of repeatedly applying the sustain pulse to all the discharge cells is performed intermittently and periodically, the sustain process execution period concentrates on a specific frequency, and unnecessary radiation occurs, or the PDP On the other hand, there is a problem that noise is generated from the drive circuit that applies various drive pulses including the sustain pulse.
JP 2000-227778 A JP 2004-252186 A

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a display panel driving method capable of displaying a high-quality image without causing unnecessary radiation or noise. Is.

  The display panel driving method according to claim 1 is for each unit display period in an input video signal, wherein each of the pixels is turned on and off in accordance with pixel data for each pixel based on the input video signal. A display panel driving method for driving a display panel by a plurality of subfields including an addressing process set to one of the above states and a sustaining process for causing the pixels in the lighting mode to emit light. An execution cycle of the sustain process between subfields varies with time.

  In the present invention, the execution cycle of the sustain process between adjacent subfields is varied with time. As a result, even when subfields having sustain processes to which substantially the same luminance weights are assigned continue, the sustain process execution cycle between the subfields is not concentrated on a specific frequency, and unnecessary radiation is eliminated. Or the noise emitted from a drive circuit is suppressed.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a plasma display device as a display device according to the present invention.

In FIG. 1, a PDP 100 as a plasma display panel includes a front substrate (not shown) serving as a display surface and a rear substrate (positioned opposite to the front substrate across a discharge space filled with discharge gas). (Not shown). On the front substrate, the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n are are respectively extended in the lateral direction of the display screen is alternately and parallel to each other. On the back substrate, column electrodes D _{1 to} D _m are formed, each extending in the vertical direction of the display screen. Incidentally, the row electrodes X ₁ to X _n and Y ₁ to Y _n, each display line of PDP100 pair of row electrodes X and Y, i.e. has a structure responsible for first through n-th display line, each row electrode Discharge cells G serving as pixels are formed at intersections (including discharge spaces) between the pair and the column electrodes. That is, in the PDP 100, (n × m) discharge cells G _{(1,1) to} G _{(n, m)} are formed in a matrix.

  The pixel data conversion circuit 1 converts the input video signal into pixel data PD for each pixel and supplies it to the multi-gradation processing circuit 2. The multi-gradation processing circuit 2 includes a line offset data generation circuit 21, an adder 22, and a lower bit truncation circuit 23.

  The line offset data generation circuit 21 generates line offset data LD and supplies it to the adder 22 every time pixel data PD is supplied from the pixel data conversion circuit 1. At this time, the line offset data generation circuit 21 generates line offset data LD having different values for each of the following display lines to which the discharge cells corresponding to the pixel data PD belong.

(4N-3) th display line (4N-2) th display line (4N-1) th display line (4N) th display line
[N: natural number less than (1/4) · n]
The adder 22 supplies the offset addition pixel data obtained by adding the line offset data LD to the pixel data PD supplied from the pixel data conversion circuit 1 to the lower bit truncation circuit 23. The lower bit truncation circuit 23 truncates the lower bit group of the offset addition pixel data and supplies the remaining upper bit group to the drive data conversion circuit 3 as multi-gradation pixel data MD.

  Based on the multi-gradation pixel data MD, the drive data conversion circuit 3 sets each discharge cell in either the lighting mode or the non-lighting mode in each address process of subfields SF1 to SF (Q-1) described later. Is converted into pixel drive data GD indicating whether or not, and this is supplied to the memory 4.

The memory 4 sequentially captures and stores the pixel drive data GD. Each time the writing of the pixel drive data GD _{(1,1) to} GD _{(n, m)} for one frame (n rows × m columns) is completed, the memory 4 performs the following reading. That is, the memory 4 separates each of the pixel drive data GD _{(1,1) to} GD _{( n, m)} for each bit digit (first to (Q-1) bits),
SF1 for each pixel drive data bit corresponding to the first bit digit,
SF2 for each pixel drive data bit corresponding to the second bit digit,
Each of the pixel drive data bits corresponding to the third bit digit is set to SF3,
・
・
・
Each pixel drive data bit corresponding to the (Q-1) th bit digit is set to SF (Q-1),
One display line (m) is read in each address process. The memory 4 supplies the read pixel drive data bits for one display line (m) to the column electrode drive circuit 5 as pixel drive data bits DB1 to DB (m).

  The drive control circuit 6 sends various timing signals to drive the PDP 100 in gray scale according to the light emission drive sequence as shown in FIG. 2 based on the subfield method, and outputs the column electrode drive circuit 5, the row electrode Y drive circuit 7 and the row electrode. This is supplied to each of the electrode X drive circuits 8.

In the light emission drive sequence shown in FIG. 2, one frame or one field display period (hereinafter referred to as a unit display period) is divided into Q (Q: an integer of 2 or more) subfields SF1 to SF (Q). The following various driving operations are performed for each subfield. The subfields SF3 to SF (Q-1) excluding the first and subsequent subfields SF1 and SF2 and the last subfield SF (Q) are divided into four divided subfields DSF ₁ as shown in FIG. consisting of ~DSF _4.

  In FIG. 2, a subfield SF1 includes a reset period R in which all discharge cells of the PDP 100 are initialized to a lighting mode, and an address process W0 in which each of the discharge cells is selectively shifted to a light-off mode according to the pixel drive data. With. The subfield SF2 selectively shifts each discharge cell to the extinguishing mode according to the sustain process I in which only the discharge cells in the lighting mode continue to emit light for a predetermined first period and the pixel drive data. And an address process W0.

Each of the divided subfields DSF _{1 to} DSF ₄ of each of the subfields SF3 to SF (Q-1) is obtained by equally dividing the number of times corresponding to the luminance weight of the subfield by the number of divided subfields (4). A sustain process I is provided in which only the discharge cells in the lighting mode are repeatedly subjected to the sustain discharge light emission for a given number of times. That is, the same luminance weight is assigned to the sustain process I of each of the divided subfields DSF _{1 to} DSF _{4 in} each subfield SF.

Further, in the divided subfield DSF ₁ of each of the subfields SF3 to SF (Q-1), immediately after the sustain process I, discharge cells belonging to the (4N-3) th display line according to the pixel drive data. An address process W1 is provided for selectively shifting each to the extinguishing mode. Further, the sub-field SF3~SF (Q-1) to each of the divided subfields DSF _2, immediately after the sustain stage I, the (4N-2) th discharge cell belonging to the display line according to pixel-drive data An address process W2 is provided for selectively shifting each to the extinguishing mode. Further, the sub-field SF3~SF (Q-1) to each of the divided subfields DSF _3, immediately after the sustain stage I, the (4N-1) th discharge cell belonging to the display line according to pixel-drive data An address process W3 is provided for selectively shifting each to the extinguishing mode. Further, in each of the divided subfields DSF ₄ of the subfields SF3 to SF (Q-1), immediately after the sustain process I, the discharge cells belonging to the (4N) th display line are displayed according to the pixel drive data. An address process W4 for selectively shifting to the extinguishing mode is provided.

  The last subfield SF (Q) includes a sustain process I in which only the discharge cells in the lighting mode are repeatedly discharged for a predetermined number of times.

In the subfield SF3~SF (Q-1) as shown in FIG. 2, between the divided subfield DSF ₂ and DSF ₃ adjacent to each other, as well as, between the divided subfield DSF ₄ and DSF ₁ adjacent to each other In addition, a divided light emission pause period NP is provided in which the light emission drive operation (discharge light emission operation) for the PDP 100 is paused. That is, the divided light emission suspension periods NP are provided between the divided subfields DSF adjacent to each other and between the subfields SF.

  FIG. 3 is a diagram showing various drive pulses applied to the PDP 100 by the column electrode drive circuit 5, the row electrode Y drive circuit 7, and the row electrode X drive circuit 8 according to the light emission drive sequence, and the application timing thereof.

  FIG. 3 shows various drive pulses applied to the PDP 100 by extracting only SF1 to SF3 from the subfields SF1 to SF (Q) shown in FIG.

First, in the reset period R of the subfield SF1, it is applied to the row electrodes X ₁ to X _n of the row electrodes X driving circuit 8 generates a moderate negative reset pulse RP _x of falling changes falling PDP 100. Simultaneously with the reset pulse RP _x, the row electrode Y driving circuit 7 applies the row electrodes Y ₁ to Y _n of PDP100 generates a reset pulse RP _Y of moderate positive rising conversion. Depending on the simultaneous application of these reset pulses RP _x and RP _Y, is within all discharge cells of PDP100 reset discharge is occurring, the wall charges in each discharge cell is formed. As a result, all the discharge cells are initialized to a lighting mode in which light emission (light emission associated with the sustain discharge) is possible in a sustain process I described later.

In the address process W0 of each of the subfields SF1 and SF2, the row electrode Y drive circuit 7 sequentially applies a negative scan pulse SP to the row electrodes Y _{1 to} Y _n . During this time, the column electrode drive circuit 5 generates (m) pixel data pulses for one display line corresponding to the pixel drive data bits DB1 to DB (m) read from the memory 4, and these m pixels. A pixel data pulse group DP consisting of data pulses is applied to each of the column electrodes D _{1 to} D _m in synchronization with the timing of the scanning pulse SP. That is, the column electrode driving circuit 5 sequentially applies each of the pixel data pulse groups DP _{1 to} DP _n corresponding to the first to nth display lines of the PDP _{100 to the} column electrodes D _{1 to} D _{m as} shown in FIG. It is. The column electrode drive circuit 5 generates a high-voltage pixel data pulse when the pixel drive data bit DB is at logic level 1, while generating a low-voltage pixel data pulse when the pixel drive data bit DB is at logic level 0. To do. Here, the erase address discharge is generated only in the discharge cell at the intersection of the display line to which the scan pulse SP is applied and the column electrode to which the high voltage pixel data pulse is applied. Due to the erase address discharge, the wall charge formed in the discharge cell disappears, and the discharge cell shifts to a light-off mode in which light emission (light emission due to the sustain discharge) is not performed in a sustain process I described later. . On the other hand, in the discharge cells to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, the erase address discharge as described above does not occur, and the state (lighting mode or extinguishing mode) until just before that occurs. maintain.

  That is, in the address process W0, each discharge cell of the PDP 100 is selectively subjected to erase address discharge based on pixel data. Thereby, each discharge cell is set to either the lighting mode or the extinguishing mode.

Next, in the sustain process I of each of the subfields SF2 to SF (Q), the row electrode X drive circuit 8 and the row electrode Y drive circuit 7 are respectively connected to the row electrodes X _{1 to} X _n and repeatedly applied to the Y ₁ to Y _n for the number of times corresponding to the positive polarity sustain pulses IP _X and IP _Y of the luminance weight of the subfield alternately. At this time, only the discharge cells in which the wall charges remain, that is, the discharge cells set in the lighting mode, are subjected to the sustain discharge every time the sustain pulses IP _X and IP _Y are applied. The accompanying light emission state is maintained.

Further, the sub-field SF3~SF (Q) of each of the divided subfields subfields DSF ₁ of the address process W1, the row electrode Y driving circuit 7 is the (4N-3) of PDP100 the scanning pulse SP of negative polarity th display It is sequentially applied to the row electrodes Y belonging to the lines [N: 1 to (1/4) · n], that is, the row electrodes Y ₁ , Y ₅ , Y ₉ ,..., Y _(n−3) . During this time, the column electrode drive circuit 5 selects pixel drive data bits DB1 to DB (DB) corresponding to the discharge cells belonging to the (4N-3) th display line from among the pixel drive data bits read from the memory 4. m pixel data pulses for one display line based on m) are generated. Then, the column electrode driving circuit 5 applies the pixel data pulse group DP composed of these m pixel data pulses to each of the column electrodes D _{1 to} D _m in synchronization with the timing of the scanning pulse SP. That is, the column electrode drive circuit 5 applies each of the pixel data pulse groups DP ₁ , DP ₅ , DP ₉ ,..., DP _(n-3) corresponding to the (4N-3) th display line to FIG. As shown in FIG. 4, the voltage is sequentially applied to each of the column electrodes D _{1 to} D _m . The column electrode drive circuit 5 generates a high voltage pixel data pulse when the pixel drive data bit DB is at logic level 1, while generating a low voltage pixel data pulse when the pixel drive data bit DB is at logic level 0. To do. Here, the erase address discharge is generated only in the discharge cell at the intersection of the display line to which the scan pulse SP is applied and the column electrode to which the high voltage pixel data pulse is applied. Due to the erase address discharge, the wall charge formed in the discharge cell disappears, and the discharge cell shifts to the extinguishing mode in which the light emission (the light emission accompanying the sustain discharge) is not performed in the sustain process I. On the other hand, the above-described erase address discharge is not generated in the discharge cell to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, and the state (lighting mode or extinguishing mode) until just before that occurs. Maintained.

  That is, in the address process W1, only the discharge cells belonging to the (4N-3) th display line of the PDP 100 are targeted, and each discharge cell is set in a state corresponding to the pixel data (lighting mode, extinguishing mode). is there.

Further, the sub-field SF3~SF (Q) of each of the divided subfields subfields in DSF ₂ of the address process W2, row electrode Y driving circuit 7 is the (4N-2) in PDP100 the scanning pulse SP of negative polarity th display The voltage is sequentially applied to the row electrodes Y belonging to the lines [N: 1 to (1/4) · n], that is, the row electrodes Y ₂ , Y ₆ , Y ₁₀ ,..., Y _(n−2) . During this time, the column electrode drive circuit 5 selects pixel drive data bits DB1 to DB (DB) corresponding to the discharge cells belonging to the (4N-2) th display line from among the pixel drive data bits read from the memory 4. m pixel data pulses for one display line based on m) are generated. Then, the column electrode driving circuit 5 applies the pixel data pulse group DP composed of these m pixel data pulses to each of the column electrodes D _{1 to} D _m in synchronization with the timing of the scanning pulse SP. That is, the column electrode drive circuit 5 applies each of the pixel data pulse groups DP ₂ , DP ₆ , DP ₁₀ ,..., DP _(n−2) corresponding to the (4N−2) th display line to FIG. As shown in FIG. 4, the voltage is sequentially applied to each of the column electrodes D _{1 to} D _m . The column electrode drive circuit 5 generates a high voltage pixel data pulse when the pixel drive data bit DB is at logic level 1, while generating a low voltage pixel data pulse when the pixel drive data bit DB is at logic level 0. To do. Here, the erase address discharge is generated only in the discharge cell at the intersection of the display line to which the scan pulse SP is applied and the column electrode to which the high voltage pixel data pulse is applied. Due to the erase address discharge, the wall charge formed in the discharge cell disappears, and the discharge cell shifts to the extinguishing mode in which the light emission (the light emission accompanying the sustain discharge) is not performed in the sustain process I. On the other hand, the above-described erase address discharge is not generated in the discharge cell to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, and the state (lighting mode or extinguishing mode) until just before that occurs. Maintained.

  That is, in the address process W2, only the discharge cells belonging to the (4N-2) th display line of the PDP 100 are set as the target, and each discharge cell is set in a state corresponding to pixel data (lighting mode, extinguishing mode). is there.

Further, the sub-field SF3~SF (Q) of each of the divided subfields subfields in DSF ₃ of address process W3, the row electrode Y driving circuit 7 is the (4N-1) of PDP100 the scanning pulse SP of negative polarity th display The voltage is sequentially applied to the row electrodes Y belonging to the lines [N: 1 to (1/4) · n], that is, the row electrodes Y ₃ , Y ₇ , Y ₁₁ ,..., Y _(n−1) . During this time, the column electrode drive circuit 5 selects pixel drive data bits DB1 to DB (DB) corresponding to the discharge cells belonging to the (4N-1) th display line from among the pixel drive data bits read from the memory 4. m pixel data pulses for one display line based on m) are generated. Then, the column electrode driving circuit 5 applies the pixel data pulse group DP composed of these m pixel data pulses to each of the column electrodes D _{1 to} D _m in synchronization with the timing of the scanning pulse SP. That is, the column electrode drive circuit 5 applies each of the pixel data pulse groups DP ₃ , DP ₇ , DP ₁₁ ,..., DP _(n−1) corresponding to the (4N−1) th display line to FIG. As shown in FIG. 4, the voltage is sequentially applied to each of the column electrodes D _{1 to} D _m . The column electrode drive circuit 5 generates a high voltage pixel data pulse when the pixel drive data bit DB is at logic level 1, while generating a low voltage pixel data pulse when the pixel drive data bit DB is at logic level 0. To do. Here, the erase address discharge is generated only in the discharge cell at the intersection of the display line to which the scan pulse SP is applied and the column electrode to which the high voltage pixel data pulse is applied. Due to the erase address discharge, the wall charge formed in the discharge cell disappears, and the discharge cell shifts to the extinguishing mode in which the light emission (the light emission accompanying the sustain discharge) is not performed in the sustain process I. On the other hand, the above-described erase address discharge is not generated in the discharge cell to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, and the state (lighting mode or extinguishing mode) until just before that occurs. Maintained.

  That is, in the address process W3, only the discharge cells belonging to the (4N-1) -th display line of the PDP 100 are targeted, and each discharge cell is set in a state corresponding to pixel data (lighting mode, extinguishing mode). is there.

Further, the sub-field SF3~SF (Q) of each of the divided subfield subfield DSF in ₄ of the address process W4, the row electrode Y driving circuit 7 is PDP100 the scanning pulse SP of negative polarity (4N) -th display line [ N: 1 to (1/4) · n], that is, sequentially applied to the row electrodes Y ₄ , Y ₈ , Y ₁₂ ,..., Y _(n) . During this time, the column electrode drive circuit 5 selects pixel drive data bits DB1 to DB (m) corresponding to the discharge cells belonging to the (4N) th display line from among the pixel drive data bits read from the memory 4. Based on the above, m pixel data pulses for one display line are generated. Then, the column electrode driving circuit 5 applies the pixel data pulse group DP composed of these m pixel data pulses to each of the column electrodes D _{1 to} D _m in synchronization with the timing of the scanning pulse SP. That is, the column electrode drive circuit 5 sequentially applies each of the pixel data pulse groups DP ₄ , DP ₈ , DP ₁₂ ,..., DP _(n) corresponding to the (4N) th display line as shown in FIG. Apply to each of the column electrodes D _{1 to} D _m . The column electrode drive circuit 5 generates a high voltage pixel data pulse when the pixel drive data bit DB is at logic level 1, while generating a low voltage pixel data pulse when the pixel drive data bit DB is at logic level 0. To do. Here, the erase address discharge is generated only in the discharge cell at the intersection of the display line to which the scan pulse SP is applied and the column electrode to which the high voltage pixel data pulse is applied. Due to the erase address discharge, the wall charge formed in the discharge cell disappears, and the discharge cell shifts to the extinguishing mode in which the light emission (the light emission accompanying the sustain discharge) is not performed in the sustain process I. On the other hand, the above-described erase address discharge is not generated in the discharge cell to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, and the state (lighting mode or extinguishing mode) until just before that occurs. Maintained.

  That is, in the address process W4, only the discharge cells belonging to the (4N) th display line of the PDP 100 are targeted, and each discharge cell is set to a state corresponding to pixel data (lighting mode, extinguishing mode).

  According to the driving shown in FIG. 2 and FIG. 3, the opportunity to change the discharge cell from the extinguishing mode to the lighting mode state in the subfields SF1 to SF (Q) is the first subfield SF1. Only the reset period R. That is, once an erase address discharge is generated in one subfield of each subfield and the discharge cell is once set to the extinguishing mode, the discharge cell is returned to the lighting mode in the subsequent subfields. I can't do that. Therefore, as shown in FIG. 4, the discharge cells are set to the lighting mode in each of the subfields SF that are continuous by the amount corresponding to the luminance gradation to be expressed. Until the erase address discharge (indicated by a black circle) occurs, sustain discharge light emission (indicated by a white circle) is continuously generated in the sustain process I in each subfield SF. At this time, the intermediate luminance corresponding to the total light emission period within one field period due to the sustain discharge light emission is visually recognized.

Here, in the driving shown in FIGS. 2 to 4, the discharge cells belonging to each of the four display lines adjacent to each other in the vertical direction of the screen of the PDP 100, that is,
Discharge cells belonging to the (4N-3) th display line;
Discharge cells belonging to the (4N-2) th display line;
Discharge cells belonging to the (4N-1) th display line;
Discharge cells belonging to each of the (4N) th display lines;
For each, the total number of times of light emission in the unit display period at each gradation is made different.

For example, in the third gradation expressing the third lowest luminance level as shown in FIG. 4, the (4N-3) th display line, that is, the first, fifth, ninth,... As indicated by the white circles, the discharge cells belonging to each of the (n-3) th display lines emit sustain discharge in the sustain process I of the DSFs _{1 of the} subfields SF1, SF2, and SF3.

In the third gradation, the discharge cells belonging to the (4N-2) th display line, that is, the second, sixth, tenth,..., (N-2) display lines are white circles. As shown in FIG. 8, sustain discharge light is emitted in the sustain process I of DSF ₁ and DSF ₂ of SF1, SF2 and SF3.

In the third gradation, the discharge cells belonging to the (4N-1) th display line, that is, the third, seventh, eleventh,..., (N-1) display lines are white circles. as shown in, for sustain discharge light emission in SF1, SF2 and DSF ₁ of SF3 ~DSF ₃ each sustain process I.

In the third gradation, the discharge cells belonging to the (4N) th display line, that is, the fourth, eighth, twelfth,..., Nth display lines are shown as white circles as SF1. , SF2 and SF3 DSF ₁ to DSF ₄ are subjected to sustain discharge light emission in the sustain process I.

At this time, if the number of times of sustain discharge light emission in the sustain process I of each of the DSF ₁ to DSF _{4 in the} subfields SF1, SF2, and SF3 is “2”, the sustain discharge light emission caused in the third gradation is caused. The total number of flashes within the unit display period is as shown in FIG.
Discharge cells belonging to the (4N-3) th display line: “6”
Discharge cells belonging to the (4N-2) th display line: “8”
Discharge cells belonging to the (4N-1) th display line: “10”
Discharge cells belonging to the (4N) th display line: “12”
It becomes.

  That is, for each of the four display lines adjacent to each other, a drive for forcibly changing the total number of times of light emission within the unit display period at each gradation, that is, so-called line dither drive is performed. At this time, in the plasma display device shown in FIG. 1, the line offset data LD is added to the pixel data PD so as to cancel the luminance difference generated for each display line by the line dither drive.

For example,
The pixel data PD corresponding to the (4N-3) th display line is “14”.
The pixel data PD corresponding to the (4N-2) th display line is “12”.
The pixel data PD corresponding to the (4N−1) th display line is “10”.
The pixel data PD corresponding to the (4N) th display line is “8”.
Each line offset data LD is added.

  Then, the higher-order bit group of the addition result is set as multi-gradation pixel data MD, and the gradation corresponding to the luminance level indicated by the multi-gradation pixel data MD, that is, the first gradation to the first gradation as shown in FIG. Pixel drive data GD that should be executed for driving indicated by one of the Q gradations is generated.

  According to the driving as described above, since the luminance level expressed by each of the four discharge cells adjacent in the vertical direction of the screen is different for each gradation, the dither coefficient is regularly added by the dither processing for each pixel. Even if this is done, a good image display in which the dither pattern is inconspicuous is made.

Further, in such a drive, as shown in FIGS. 2 and 3, all discharges occur between the divided subfields DSF ₂ and DSF ₃ adjacent to each other and between the divided subfields DSF ₄ and DSF ₁ adjacent to each other. A divided light emission pause period NP in which the discharge light emission operation of the cell stops is provided.

  That is, when the sub-field method is employed and the PDP is driven in gray scale by a plurality of sub-fields SF1 to SF (Q) for each unit display period, actually, as shown in FIG. After the subfield SF (Q), there is a non-light emission drive period NPA in which no light emission drive operation is performed on the PDP 100. Therefore, each of the divided light emission pause periods NP obtained by dividing the non-light emission drive period NPA into a plurality of parts is distributed and arranged in the subfields SF3 to SF (Q-1) as shown in FIGS. It was.

According to the driving shown in FIG. 2 and FIG. 3, the period of each of the divided subfields DSF _{1 to} DSF _{4 in} each subfield SF is the same, but the next DSF ₂ is started after DSF ₁ is started. The period from the start of DSF ₂ is different from the period from the start of DSF ₂ to the start of the next DSF ₃ . Furthermore, the period from the start of the DSF ₃ to the start of the next DSF ₄ and the start of the sub-field DSF _{1 at} the beginning of the next subfield SF after the DSF ₄ is started. The periods between are different from each other.

For example, in the sub-field SF3 in FIG. 2, the period of the divided subfields DSF ₁ ~DSF ₄ each When a respective same period T _a1, DSF ₂ is started from the start is divided subfields DSF ₁ The period until is T _a1 . However, since there is a divided light emission suspension period NP between the divided subfields DSF ₂ and DSF ₃ , the period from the start of DSF ₂ to the start of DSF ₃ is divided into the above _Ta1 . A period _Ta2 is obtained by adding the light emission suspension period NP. Although the period from the start of the divided subfields DSF ₃ until DSF ₄ is started is T _a1, split emission between the divided subfields DSF ₁ of the DSF ₄ and the next sub-field SF since pause period NP is present, the period between from DSF ₄ is started up division subfield DSF ₁ of the next subfield SF is started becomes the T _a2.

As described above, in the driving shown in FIGS. 2 and 3, the divided light emission suspension periods NP are interspersed in the series of the divided subfield DSF, so that the sustaining between the adjacent subfields (DSF _{1 to} DSF ₄ ) is performed. The execution cycle of the process I is changed with the passage of time. As a result, even when divided subfields DSF having a sustain process to which substantially the same luminance weights are assigned continue, the execution cycle of the sustain process I does not concentrate on a specific frequency, so unnecessary radiation or driving Noise generated from the circuit is prevented.

  In the above embodiment, the divided light emission pause periods NP each having the same period length obtained by equally dividing the non-light emission drive period NPA as shown in FIG. 5 are scattered in the series by the divided subfield DSF. However, each of the divided light emission suspension periods does not necessarily have the same period length.

  6 and 7 are diagrams showing an example of a light emission drive sequence made in view of such points.

In FIG. 6, a divided light emission suspension period NP ₁ composed of different periods is provided between the divided subfields DSF ₂ and DSF ₃ adjacent to each other and between the divided subfields DSF ₄ and DSF ₁ adjacent to each other. ... NP ₃ is inserted, and other configurations are the same as those shown in FIG. On the other hand, in FIG. 7, the divided light emission suspension periods NP _{1 to} NP ₃ are randomly scattered without fixing the positions in the subfields SF3 to SF (Q-1).

Further, when inserting the divided light emission rest periods NP _{1 to} NP ₃ between the divided subfields DSF ₂ and DSF ₃ adjacent to each other and between the DSF ₄ and DSF ₁ , as shown in FIG. The divided light emission suspension periods NP _{1 to} NP ₃ to be inserted may be changed for each frame (or one field) display period or for each frame group (or field group).

Further, in the above embodiment, the line dither driving divides each subfield SF to be carried into four divided subfields DSF ₁ ~DSF _4, the number of dividing each sub-field is limited to four Instead, for example, it may be divided into eight divided subfields. At this time, one divided light emission suspension period NP is provided for every two consecutive DSFs or for every four DSFs.

  Further, in the above embodiment, as an addressing method for setting each discharge cell to a state (lighting mode or extinguishing mode) according to the pixel data, wall charges are formed in all the discharge cells in advance, and the pixel data The case where the so-called selective erasure address method for selectively erasing the wall charges remaining in each discharge cell according to the above is described. However, the present invention can be similarly applied to a case where a so-called selective write address method in which wall charges are selectively formed in each discharge cell in accordance with pixel data as such an addressing method. is there.

  In the above embodiment, the operation in the case where the present invention is applied to the light emission drive sequence in which the line dither drive is combined with the gradation drive based on the subfield method has been described. However, the line dither drive is not performed. The same applies.

For example, the present invention can be similarly applied to a light emission drive sequence including subfields SF1 to SF (Q) each having the address process W0 and the sustain process I as described above. At this time, as shown in FIG. 9, in inserting one of the divided light emission suspension periods NP _{1 to} NP ₃ for every two consecutive subfields SF, one frame (or 1 The divided light emission suspension periods NP _{1 to} NP ₃ to be inserted may be changed for each field) display period or for each frame group (or field group).

In the above embodiment, the execution cycle of the sustain process is changed by inserting the divided light emission suspension periods (NP, NP _{1 to} NP ₃ ) between the adjacent subfields (SF or DSF). . However, instead of inserting such a divided light emission pause period (NP, NP _{1 to} NP ₃ ), the pulse width of the scan pulse SP or the sustain pulse IP or the application period is changed to vary the execution period of the sustain process. You may do it.

For example, in each subfield SF shown in FIG. 2, instead of inserting the divided light emission suspension period NP, FIG. 10A is used for the divided subfields DSF ₁ and DSF ₃ and FIG. 10B is used for the DSF ₂ and DSF ₄ . ), The scan pulse SP and the sustain pulse IP are applied in the sustain process and the address process, respectively. At this time, in each sustain process of the divided subfields DSF ₁ and DSF ₃ , the row electrode Y drive circuit 7 and the row electrode X drive circuit 8 apply a sustain pulse IP having a pulse width T _I1 as shown in FIG. It is repeatedly applied to the row electrodes X and Y alternately. On the other hand, in the sustain process of each of the divided subfields DSF ₂ and DSF ₄ , the row electrode Y drive circuit 7 and the row electrode X drive circuit 8 have a pulse larger than the pulse width T _{I1 as} shown in FIG. A sustain pulse IP having a width T _I2 is repeatedly applied to the row electrodes X and Y alternately. Further, in each address process of the divided subfields DSF ₁ and DSF ₃ , the row electrode Y drive circuit 7 applies a scan pulse SP having a pulse width T _S1 as shown in FIG. 10A to each of the row electrodes Y _{1 to} Y _n. Are sequentially applied alternatively. On the other hand, in each address process of the divided subfields DSF ₂ and DSF ₄ , the row electrode Y drive circuit 7 scans a pulse having a pulse width T _S2 larger than the pulse width T _{S1 as} shown in FIG. sequentially alternatively applying a SP to the row electrodes Y ₁ to Y _n, respectively.

As described above, by changing the pulse width of the scan pulse SP or the sustain pulse IP or the application period, the period T _a1 spent in each of the divided subfields DSF ₁ and DSF ₃ is divided into the divided subfields DSF ₂ and DSF _4, respectively. It is smaller than the period T _a2 spent in the process. Therefore, even if the subfields (DSF _{1 to} DSF ₄ ) having the sustain process to which substantially the same luminance weight is assigned are consecutive, the execution cycle of the sustain process in each subfield (DSF _{1 to} DSF ₄ ) is It will change over time. Accordingly, since the sustain cycle execution cycle does not concentrate on a specific frequency, unnecessary radiation and noise generated from the drive circuit can be prevented.

It is a figure which shows the structure of the plasma display apparatus as a display apparatus by this invention. It is a figure which shows an example of the light emission drive sequence by this invention. It is a figure which shows the various drive pulses applied to PDP100 according to the light emission drive sequence shown in FIG. 2, and its application timing. It is a figure which shows an example of the light emission drive pattern in the unit display period in each of the 1st-Qth gradation. It is a figure showing the non-light-emission drive period NPA provided in the tail part in each unit display period when the drive according to a subfield method is implemented. It is a figure which shows another example of the light emission drive sequence. It is a figure which shows another example of the light emission drive sequence. It is a figure which shows another example of the light emission drive sequence. It is a figure which shows another example of the light emission drive sequence. It is a figure showing other examples (change of the pulse width or application period of scanning pulse SP or sustain pulse IP) of changing the execution cycle of a sustain process.

Explanation of symbols

2 Multi-gradation processing circuit 3 Drive data conversion circuit 6 Drive control circuit 100 PDP

Claims (12)

For each unit display period in the input video signal, an address process for setting each of the pixels to one of a lighting mode and a light-off mode according to pixel data for each pixel based on the input video signal, A display panel driving method for driving a display panel by a plurality of subfields including a sustain process for emitting light from the pixel in a lighting mode state,
A method for driving a display panel, wherein an execution cycle of the sustain process between adjacent subfields varies with time.   Each of the divided light emission suspension periods obtained by dividing the non-light emission drive period during which no light emission drive is performed on the display panel within the unit display period is divided into a plurality of the unit display periods. 2. The method of driving a display panel according to claim 1, wherein an execution cycle of the process is changed.   Each of the divided light emission rest periods is dispersedly arranged in a subfield group in which subfields including a sustain process having the same luminance weight are continuously arranged within the unit display period. The method for driving a display panel according to claim 2.   3. The display panel driving method according to claim 2, wherein each of the divided light emission suspension periods has the same period length.   3. The method of driving a display panel according to claim 2, wherein at least two of the divided light emission suspension periods have different period lengths.   3. The display panel driving method according to claim 2, wherein the divided light emission suspension period is provided for each of a predetermined number of continuous subfields.   The display panel driving method according to claim 2, wherein each of the divided light emission suspension periods is randomly arranged within the unit display period.   3. The display panel driving method according to claim 2, wherein each of the divided light emission suspension periods is disposed between adjacent subfields.   3. The method of driving a display panel according to claim 2, wherein at least one of each of the divided light emission suspension periods is arranged in a subfield.   2. The display panel driving method according to claim 1, wherein an execution cycle of the sustain process is changed for each field or for each of a plurality of fields.   2. The display panel driving method according to claim 1, wherein the sustaining cycle is changed by changing a pulse width of a driving pulse applied to the display panel in the addressing step or the sustaining step.   2. The display panel driving method according to claim 1, wherein an execution period of the sustain process is changed by changing an application period of a drive pulse applied to the display panel in the address process or the sustain process.

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