JP3678940B2 - Display panel drive method - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a method for driving a display panel such as a plasma display panel (hereinafter referred to as PDP).
[0002]
[Prior art]
Conventionally, a subfield method is known as a method of displaying gray scales on a matrix display panel such as a PDP. In this subfield method, display is performed by dividing a display period of one field into N subfields that emit light a number of times corresponding to the weighting of each bit digit of N-bit pixel data. For example, when the pixel data per pixel is 6 bits, the display period of one field is divided into _six subfields SF _{1 to} SF ₆ . At this time, the number of sustain discharges in each of the subfields SF _{1 to} SF ₆ is set to, for example, 1 time, 2 times, 4 times, 8 times, 16 times, and 32 times in order. A combination of 64 gradations is displayed.
[0003]
When driving a matrix display panel such as a PDP, when image display is performed using interlaced video signals (interlaced video signals) such as NTSC, scanning is performed to compensate for the low emission luminance. The interlaced video signal is converted into a non-interlaced video signal for sequential scanning by line conversion processing, and display driving is performed by sequential scanning.
[0004]
[Problems to be solved by the invention]
However, the above-described conventional driving method requires a large-capacity memory, an arithmetic circuit, and the like to perform the scanning line conversion process, and there is a problem in that the entire circuit becomes large and costs increase.
[0005]
The present invention has been made to solve the above-described conventional problems, and provides a display panel driving method capable of reducing cost by eliminating the need for a scanning line conversion process and suppressing a decrease in light emission luminance. The purpose is to do.
[0006]
[Means for Solving the Problems]
The invention according to claim 1 for achieving the above object, a method of driving a display panel for gradation display using a plurality of sub-fields, the display period of two fields, odd and even fields A plurality of N subfields according to the pixel data for one field, and a subfield for selectively driving the discharge cells of the odd-numbered display line group according to the pixel data of the odd field; The arrangement order of the subfields for selectively driving the discharge cells in the even-numbered display line group according to the even-field pixel data is shifted by one field from each other,
An address period in which each of the discharge cells positioned in the display line group in the odd-numbered row is set to either light emission or non-light emission in accordance with the pixel data in the odd field, and in accordance with the pixel data in the even field. An address period that allows each of the discharge cells positioned in the display line group of the even-numbered rows to be set to either light emission or non-light emission is provided over the two fields .
[0007]
According to such a driving method, it is possible to prevent a decrease in light emission luminance, and it is unnecessary to perform a scanning line conversion process, thereby realizing a reduction in cost by simplifying a circuit or the like. In addition, since the number of selective discharges for each discharge cell is ½ that of the prior art, power consumption during addressing can be reduced.
[0008]
According to a second aspect of the present invention, in the display panel driving method according to the second aspect of the present invention, M (2 ≦ M ≦ N) subfields continuously arranged from the plurality of N subfields. And a sustain discharge period in which a number of sustain pulses corresponding to each subfield is supplied to the display line to cause only the light emitting cells to emit light. initially either state of the respective discharge cells, light-emitting cells or non-light emitting cell by allowed to discharge all the discharge cells prior to the address period only in the sub-field is first arranged in the sub-field group A reset period for converting the pixel data into an address period of any one of the subfields in the subfield group. Wherein the allowed to set in one of the state of each light emitting cells or non-light emitting cells of the discharge cell positioned in the display lines of the odd and even rows in accordance with the.
[0009]
According to this driving method, the number of reset discharges and the number of selective discharges for each discharge cell is, for example, once in two fields, so that the contrast is improved and the power consumption during addressing is reduced.
[0010]
According to a third aspect of the present invention, in the display panel driving method according to the second aspect of the present invention, the sustain discharge period of the subfield in the temporally rear field of the display period over the two fields is set. , into a plurality of divided sustain discharge period, the supply timing of the sustain pulses in the one field, and sets the same in the adjacent display lines.
[0011]
According to this driving method, when driving the odd-numbered display line group and the even-numbered display line group of the display panel, the time between the address period of one display line group and the sustain discharge period of the other display line group Therefore, the stability of the selective discharge in these address periods is ensured.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. As an embodiment, a method for driving a plasma display panel (PDP) will be described.
[0013]
(First embodiment)
A first embodiment will be described with reference to FIGS. FIG. 1 is a block diagram showing the configuration of a driving device that drives a PDP based on the driving method of the present embodiment. FIG. 2 is a timing chart for explaining the relationship between writing and reading of pixel data in a frame memory. 3 is an explanatory diagram for explaining the relationship between each field and data written to the frame memory, and FIG. 4 is an explanatory diagram for explaining a drive format.
[0014]
In FIG. 1, the driving device 1 of this embodiment includes an A / D converter 2, a data processing unit 3, a frame memory 4, a control unit 5, an address driver 6, Y electrode drivers 7 and 8 that are sustain drivers, and an X electrode. A driver 9 and 10 are provided.
[0015]
The A / D converter 2 synchronizes the interlaced scanning video signal Sin with N bits per pixel in synchronization with a clock signal CK having a predetermined frequency supplied from the control unit 5 (in this embodiment, N = Is converted into input pixel data Din of 8 bits) and supplied to the data processing unit 3.
[0016]
The data processing unit 3 performs multi-gradation processing such as error diffusion processing or dither processing in accordance with the control signal CNT synchronized with the clock signal CK supplied from the control unit 5, whereby the input pixel data Din The lower 2 bits are compressed. Thus, the 8-bit input pixel data Din is compressed and converted into 6-bit pixel data Pin and supplied to the frame memory 4.
[0017]
The frame memory 4 writes and reads each pixel data Pin in accordance with a synchronization signal such as a read / write control signal RW supplied from the control unit 5. That is, as shown in the timing chart of FIG. 2, the frame memory 4 alternately writes the interlaced pixel data Pin in the order of an odd field (hereinafter referred to as A field) and an even field (hereinafter referred to as B field). . Then, each pixel data Pin of the odd line written during the current A field period is read out during the current frame period (within the current A field and the current B field period), and each pixel of the even line written during the B field period. Data Pin is read within the period of the current B field and the next A field.
[0018]
More specifically, as shown in FIG. 3, each pixel data Pin of the A field corresponding to the odd-numbered display lines of the PDP is represented by A _{1,1 to} A _{2n-1, m} , and the even-numbered display lines of the PDP. If the pixel data Pin of the B field corresponding to is represented by B _{2,1 to} B _{2n, m} (where n and m are natural numbers), the pixel data A _{1,1 to} A _{2n-1, m} is an odd number. Write sequentially to each odd address storage area of the frame memory 4 corresponding to the display line of the row, and then store the pixel data B _{2,1 to} B _{2n, m} of the B field into the frame memory corresponding to the display line of the even row. 4 are sequentially written in the storage area of the even address.
[0019]
On the other hand, at the time of reading, the pixel data A _{1,1 to} A _{2n-1, m} and B _{2,1 to} B _{2n, m} written in the frame memory 4 are stored in bit digits corresponding to each subfield described later. The bit data is divided and supplied to the address driver 6 in synchronization with the scanning cycle of the display line (one horizontal scanning cycle).
[0020]
The control unit 5 generates a reset timing signal, a scanning timing signal, a maintenance timing signal, and an erasing timing signal based on the horizontal and vertical synchronization signals included in the input video signal Sin, and outputs these generated signals to the Y electrode. Supplied to drivers 7 and 8 and X electrode drivers 9 and 10.
[0021]
The Y electrode drivers 7 and 8 and the X electrode drivers 9 and 10 are provided with a reset pulse and address driver 6 for initializing the wall charge amount of each discharge cell of the PDP in accordance with the timing set by each of the generation signals. A scan pulse for writing a pixel data pulse, which will be described later, supplied, a sustain pulse for maintaining the discharge light emission state, and an erase pulse for stopping the discharge light emission of each of the discharge cells are generated. Then, it is supplied to the row electrode pairs Y ₁ to Y _2n and X _{1 to} X _2n at a predetermined timing described later.
[0022]
The address driver 6 generates a pixel data pulse having a voltage value (gradation value) corresponding to each bit data based on the bit digit bit data corresponding to each subfield supplied from the frame memory 4. and supplies these pixel data pulses to the column electrodes D ₁ to D _m of the PDP.
[0023]
In the PDP, the discharge cells CL _{1,1 to} CL _{2n, 2m} are arranged in a matrix at the intersections of the row electrode pairs Y ₁ to Y _2n and X _{1 to} X _2n and the column electrodes D _{1 to} D _m. It is arranged in a shape.
[0024]
Next, the operation of the PDP driving apparatus having such a configuration will be described with reference to the driving format of FIG.
[0025]
In FIG. 4, in the present embodiment, as a typical example, a display period _TF consisting of two fields is divided into _six subfields SF _{1 to} SF ₆ according to 6-bit pixel data Pin, and for each field. The supplied pixel data Pin is made to correspond to the display period _TF of 2 fields.
[0026]
Each of the subfields SF _{1 to} SF ₆ includes a reset period R, an address period W, a sustain discharge period I, and a full erase period E.
[0027]
In the reset period R, the Y electrode drivers 7 and 8 and the X electrode drivers 9 and 10 simultaneously apply the reset pulse having the opposite polarity to each pair of the row electrode pairs Y ₁ to Y _2n and X _{1 to} X _2n. Then, reset discharge is generated in all the discharge cells CL _{1,1 to} CL _{2n, m} . As a result, a predetermined amount of wall charges are formed in the discharge cells CL _{1,1 to} CL _{2n, m} to initialize the state of the light emitting cell.
[0028]
In the address period W, the address driver 6 applies pixel data pulse groups corresponding to each row (display line) of the PDP to the column electrodes D _{1 to} D _m in a dot-sequential manner. Further, the Y electrode drivers 7 and 8 sequentially apply the scan pulse to the row electrodes Y _{1 to} Y _2n at the same timing as the application timing of the pixel data pulse group. At this time, discharge occurs only in the discharge cell at the intersection of the row electrode to which the scan pulse is applied and the column electrode to which the high-voltage pixel data pulse is applied, and the discharge cell is formed in the reset period R. The wall charge that has been applied is selectively erased. By this selective erasing discharge, a light emitting discharge cell in which discharge light emission occurs in a sustain discharge period I described later and a non-light emitting discharge cell in which no discharge light emission occurs are set.
[0029]
Next, the sustaining pulses are alternately applied to the row electrodes Y _{1 to} Y _2n and the row electrodes X _{1 to} X _2n by the Y electrode drivers 7 and 8 and the X electrode drivers 9 and 10. Accordingly, only the light emitting discharge cells in which the wall charges remain in the address period W are discharged each time the sustain pulse is applied, and the light emitting state is maintained.
[0030]
When this light emitting discharge cell emits light by discharge, the ratio of the number of times of light emission (number of sustain pulses) within each sustain discharge period I of each of the subfields SF _{1 to} SF ₆ is SF ₁ : SF ₂ : SF ₃ : SF ₄ : SF ₅ : SF ₆ = 1: 2: 4: 8: 16: 32 is set, and the sustain discharge period I of each of the subfields SF _{1 to} SF ₆ is set to a uniform time length τ. ing. That is, when driving the light emitting cells CL _{1,1 to} CL _{2n-1, m} located in the odd-numbered display line group and the light emitting cells CL _{2,1 to} CL _{2n, m} located in the even-numbered display line group, If the address period W of one display line group and the sustain discharge period I of the other display line group overlap in time, the stability of the selective discharge in the address period W may be impaired. By setting each sustain discharge period I of SF _{1 to} SF ₆ to a uniform time length τ, the above time overlap is not caused.
[0031]
When the PDP is driven according to such a drive format, in the first field period shown in FIG. 4, the lower three bits of the pixel data Pin supplied in the A field period of the first frame are displayed for the odd-numbered display lines of the PDP. In the corresponding subfields SF ₁ , SF ₂ , SF ₃ , the light emission drive is executed sequentially.
[0032]
Further, in the second field period in the figure, the subfields SF ₄ and SF corresponding to the upper 3 bits of the pixel data Pin supplied in the A field period of the first frame with respect to the odd-numbered display lines of the PDP. ₅ and SF ₆ , the light emission drive is sequentially executed, and the subfield SF corresponding to the lower 3 bits of the pixel data Pin supplied in the B field period of the first frame is applied to the display lines of the even rows of the PDP. ₁ , SF ₂ , and SF ₃ are sequentially driven for light emission.
[0033]
Furthermore, in the third field in the figure, the subfields SF ₁ and SF corresponding to the lower 3 bits of the pixel data Pin supplied within the A field period of the second frame for the odd-numbered display lines of the PDP. ₂ and SF ₃ , the light emission drive is sequentially executed, and the subfield SF corresponding to the upper 3 bits of the pixel data Pin supplied in the B field period of the first frame for the even-numbered display lines of the PDP. ₄ , SF ₅ , and SF ₆ are sequentially driven for light emission.
[0034]
As described above, in the driving method of the present embodiment, the display period _TF of two fields is divided into _N subfields SF _{1 to} SF _N according to the pixel data Pin for one field (A field or B field), In each of the subfields SF _{1 to} SF _N , the discharge cells CL _{1,1 to} CL _{2n, m} on each display line of the PDP are driven and the arrangement order of the subfields SF _{1 to} SF _N is displayed adjacently. The line is shifted by one field.
[0035]
As a result, it is possible to prevent the light emission luminance from being lowered, and the scanning line conversion process is not required, so that the cost can be reduced by simplifying the circuit. Further, the number of selective erasing discharges in the address period W is halved compared to the conventional case, and the power consumption during addressing can be reduced.
[0036]
(Second Embodiment)
Next, a second embodiment will be described with reference to FIGS. FIG. 5 is an explanatory diagram for explaining a drive format in this embodiment, and is shown corresponding to FIG. FIG. 6 is a block diagram showing a configuration of the data processing unit 3 ′, and FIG. 7 is a light emission driving pattern when the selective erasing address method is adopted, and is used by the data conversion unit 3b ′ when implementing this light emission driving pattern. It is explanatory drawing which shows an example of a conversion table.
[0037]
The drive device of this embodiment has a configuration in which the data processing unit 3 in FIG. 1 is replaced with the data processing unit 3 ′ shown in FIG. 6, and other components are the same as those in the first embodiment. It is.
[0038]
Hereinafter, characteristic points of the present embodiment will be described. 6 and 7, the multi-gradation processing unit 3 a ′ of the data processing unit 3 ′ includes the lower 5 bits of the 8-bit input pixel data Din from the A / D converter 2 by multi-gradation processing. Is compressed to generate 3-bit pixel data with a reduced number of bits. The data conversion unit 3b ′ receives the 3-bit pixel data, and in accordance with the data conversion table shown in FIG. 7, the 7-bit pixel data Pin including the first to seventh bits corresponding to each of the subfields SF1 to SF7. Convert to and output.
[0039]
Next, in the drive format of FIG. 5, as a first feature point, a display period _TF consisting of two fields is divided into N subfields SF _{1 to} SF ₇ (N = 7 in this embodiment). The subfields SF _{1 to} SF ₅ are assigned to the period in which the pixel data Pin belonging to the A field is supplied, and the subfields SF ₆ and SF ₇ are assigned to the period in which the pixel data Pin belonging to the B field is supplied. Here, the sustain discharge period of subfields SF ₆ and SF ₇ is divided into a plurality of divided sustain discharge periods I ₁ , I ₂ and I ₁ ′ to I ₃ ′, and these divided sustain discharge periods I ₁ , I The number of sustain pulses in ₂ and I ₁ ′ to I ₃ ′ and their supply timing are set to be the same in the adjacent display lines of the PDP.
[0040]
Further, as a second feature point, among N = 7 subfields SF _{1 to} SF ₇ , 2 or more and N or less subfields SF (ie, 2 ≦ M ≦ N ) arranged continuously. _{1 to} SF _M are subfield groups, and a reset period R is provided only in the _first subfield SF ₁ arranged in the subfield group. In the present embodiment, the subfields SF _{1 to} SF _M constituting the subfield group are M = 7 subfields SF _{1 to} SF ₇ .
[0041]
Further, in the subfield SF ₇ arranged last in the subfield group, a full-erasing period E for setting all the discharge cells as non-light emitting cells is provided after the sustain discharge period I ₃ ′, and the subfield SF ₁ In the address period W of any one subfield in .about.SF ₇ , each discharge cell is selectively discharged according to the pixel data Pin so as to be set to either the light emitting cell or the non-light emitting cell. ing.
[0042]
Here, as a third feature point, the step of selectively discharging each discharge cell in accordance with the pixel data Pin in the second feature point to set the state to either the light emitting cell or the non-light emitting cell is as follows. This is executed in the address period W of any one subfield and the address period W of at least one subfield arranged behind the one subfield in terms of time.
[0043]
When the PDP is driven based on such a driving format, the address period W of one display line group and the display of the other display line group when driving the odd-numbered display line group and the even-numbered display line group due to the first feature point. Time overlap with the sustain discharge periods I, I ₁ , I ₂ and I ₁ ′ to I ₃ ′ of the line group can be prevented, and the stability of the selective discharge during these address periods can be ensured.
[0044]
Furthermore, because of the second feature point, the number of reset discharges and the number of selective discharges for each discharge cell is one in two fields, so that the contrast can be improved and the power consumption during addressing can be reduced.
[0045]
Further, according to the third feature, the selection operation can be ensured by performing the selection operation at least twice with the same pixel data Pin.
[0046]
In the second embodiment, the case of using the selective erasure address method has been described. However, the present invention is not limited to this, but can be applied to the case of using the selective write address method.
[0047]
【The invention's effect】
As described above, according to the display panel driving method of the present invention, gradation display is performed using N subfields, and a display period of 2 fields is set to N in accordance with pixel data for one field. Since the display lines of the display panel are driven in each subfield, the display line of the display panel is driven by shifting the arrangement order of the subfields by one field in the adjacent display lines. A reduction in light emission luminance can be prevented, and a scan line conversion process is not required, so that the cost can be reduced by simplifying the circuit.
[0048]
Further, since the number of reset discharges and the number of selective discharges for each discharge cell can be halved compared to the conventional one, the contrast can be improved and the power consumption during addressing can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a PDP driving device according to an embodiment.
FIG. 2 is a timing chart for explaining a relationship between writing and reading of pixel data in a frame memory.
FIG. 3 is an explanatory diagram for explaining a relationship between each field and data written to the frame memory;
FIG. 4 is an explanatory diagram for explaining a drive format when driving a PDP;
FIG. 5 is an explanatory diagram for explaining a drive format in a second embodiment;
FIG. 6 is a block diagram showing a configuration of a data processing unit in the second embodiment.
FIG. 7 is an explanatory diagram showing an example of a light emission driving pattern and a data conversion table when the light emission driving pattern is executed in the second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Drive device 2 ... A / D converter 3, 3 '... Data processing part 3a' ... Multi-gradation processing part 3b '... Data conversion part 4 ... Frame memory 5 ... Control part 6 ... Address driver 7, 8 ... Y electrode drivers 9, 10... X electrode drivers CL _{1,1 to} CL _{2n, m} ... discharge cells Y _{1 to} Y _2n , X _{1 to} X _2n ... row electrodes D _{1 to} D _m ... column electrodes

Claims (5)

A display panel driving method for performing gradation display using a plurality of subfields,
The display period of two fields, in response to each one field of pixel data of the odd and even fields, as well as divided into subfields plurality N,
A subfield for selectively driving the discharge cells of the odd-numbered display line group according to the pixel data of the odd-numbered field, and a subfield for selectively driving the discharge cells of the even-numbered display line group according to the pixel data of the even-numbered field. Are arranged by shifting the arrangement order of each other by one field,
An address period in which each of the discharge cells positioned in the display line group in the odd-numbered row is set to either light emission or non-light emission in accordance with the pixel data in the odd field, and in accordance with the pixel data in the even field. A display panel driving method comprising: an address period for setting each of the discharge cells located in the display line group of the even-numbered rows to either one of light emission or non-light emission over the two fields. . Of the N subfields, M subfields (2 ≦ M ≦ N) arranged continuously are subfield groups,
Each of the subfields in the subfield group is provided with a sustain discharge period in which a number of sustain pulses corresponding to each subfield is supplied to the display line so that only the light emitting cells emit light ,
Only in the first subfield arranged in the subfield group, all the discharge cells are discharged before the address period to initialize each of the discharge cells to a light emitting cell or a non-light emitting cell. Set a reset period to
In the address period of any one subfield in the subfield group, each of the discharge cells located on the display lines of the odd and even rows according to the pixel data is either a light emitting cell or a non-light emitting cell. The display panel driving method according to claim 1, wherein the display panel is set to a state. The discharge sustain periods of the sub-fields in a field of a temporally rear of the display period over two fields, into a plurality of divided sustain discharge period, the supply timing of the sustain pulses in the one field, adjacent 3. The display panel driving method according to claim 2, wherein the display lines are set to be the same in the display lines. In the address period in any one subfield in the subfield group and in the address period in a subfield arranged after the one subfield, each of the discharge cells or 3. The display panel driving method according to claim 2, wherein any one of the non-light emitting cells is set. The display of claim 2, characterized in that Ru is provided on the entire surface erase period for setting all of the discharge cells in the non-light emitting cells after the sustain discharge period in the sub-field at the end arranged in the sub-field group Panel drive method.

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