JP2007528553A5 - - Google Patents

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Publication number
JP2007528553A5
JP2007528553A5 JP2007502715A JP2007502715A JP2007528553A5 JP 2007528553 A5 JP2007528553 A5 JP 2007528553A5 JP 2007502715 A JP2007502715 A JP 2007502715A JP 2007502715 A JP2007502715 A JP 2007502715A JP 2007528553 A5 JP2007528553 A5 JP 2007528553A5
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JP
Japan
Prior art keywords
simulation
execution
design
verification
objects
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Pending
Application number
JP2007502715A
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English (en)
Japanese (ja)
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JP2007528553A (ja
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Priority claimed from KR1020040017476A external-priority patent/KR20040063845A/ko
Priority claimed from KR1020040093309A external-priority patent/KR20050090053A/ko
Priority claimed from KR1020050007330A external-priority patent/KR20050118107A/ko
Application filed filed Critical
Priority claimed from PCT/KR2005/000668 external-priority patent/WO2005093575A1/en
Publication of JP2007528553A publication Critical patent/JP2007528553A/ja
Publication of JP2007528553A5 publication Critical patent/JP2007528553A5/ja
Pending legal-status Critical Current

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JP2007502715A 2004-03-09 2005-03-09 検証性能と検証效率性を高める動的検証−基盤方式の検証装置及びこれを用いた検証方法論 Pending JP2007528553A (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR1020040017476A KR20040063845A (ko) 2001-09-14 2004-03-09 검증 성능을 높이는 시뮬레이션 기반의 검증 장치 및 이를이용한 시뮬레이션 방법
KR1020040019066A KR20040063846A (ko) 2001-09-14 2004-03-16 다양한 검증 플랫폼들의 통합 사용을 지원하는 검증 장치및 이를 이용한 검증 방법
KR20040055329 2004-07-12
KR1020040093309A KR20050090053A (ko) 2004-03-06 2004-11-08 검증 성능을 높이는 시뮬레이션 기반의 검증 장치 및 이를이용한 시뮬레이션 방법
KR1020050007330A KR20050118107A (ko) 2004-03-09 2005-01-24 검증 성능과 검증 효율성을 높이는 동적검증 기법 방식의검증 장치 및 이를 이용한 검증 방법론
PCT/KR2005/000668 WO2005093575A1 (en) 2004-03-09 2005-03-09 Dynamic-verification-based verification apparatus achieving high verification performance and verification efficency and the verification methodology using the same

Publications (2)

Publication Number Publication Date
JP2007528553A JP2007528553A (ja) 2007-10-11
JP2007528553A5 true JP2007528553A5 (de) 2008-04-24

Family

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Family Applications (1)

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JP2007502715A Pending JP2007528553A (ja) 2004-03-09 2005-03-09 検証性能と検証效率性を高める動的検証−基盤方式の検証装置及びこれを用いた検証方法論

Country Status (2)

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JP (1) JP2007528553A (de)
WO (1) WO2005093575A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8781808B2 (en) 2005-10-10 2014-07-15 Sei Yang Yang Prediction-based distributed parallel simulation method
CN100371910C (zh) * 2006-04-30 2008-02-27 华为技术有限公司 单板中本地版本软件的校验方法
KR101968214B1 (ko) * 2012-09-07 2019-04-11 삼성전자주식회사 사용자 프로그램 코드에 기반한 어써션 생성 장치 및 방법, 어써션을 이용한 프로세서 검증 장치 및 방법
CN103678114B (zh) * 2012-09-07 2018-11-02 三星电子株式会社 产生断言的设备和方法以及验证处理器的设备和方法
GB2524016B (en) * 2014-03-11 2021-02-17 Advanced Risc Mach Ltd Hardware simulation
US10061876B2 (en) 2014-12-23 2018-08-28 Board Of Trustees Of The University Of Illinois Bounded verification through discrepancy computations
CN109726507B (zh) * 2019-01-17 2023-04-18 湖南进芯电子科技有限公司 一种高效的多功能验证方法
CN111310396B (zh) * 2020-02-13 2023-10-03 深圳航天科技创新研究院 一种fpga虚拟平台及实现fpga虚拟平台的方法

Family Cites Families (15)

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Publication number Priority date Publication date Assignee Title
ATE265712T1 (de) * 1988-10-05 2004-05-15 Quickturn Design Systems Inc Verfahren zur verwendung einer elektronisch wiederkonfigurierbaren gatterfeld-logik und dadurch hergestelltes gerät
JPH0561933A (ja) * 1991-09-04 1993-03-12 Hokuriku Nippon Denki Software Kk 論理検証装置
JPH09265489A (ja) * 1996-03-29 1997-10-07 Fujitsu Ltd シミュレーション処理方法
JPH1010196A (ja) * 1996-06-21 1998-01-16 Hitachi Ltd 論理エミュレーション装置
JPH10124536A (ja) * 1996-10-17 1998-05-15 Matsushita Electric Ind Co Ltd シミュレーション再現方法
GB2318665B (en) * 1996-10-28 2000-06-28 Altera Corp Work group computing for electronic design automation
US6185707B1 (en) * 1998-11-13 2001-02-06 Knights Technology, Inc. IC test software system for mapping logical functional test data of logic integrated circuits to physical representation
JP2000250949A (ja) * 1999-02-26 2000-09-14 Matsushita Electric Ind Co Ltd シミュレーション装置
JP3178458B2 (ja) * 1999-03-31 2001-06-18 日本電気株式会社 回路シミュレーション装置および方法
US6678645B1 (en) * 1999-10-28 2004-01-13 Advantest Corp. Method and apparatus for SoC design validation
US6675310B1 (en) * 2000-05-04 2004-01-06 Xilinx, Inc. Combined waveform and data entry apparatus and method for facilitating fast behavorial verification of digital hardware designs
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JP2003085235A (ja) * 2001-09-11 2003-03-20 Matsushita Electric Ind Co Ltd シミュレーション方法および装置
US6658633B2 (en) * 2001-10-03 2003-12-02 International Business Machines Corporation Automated system-on-chip integrated circuit design verification system
WO2003036523A1 (fr) * 2001-10-24 2003-05-01 Renesas Technology Corp. Procede et programme de simulation et procede d'affichage

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