JP2007528553A5

JP2007528553A5 -

Info

Publication number: JP2007528553A5
Application number: JP2007502715A
Authority: JP
Filing date: 2005-03-09
Publication date: 2008-04-24

Claims

  In the verification method to find the existence of one or more design errors present in the gate level netlist generated by design code and synthesis through simulation,
  The simulation is composed of a primary simulation stage in the previous simulation stage and one or more simulation stages performed after the primary simulation in the subsequent simulation stage.
  In the primary simulation in the preceding simulation stage, while performing the primary simulation, one or more simulations performed after the primary simulation in the subsequent simulation stage are performed with one or more specific simulation sections, the design code, and the synthesis. The minimum information necessary to enable simulation to be performed on one or more design blocks existing in the gate level netlist generated in step 1 is automatically performed in the primary simulation process of the previous simulation stage. Additional code and additional circuits are added to the gate code netlist generated by design code and synthesis using an automated method using verification software, and the first simulation in the previous simulation stage is performed as described above. While collecting minimal information Promptly performed, using this collected information, the verification method of performing a simulation of one or more times to be performed in the primary simulation after the subsequent simulation phase.

In the verification method to find the existence of one or more design errors that exist in the gate level netlist generated by the above design code or synthesis through simulation,
  The simulation is composed of a primary simulation stage in the previous simulation stage and one or more simulation stages performed after the primary simulation in the subsequent simulation stage.
  Collect all input and I / O values of one or more design blocks in the above design code or gate level netlist generated by synthesis while performing the first simulation of the previous simulation stage in the entire simulation time At the same time, collect state information of one or more design blocks above at one or more specific simulation points,
  The collected input and input / output values are used on the test bench, the state information of the one or more design blocks is used at least once in the initial state, and the simulation is performed after the first simulation in the subsequent simulation stage. A verification method characterized in that at least one simulation execution is started at a time other than simulation time 0 for one or more design blocks existing in a design level or a gate level netlist generated by synthesis.

At least one simulation execution for one or more design blocks existing in the design code or the gate level netlist generated by synthesis in one or more simulation stages performed after the first simulation in the latter simulation stage 3. The verification method according to claim 1, wherein visibility is ensured by dumping values for one or more arbitrary signals or variables existing in the one or more design blocks.

The total time of one or more specific simulation time points for collecting the state information of the design block is smaller than the total simulation time of the primary simulation in the previous simulation stage,
At least one simulation execution for one or more design blocks existing in the design code or the gate level netlist generated by synthesis in one or more simulation stages performed after the first simulation in the latter simulation stage To obtain a dump value for one or more arbitrary signals or variables present in one or more design blocks, and through the obtained dump value, 1 in the netlist of the gate level generated by the design code or synthesis. 3. The verification method according to claim 2, wherein the presence or absence of the above design error is found.

The state information of the above design block is the minimum state information,
The total time of one or more specific simulation time points for collecting the state information of the design block is smaller than the total simulation time of the primary simulation in the previous simulation stage,
At least one simulation execution for one or more design blocks existing in the design code or the gate level netlist generated by synthesis in one or more simulation stages performed after the first simulation in the latter simulation stage To obtain a dump value for one or more arbitrary signals or variables present in one or more design blocks, and through the obtained dump value, 1 in the netlist of the gate level generated by the design code or synthesis. 3. The verification method according to claim 2, wherein the presence or absence of the above design error is found.

In a verification method for performing design verification through simulation execution using any one or more simulators,
  The above simulation is composed of a primary simulation stage in the preceding simulation stage and one or more simulation stages performed after the primary simulation in the subsequent simulation stage.
  The simulation performed in the primary simulation stage of the preceding simulation stage is a simulation for a design with a higher abstraction level than the simulation performed in one or more simulation stages performed after the primary simulation of the subsequent simulation stage.
  The simulation performed in one or more simulation stages performed after the first simulation in the latter simulation stage is a simulation for a design with a lower abstraction level than the simulation performed in the first simulation stage in the preceding simulation stage,
  Simulation with a design with a lower abstraction level than the simulation performed in the first simulation stage of the preceding simulation stage for simulations performed in one or more simulation stages performed after the first simulation in the latter simulation stage. Collect state information for one or more design objects collected at one or more simulation points that are not time 0,
  A verification method for performing simulation performed in one or more simulation stages performed after the first simulation in the subsequent simulation stage using the collected state information for one or more design objects.

In a verification method for performing design verification through simulation execution using any one or more simulators,
  The above simulation is composed of a primary simulation stage in the preceding simulation stage and one or more simulation stages performed after the primary simulation in the subsequent simulation stage.
  The simulation performed in the primary simulation stage of the preceding simulation stage is a simulation for a design with a higher abstraction level than the simulation performed in one or more simulation stages performed after the primary simulation of the subsequent simulation stage.
  The simulation performed in one or more simulation stages performed after the first simulation in the latter simulation stage is a simulation for a design with a lower abstraction level than the simulation performed in the first simulation stage in the preceding simulation stage,
  Simulation with a design with a lower abstraction level than the simulation performed in the first simulation stage of the preceding simulation stage for simulations performed in one or more simulation stages performed after the first simulation in the latter simulation stage. Collect state information for one or more design objects collected at one or more simulation points that are not time 0, and at the same time, all inputs and input / output values or all inputs and outputs for the one or more design objects over the entire simulation time. Collect input and output values
  Using the collected status information for one or more design objects and all the collected input and input / output values or all the input and output and input / output values, perform the simulation after the first simulation in the subsequent simulation stage. A verification method that performs a simulation performed in one or more simulation stages.

The simulation at the preceding simulation stage is a transaction level simulation or a mixed action / register transmission simulation, and the simulation at the latter simulation stage is a register transmission level simulation, or
  The simulation in the preceding simulation stage is a register transmission level simulation or a register transmission / gate mixed level simulation, and the simulation in the latter simulation stage is a gate level simulation, or
  The simulation at the preceding simulation stage uses a simplified delay time model, and the simulation at the latter simulation stage uses a more accurate delay time model than the simplified delay time model. Or
  8. The verification method according to claim 6, wherein the simulation at the preceding simulation stage is cycle-based simulation, and the simulation at the latter simulation stage is event-driven simulation.

The simulation performed in one or more simulation stages performed after the first simulation is two or more times, and the two or more simulations are executed in parallel using two or more simulators. 6. The verification method according to any one of 6 and 7.

The simulation at the preceding simulation stage is a transaction level simulation or a mixed action / register transmission simulation, and the simulation at the latter simulation stage is a register transmission level simulation, or
  The simulation in the preceding simulation stage is a register transmission level simulation or a register transmission / gate mixed level simulation, and the simulation in the latter simulation stage is a gate level simulation, or
  The simulation at the preceding simulation stage uses a simplified delay time model, and the simulation at the latter simulation stage uses a more accurate delay time model than the simplified delay time model. Or
  The simulation at the preceding simulation stage is cycle-based simulation, and the simulation at the latter simulation stage is event-driven simulation.
  The simulation performed in one or more simulation steps performed after the first simulation is performed two or more times, and the two or more simulations are executed in parallel using two or more simulators. The verification method according to 7.

In a design verification apparatus comprising verification software running on any computer and a verification platform comprising one or more simulators or one or more simulation accelerators or one or more hardware emulators or one or more prototyping systems,
The verification software adds an additional code or additional circuit to the verification target design code or design circuit composed of two or more design objects through an automated method, and adds the design code or design circuit on the verification platform. It can be performed together with code and additional circuits, enabling dynamic information to be collected at one or more specific verification points during one or more verification executions (simulation execution or simulation acceleration execution)
By reusing this collected dynamic information for verification execution (simulation execution or simulation acceleration execution) that is performed after one or more design objects have been changed, two or more existing code and design circuits to be verified are present. One or more design objects that have not been changed in the design object are the ones at the time of the start verification at the time of verification execution (simulation execution or simulation acceleration execution) in the verification execution (simulation execution or simulation acceleration execution) performed after the above change. The time required for the verification execution (simulation execution or simulation acceleration execution) performed after the above change can be shortened by not having to be executed from the verification time 0 Verification device.

In a verification method utilizing a verification platform comprising one or more simulators or one or more simulation accelerators or one or more hardware emulators or one or more prototyping systems,
  When expressing one or more design objects existing in the design code or design circuit to be verified consisting of two or more design objects as DO (m '),
  Add an additional code or additional circuit to the verification target design code or design circuit composed of the above two or more design objects so that the design code and design circuit can be executed along with the additional code or additional circuit on the verification platform. Dynamic information can be collected at one or more specific verification points during one or more verification executions (simulation execution or simulation acceleration execution)
  By reusing this collected dynamic information for verification execution (simulation execution or simulation acceleration execution) performed after the one or more design objects DO (m ') are changed, the verification design code and design circuit One or more design objects in the design object that are not changed among the two or more design objects existing in the above are verified execution (simulation execution or simulation acceleration execution) in the verification execution (simulation execution or simulation acceleration execution) performed after the above change. The time required for verification execution (simulation execution or simulation acceleration execution) performed after the above change can be shortened by making it unnecessary to execute from the verification time 0 at the start verification time of (execution) A verification method characterized by:

In a verification method utilizing a verification platform comprising one or more simulators or one or more simulation accelerators or one or more hardware emulators or one or more prototyping systems,
One or more design objects existing in the design code or design circuit to be verified consisting of two or more design objects are represented by DO (i), and changes are made in DO (i) above while the design verification process is in progress. The design object to be displayed is represented by DO (m ′), and the design object after the change of the above DO (m ′) is represented by DO (m),
  Add an additional code or additional circuit to the verification target design code or design circuit composed of the above two or more design objects so that the design code and design circuit can be executed along with the additional code or additional circuit on the verification platform. Start of one or more verification executions (simulation execution or simulation acceleration execution) From the verification point to the specific verification point, all input values, all output values, and all bidirectional input / output values of the above one or more design objects DO (i) Storing the state information of the one or more design objects DO (i) at the time of collection and verification that is one or more checkpoints;
  One or more design objects DO changed in the verification execution (simulation execution or simulation acceleration execution) performed after one or more design objects DO (m ') existing in the verification target design code or design circuit are changed All outputs of the above design object DO (m ') collected in the verification execution before the change (simulation execution or simulation acceleration execution) The result of the output value in all bidirectional inputs and outputs and the first change point are all input of the design object DO (m) collected in the verification execution process (simulation execution or simulation acceleration execution) before the change and all bidirectional input. All outputs and all bidirectional inputs of the one or more modified design objects DO (m) obtained by applying the input value at the output only to the one or more modified design objects DO (m). Results of output values in force and results of output values of all the above-mentioned design object DO (m ') collected in the verification execution (simulation execution or simulation acceleration execution) before change and output values in all bidirectional inputs and outputs While comparing and finding
  State information storage for one or more design objects DO (m) changed in the above is performed with one or more specific verifications, and changes obtained in the verification execution (simulation execution or simulation acceleration execution) process after the change have been made1 Utilize the state information for the design object DO (m) and the state information for one or more design objects that were not changed in the verification execution (simulation execution or simulation acceleration execution) process before the change, or Through the stage of utilizing state information for one or more design objects that were not changed in the verification execution (simulation execution or simulation acceleration execution) process before the change,
  At least one design object that is not changed among the two or more design objects existing in the design code or design circuit to be verified is verified by the verification execution (simulation execution or simulation acceleration execution) performed after the change. The time required for verification execution (simulation execution or simulation acceleration execution) that is performed after the above change is made by not requiring execution from the verification time 0 at the start verification time of execution (simulation execution or simulation acceleration execution) A verification method that can shorten the time.

In a verification method using a verification platform composed of two or more simulators, or one or more simulators and one or more hardware-based verification platforms,
  One or more design objects existing in the design code or design circuit to be verified composed of two or more design objects are represented by DO (i), and changes are made in DO (i) above while the design verification process is in progress Is represented by DO (m ′), and the design object after the change of DO (m ′) is represented by DO (m).
  Additional code or additional circuit is added to the verification target design code or design circuit consisting of the above two or more design objects, and the design code and design circuit are verified along with the additional code and additional circuit on the verification platform (simulation execution or (Simulation acceleration execution) and at least one verification execution (simulation execution or simulation acceleration execution) from the start verification point to the specific verification point all input values and all output values of the above one or more design objects (i) Collecting all bidirectional I / O values;
  All of the one or more design objects DO (m) modified in the verification execution (simulation execution or simulation acceleration execution) performed after one or more design objects existing in the verification target design code or design circuit are changed All outputs and all bidirectional inputs / outputs of the design object DO (m ') collected in the previous verification execution (simulation execution or simulation acceleration execution) The output value result and the first change point (td) of the above-mentioned design object DO are the results of all the outputs of one or more modified design objects DO (m) and the output values at all bidirectional inputs and outputs. find out by comparing all the outputs of (m ') and the output value results at all bidirectional inputs and outputs;
  For one or more design objects that have not been changed, the verification time at the start verification time of the verification execution (simulation execution or simulation acceleration execution) in the verification execution (simulation execution or simulation acceleration execution) performed after the change From 0 to the first change point (td), input at all inputs and inputs / outputs of one or more design objects that were collected in the previous verification execution (simulation execution or simulation acceleration execution) Performing by applying a value;
  From the first change point (td), verification is performed in a way that all design objects work together without reusing the dynamic information obtained in the verification execution (simulation execution or simulation acceleration execution) before the change. A verification method including a stage of performing (simulation execution or simulation acceleration execution).

  In a verification method using a verification platform composed of two or more simulators, or one or more simulators and one or more hardware-based verification platforms,
  One or more design objects existing in the design code or design circuit to be verified that consists of two or more design objects are represented by DO (i), and changes are made in DO (i) while the design verification process is in progress. The design object to be displayed is represented by DO (m ′), and the design object after the change of the above DO (m ′) is represented by DO (m),
  Additional code or additional circuit is added to the verification target design code or design circuit consisting of the above two or more design objects, and the design code and design circuit are verified along with the additional code and additional circuit on the verification platform (simulation execution or All the input values and all the output values of one or more design objects DO (i) above from the start verification time to the specific verification time of one or more verification executions (simulation execution or simulation acceleration execution) And storing all the bidirectional input / output values and storing simulation state information of the simulator that executes the one or more design objects DO (i) at the time of verification as one or more checkpoints;
  All of the one or more design objects DO (m) modified in the verification execution (simulation execution or simulation acceleration execution) performed after one or more design objects existing in the verification target design code or design circuit are changed All outputs and all bidirectional inputs / outputs of the design object DO (m ') collected in the previous verification execution (simulation execution or simulation acceleration execution) The input value is changed for all inputs and inputs / outputs of the design object DO (m ') collected during the verification execution (simulation execution or simulation acceleration execution) process before the change. All the outputs of the modified one or more design objects DO (m) obtained by applying to only one or more design objects DO (m) At the same time as comparing all the outputs of the design object DO (m ') collected in the verification execution (simulation execution or simulation acceleration execution) before the change and the output value results in all bidirectional inputs and outputs ,
  The simulation status information saved at the time of one or more specific simulations was not changed in the verification execution (simulation execution or simulation acceleration execution) after the change for one or more design objects DO (m) for which the above changes were made Use simulation state information saved in verification execution (simulation execution or simulation acceleration execution) before change for one or more design objects, or verification execution before change for one or more design objects that have not been changed ( Through the stage of utilizing the simulation state information saved in (Simulation execution or Simulation acceleration execution)
  Among the two or more design objects present in the verification target design code or design circuit, at least one design object that is not changed is a verification execution (simulation execution or simulation acceleration execution) performed after the change. Start of verification execution (simulation execution or simulation acceleration execution) Necessity of verification execution (simulation execution or simulation acceleration execution) performed after the above change by not having to be executed from verification time 0 at the time of verification A verification method that allows you to save time.

Changes to the one or more design objects DO (m ') in the dynamic information reused in the verification execution (simulation execution or simulation acceleration execution) performed after the one or more design object DO (m') is changed Changes that were collected at one or more verification times (Tr) other than the verification time 0 at the start of verification execution (simulation execution or simulation acceleration execution) at the time of previous verification execution (simulation execution or simulation acceleration execution) Contains state information for one or more design objects that must be
In the verification execution (simulation execution or simulation acceleration execution) performed after the one or more design objects DO (m ') are changed, the verification execution performed before the change to the one or more design objects DO (m') The state information of one or more design objects that do not change as the state information in the Tr of the one or more design objects that do not become the change collected in (Simulation Execution or Simulation Acceleration Execution) does not change because the state information of one or more design objects that do not change is restored The one or more design objects are not executed from the verification time 0 at the time of start verification of the verification execution (simulation execution or simulation acceleration execution), but are executed from the Tr. Method of verification.

  When expressing one or more design objects that do not change as DO (u),
  At the time of verification, which is one or more checkpoints for the one or more design objects DO (i) that exist in the design code or design circuit to be verified, the state information of the design objects is saved before the change (simulation execution or simulation). Accelerated execution) at the start of verification execution (simulation execution or simulation acceleration execution) at the verification time (Tr) of 1 or more other than the verification time 0 at the time of verification
  In the verification execution (simulation execution or simulation acceleration execution) that is performed after the change to the one or more design objects DO (m ′), one or more design objects DO (u) that do not change the above-mentioned verification execution (simulation execution or simulation). It is not executed from the verification time 0 at the start verification time of (acceleration execution), and it does not become the above change collected in the verification execution (simulation execution simulation acceleration execution) before the above change for the design object DO (m ′) of 1 or more 1 14. The verification method according to claim 13, wherein the verification method is executed from the Tr through restoration with the state information of the design object DO (u).

  When expressing one or more design objects that do not change as DO (u),
  Pre-change verification execution (simulation execution or simulation acceleration execution) at the time of verification, which is the check point for the simulator that performs simulation for one or more design objects existing in the verification target design code or design circuit At the start of the verification execution (simulation execution or simulation acceleration execution) at the verification time (Tr) of 1 or more other than the verification time 0 at the time of verification
  In the verification execution (simulation execution or simulation acceleration execution) performed after the change to the one or more design objects DO (m ′), one or more design objects DO (u) that do not change the above are executed in the verification execution (simulation execution or simulation). Acceleration execution) is not executed from the verification time 0 at the time of start verification, and does not result in the above changes collected in the verification execution (simulation execution or simulation acceleration execution) before the above change for the design object DO (m ') of 1 or more 16. The verification method according to claim 15, wherein the verification method is executed from the Tr through restoration to simulation state information of a simulator that performs simulation for one or more design objects DO (u).

Changes to the one or more design objects DO (m ') in the dynamic information reused in the verification execution (simulation execution or simulation acceleration execution) performed after the one or more design object DO (m') is changed Information on all input, output, and input / output values of one or more design objects DO (m ') collected in the previous verification execution (simulation execution or simulation acceleration execution) process is included. 13. The verification method according to claim 12, characterized by:

  In a verification method using a verification platform comprising one or more simulators or one or more simulation accelerators or one or more hardware emulators or one or more prototyping systems,
  One or more design objects existing in the design code or design circuit to be verified that consists of two or more design objects are represented by DO (i), and changes are made in DO (i) while the design verification process is in progress. The design object to be displayed is represented by DO (m ′), the design object after the change of DO (m ′) is represented by DO (m), and verification consisting of the above two or more design objects When expressing one or more design objects that do not change in the target design code or design circuit as DO (u),
  Add additional code or additional circuit to the verification target design code or design circuit consisting of the above two or more design objects so that the design code and design circuit can be executed along with the additional code or additional circuit on the verification platform. All input values, all output values, and all bidirectional input / output values of the above one or more design objects DO (i) from the start verification point to the specific verification point The stage of collecting,
  One or more design objects DO changed in the verification execution (simulation execution or simulation acceleration execution) performed after one or more design objects DO (m ') existing in the verification target design code or design circuit are changed All outputs of the above design object DO (m ') collected in the verification execution before the change (simulation execution or simulation acceleration execution) The result of the output value in all bidirectional inputs and outputs and the first change point are shown for all inputs and inputs / outputs of the design object DO (m ') collected during the verification execution (simulation execution or simulation acceleration execution) process before the change. All the outputs of the above-mentioned one or more modified design objects DO (m) obtained by applying the input value to only one or more of the above-mentioned modified design objects DO (m) and the outputs at all bidirectional inputs / outputs value And compare the results of all the outputs of the design object DO (m ') collected in the verification execution (simulation execution or simulation acceleration execution) process before the change and the output values at all bidirectional inputs and outputs At the same time
  State information is saved for one or more design objects DO (m) that have been changed at one or more specific verification points, and changes obtained during the verification execution (simulation execution or simulation acceleration execution) after the change were made. Through the stage of utilizing state information for one or more design objects DO (m)
  In the verification execution (simulation execution or simulation acceleration execution) that proceeds after one or more design objects are changed, the design object DO (u) that exists in the verification target design code or design circuit is verified (simulation execution). Alternatively, the time required for verification execution (simulation execution or simulation acceleration execution) to be performed after the above-mentioned change can be shortened by not requiring execution from the verification time 0 at the start verification time of simulation acceleration execution). Verification method that allows you to

  In a verification method using a verification platform composed of two or more simulators, or one or more simulators and one or more hardware-based verification platforms,
  One or more design objects existing in the design code or design circuit to be verified consisting of two or more design objects are represented by DO (i), and changes are made in DO (i) above while the design verification process is in progress. The design object to be displayed is represented by DO (m ′), the design object after the change of DO (m ′) is represented by DO (m), and verification consisting of the above two or more design objects When one or more design objects that are not changed in the target design code or design circuit are represented by DO (u),
  Add an additional code or additional circuit to the verification target design code or design circuit composed of the above two or more design objects so that the design code and design circuit can be executed together with the additional code or additional circuit on the verification platform. Collecting all input values, all output values, and all bidirectional I / O values of the above one or more design objects from the start verification point to the specific verification point at the start of more than one verification execution (simulation execution or simulation acceleration execution) When,
  One or more design objects DO changed in the verification execution (simulation execution or simulation acceleration execution) performed after one or more design objects DO (m ') existing in the verification target design code or design circuit are changed All outputs of the above design object DO (m ') collected in the verification execution before the change (simulation execution or simulation acceleration execution) The results of output values in all bidirectional I / O and the first change time were collected in the verification execution (simulation execution or simulation acceleration execution) process after the change in the verification execution process (simulation execution or simulation acceleration execution) after the change. The above obtained by applying all the inputs and input values at the input / output of the design object DO (m ') only to one or more design objects DO (m) that have been changed The above design object collected in the process of verification execution (simulation execution or simulation acceleration execution) before the change and the results of all the outputs of one or more modified design objects DO (m) and the output values at all bidirectional inputs and outputs At the same time finding and comparing the results of all outputs of DO (m ') and the output values of all bidirectional inputs and outputs,
  Through the stage of utilizing the simulation state information saved in the verification execution (simulation execution or simulation acceleration execution) after the change to one or more design objects DO (m) where the change was made,
  In the verification execution (simulation execution or simulation acceleration execution) that proceeds after one or more design objects are changed, the design object DO (u) that exists in the design code to be verified and the design circuit is verified (simulation execution or simulation execution). The time required for verification execution (simulation execution or simulation acceleration execution) performed after the above change can be shortened by making it unnecessary to execute from the verification time 0 at the start verification time of (acceleration execution) How to verify.

  One or more design objects existing in the design code or design circuit to be verified that consists of two or more design objects are represented by DO (i), and changes are made in DO (i) while the design verification process is in progress. Design object to be displayed is represented by DO (m '), and one or more design objects that are not changed in the verification target design code or design circuit composed of the above two or more design objects are represented by DO (u) In case,
  Before changing the state information storage of the design object at the time of verification that becomes one or more checkpoints for the one or more design objects DO (i) existing in the design code or design circuit to be verified through the additional code or additional circuit In the verification execution (simulation execution or simulation acceleration execution), start at the verification execution (simulation execution or simulation acceleration execution)
  In the verification execution (simulation execution or simulation acceleration execution) that is performed after changing one or more design objects DO (m ') through the above additional code or additional circuit, one or more design objects DO (u) that do not change are verified. (Simulation execution or simulation acceleration execution) Collected in the verification execution (simulation execution or simulation acceleration execution) before the change for the design object DO (m ') above 1 without being executed from the verification time 0 at the start verification time. 12. The verification apparatus according to claim 11, wherein the verification apparatus is executed from the Tr through state information restoration of one or more design objects DO (u) that are not changed.

  DO (i) represents one or more design objects existing in the design code or design circuit to be verified, which consists of two or more design objects, and the design verification process is in progress. The design object to be performed is represented by DO (m '), and one or more design objects that are not changed in the verification target design code or design circuit composed of the above two or more design objects are represented by DO (u). When expressing
  Simulation for the design object DO (i) at the time of verification that becomes one or more checkpoints for the one or more design objects DO (i) existing in the design code or circuit to be verified through the additional code or circuit The simulation state information storage of the simulator that performs the simulation is executed at the start of the verification execution (simulation execution or simulation acceleration execution) in the previous verification execution (simulation execution or simulation acceleration execution). )
  In the verification execution (simulation execution or simulation acceleration execution) that is performed after changing one or more design objects DO (m ') through the above additional code or additional circuit, one or more design objects DO (u) that do not change are verified. (Simulation execution or simulation acceleration execution) Collected in the verification execution (simulation execution or simulation acceleration execution) before the change for the design object DO (m ') above 1 without being executed from the verification time 0 at the start verification time. 12. The verification apparatus according to claim 11, wherein the verification apparatus is executed from the Tr through simulation state information restoration of a simulator that performs simulation for one or more design objects DO (u) that are not changed.

  The primary simulation in the preceding simulation stage is a simulation through simulation acceleration training using a hardware emulator or a simulation accelerator, and one or more simulations performed after the primary simulation in the subsequent simulation stage are one or more. It is a simulation that uses only the simulator of
  The state information of the above design block is the minimum state,
  The total time of one or more specific simulation time points for collecting the state information of the design block is smaller than the total simulation time of the primary simulation in the previous simulation stage,
  At least one simulation execution for one or more design blocks existing in the design code or the gate level netlist generated by synthesis in one or more simulation stages performed after the first simulation in the latter simulation stage To obtain a dump value for one or more arbitrary signals or variables present in one or more design blocks, and through the obtained dump value, 1 in the netlist of the gate level generated by the design code or synthesis. 3. The verification method according to claim 2, wherein the presence or absence of the above design error is found.