JP2007524196A5 - - Google Patents
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- JP2007524196A5 JP2007524196A5 JP2006520397A JP2006520397A JP2007524196A5 JP 2007524196 A5 JP2007524196 A5 JP 2007524196A5 JP 2006520397 A JP2006520397 A JP 2006520397A JP 2006520397 A JP2006520397 A JP 2006520397A JP 2007524196 A5 JP2007524196 A5 JP 2007524196A5
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- circuit board
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- interposer
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- 239000004020 conductor Substances 0.000 claims 53
- 239000000758 substrate Substances 0.000 claims 6
- 230000000875 corresponding Effects 0.000 claims 2
- 239000003989 dielectric material Substances 0.000 claims 2
- 102100020572 RUBCNL Human genes 0.000 claims 1
- 101710044922 RUBCNL Proteins 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
Claims (40)
第1回路基板であって、(a)第1差動相互接続経路と、(b)前記第1回路基板の表面の第1信号パッドと、(c)同じく前記第1回路基板の前記表面の第2信号パッドとを備えた第1回路基板であって、前記第1差動相互接続経路は、前記第1信号パッドに電気接続された第1信号経路と前記第2信号パッドに電気接続された第2信号経路とを備えている、第1回路基板と、
第2差動相互接続経路を備えた第2回路基板と、
前記第1差動相互接続経路を前記第2差動相互接続経路と電気接続させるコネクタであって、
第1面と前記第1面とは反対側の第2面とを有するインターポーザーであって、前記第1面は前記第1回路基板の前記表面に面する、インターポーザーと、
前記インターポーザーの前記第2面に隣接する端部を有する第1導体と、
前記第1導体と平行であり長さがほぼ等しい第2導体であって、同じく前記インターポーザーの前記第2面に隣接する端部を有する第2導体と、
前記第1導体と前記第2導体との間に配置される誘電材料と、
導体接触部と基板接触部と前記導体接触部と前記基板接触部との間の中間部とを有する第1の細長いコンタクト部材であって、前記導体接触部は前記第1導体の前記端部と物理的に接触し、前記基板接触部は前記第1信号パッドの表面と物理的に接触し前記表面を押し付けるが前記第1信号パッドに固定されず、そして前記中間部は前記インターポーザーの前記第1面から前記インターポーザーの前記第2面まで延びる穴内に配置され、ここで前記第1信号パッドは前記第1コンタクト部材に力を加え、前記第1コンタクト部材は限定された程度まで前記力の方向に自由に移動し、また前記力は前記第1回路基板の前記表面に対して垂直の方向である、第1の細長いコンタクト部材と、
導体接触部と基板接触部と前記導体接触部と前記基板接触部との間の中間部とを有する第2の細長いコンタクト部材であって、前記導体接触部は前記第2導体の前記第1端部と物理的に接触し、前記基板接触部は前記第2信号パッドの上表面と物理的に接触し前記表面を押し付けるが前記第2信号パッドに固定されず、そして前記中間部は前記インターポーザーの前記第1面から前記インターポーザーの前記第2面まで延びる穴内に配置され、ここで前記第2信号パッドは前記第2コンタクト部材に力を加え、前記第2コンタクト部
材は限定された程度まで前記力の方向に自由に移動し、また前記力は前記第1回路基板の前記表面に対して垂直の方向である、第2の細長いコンタクト部材と、を備えたコネクタと、
を備えた相互接続システム。 An interconnection system,
A first circuit board, comprising: (a) a first differential interconnection path; (b) a first signal pad on the surface of the first circuit board; and (c) a surface of the surface of the first circuit board. A first circuit board having a second signal pad, wherein the first differential interconnection path is electrically connected to the first signal path and the second signal pad electrically connected to the first signal pad; A first circuit board having a second signal path;
A second circuit board with a second differential interconnect path;
A connector for electrically connecting the first differential interconnect path with the second differential interconnect path;
An interposer having a first surface and a second surface opposite to the first surface, wherein the first surface faces the surface of the first circuit board;
A first conductor having an end adjacent to the second surface of the interposer;
A second conductor that is parallel to and substantially equal in length to the first conductor and also has an end adjacent to the second surface of the interposer;
A dielectric material disposed between the first conductor and the second conductor;
A first elongate contact member having a conductor contact portion, a substrate contact portion, and an intermediate portion between the conductor contact portion and the substrate contact portion, wherein the conductor contact portion and the end portion of the first conductor The substrate contact portion physically contacts and presses against the surface of the first signal pad but is not fixed to the first signal pad, and the intermediate portion is the first portion of the interposer. Disposed in a hole extending from one surface to the second surface of the interposer, wherein the first signal pad applies a force to the first contact member, and the first contact member is applied to the force to a limited extent. A first elongate contact member that is free to move in a direction and wherein the force is in a direction perpendicular to the surface of the first circuit board;
A second elongate contact member having a conductor contact portion, a substrate contact portion, and an intermediate portion between the conductor contact portion and the substrate contact portion, wherein the conductor contact portion is the first end of the second conductor. The substrate contact portion physically contacts the upper surface of the second signal pad and presses the surface but is not fixed to the second signal pad, and the intermediate portion is the interposer. Is disposed in a hole extending from the first surface to the second surface of the interposer, wherein the second signal pad applies a force to the second contact member and the second contact member is limited to a limited extent. A second elongate contact member that is free to move in the direction of the force, and wherein the force is in a direction perpendicular to the surface of the first circuit board;
Interconnect system with.
M個の溝セットが配置された第1面であって、前記M個の溝の各々は前記第1面の第1縁から前記第1面の第2縁まで延びる、第1面と、
N個の溝セットが配置された第2面であって、前記N個の溝の各々は前記第2面の第1縁から前記第2面の第2縁まで延びる、第2面と、
前記スペーサーを前記コネクタの一部に取り付けるため前記スペーサーの面から外側に突き出た細長いフィンガーと、
を備えたスペーサー。 A spacer for the connector,
A first surface on which M groove sets are disposed, each of the M grooves extending from a first edge of the first surface to a second edge of the first surface;
A second surface on which N groove sets are disposed, each of the N grooves extending from a first edge of the second surface to a second edge of the second surface;
Elongate fingers protruding outward from the surface of the spacer to attach the spacer to a portion of the connector;
With spacer.
各々が第1面と前記第1面とは反対側の第2面とを有する、第1、第2および第3スペーサーと、
第1の回路基板であって、前記第1および第2スペーサーの間に、前記第1の回路基板の第1面は前記第1スペーサーの前記第2面に当接し、前記第1の回路基板の第2面は前記第2スペーサーの前記第1面に当接するように挟まれ、前記第1の回路基板の前記第2面には信号導体セットが配置され、前記第1の回路基板の前記第2面に配置された前記信号導体の各々は前記第1の回路基板の前記第2面の第1縁に隣接する第1端部と、前記第1の回路基板の前記第2面の第2縁に隣接する第2端部と、前記第1端部と前記第2端部との間の中間部とを有する、第1の回路基板と、
第2の回路基板であって、前記第2および第3スペーサーの間に、前記第2の回路基板の第1面は前記第2スペーサーの前記第2面に当接し、前記第2の回路基板の第2面は前記第3スペーサーの前記第1面に当接するように挟まれ、前記第2の回路基板の前記第1面には信号導体セットが配置され、前記第2の回路基板の前記第1面に配置された前記信号導体の各々は前記第2の回路基板の前記第1面の第1縁に隣接する第1端部と、前記第2の回路基板の前記第1面の第2縁に隣接する第2端部と、前記第1端部と前記第2端部との間の中間部とを有する、第2の回路基板と、を備え、
前記第1の回路基板の前記第2面の前記第1縁は、前記第2の回路基板の前記第1面の前記第1縁と平行でありまたこれから離れて位置しており、
前記第2の回路基板の前記第1面に配置された前記信号導体のいずれも、前記第1の回路基板の前記第2面に配置された前記信号導体のいずれをも反映しない、コネクタ。 A connector for electrically connecting a signal path on the first circuit board to a signal path on the second circuit board,
First, second and third spacers each having a first surface and a second surface opposite the first surface;
A first circuit board, wherein the first surface of the first circuit board is in contact with the second surface of the first spacer between the first and second spacers, and the first circuit board The second surface of the first circuit board is sandwiched so as to contact the first surface of the second spacer, and a signal conductor set is disposed on the second surface of the first circuit board. Each of the signal conductors disposed on the second surface includes a first end adjacent to the first edge of the second surface of the first circuit board and a second end of the second surface of the first circuit board. A first circuit board having a second end adjacent to two edges and an intermediate portion between the first end and the second end;
A second circuit board, wherein the first surface of the second circuit board is in contact with the second surface of the second spacer between the second and third spacers, and the second circuit board. The second surface of the second circuit board is sandwiched so as to contact the first surface of the third spacer, a signal conductor set is disposed on the first surface of the second circuit board, and the second circuit board includes the signal conductor set. Each of the signal conductors disposed on the first surface includes a first end adjacent to a first edge of the first surface of the second circuit board, and a first end of the first surface of the second circuit board. A second circuit board having a second end adjacent to two edges and an intermediate portion between the first end and the second end;
The first edge of the second surface of the first circuit board is parallel to and away from the first edge of the first surface of the second circuit board;
None of the signal conductors disposed on the first surface of the second circuit board reflects any of the signal conductors disposed on the second surface of the first circuit board.
前記第2スペーサーの前記第2面には第2セットの溝が、前記溝の各々が前記第2の回路基板の前記第1面に配置された前記信号導体のうちの1つを反映するように配置される、請求項16に記載のコネクタ。 A first set of grooves on the first surface of the second spacer such that each of the grooves reflects one of the signal conductors disposed on the second surface of the first circuit board. Placed in
A second set of grooves on the second surface of the second spacer so that each of the grooves reflects one of the signal conductors disposed on the first surface of the second circuit board. The connector according to claim 16, wherein
複数のプリント回路基板であって、各々がその両面に各々配置される少なくとも1対の導電体を有する、複数のプリント回路基板と、
2つの端部を有する列として互いに隣接して配置されるようにされた複数のスペーサーであって、各スペーサーは、前記複数のプリント回路基板のうちの1つが、そのスペーサーと前記複数のスペーサーのうちの別のスペーサーとの間に配置され得るようにされ、前記複数のスペーサーの各々の各面はその隣接するプリント回路基板の前記導電体の各々のための溝を含み、前記溝はそのスペーサーと前記隣接するプリント回路基板の前記導体との間に空気スペースを設けるようにされ、前記導電体の各々は第1および第2端部を有し
、前記プリント回路基板と前記複数のスペーサーとは、第1面上で、前記複数の導電体の前記第1端部のすべてを露出させ、また第2面上で、前記複数の導電体の前記第2端部のすべてを露出させるようにされる、複数のスペーサーと、
前記複数のスペーサー列の前記両端部に各々隣接して配置されるようにされた一対のエンドピースと、
複数のセルと、
各々が前記第1および第2面に隣接して配置されるようにされた第1および第2インターポーザーであって、各インターポーザーは前記複数のプリント回路基板の各導電体対のための前記複数のセルのうちの1つを受容するようにされた開口部を有する、第1および第2インターポーザーと、
複数の導電コンタクトであって、各導電コンタクトは第1および第2端部を有し、前記第1および第2インターポーザーの前記セルのうちの1つに配置されるようにされ、ここで、前記複数の導電コンタクトの各々の前記第1端部は前記複数のプリント回路基板の前記導体対のうちの1つに電気接続し、また前記複数の導電コンタクトの各々の前記第2端部は各々のインターポーザーの各々のセルを通って前記インターポーザーの面を越えて延びる、複数の導電コンタクトと、
を備えたコネクタ。 A connector,
A plurality of printed circuit boards, each having at least one pair of conductors each disposed on both sides thereof; and
A plurality of spacers arranged adjacent to each other in a row having two ends, each spacer comprising one of the plurality of printed circuit boards, wherein the spacer and the plurality of spacers Each of the plurality of spacers includes a groove for each of the conductors of its adjacent printed circuit board, the groove being the spacer. And an air space between the conductor of the adjacent printed circuit board and each of the conductors has first and second ends, and the printed circuit board and the plurality of spacers are And exposing all of the first ends of the plurality of conductors on the first surface and exposing all of the second ends of the plurality of conductors on the second surface. , And a plurality of spacers,
A pair of end pieces arranged to be adjacent to both ends of the plurality of spacer rows,
Multiple cells,
First and second interposers, each disposed adjacent to the first and second surfaces, each interposer being configured for each conductor pair of the plurality of printed circuit boards. First and second interposers having an opening adapted to receive one of a plurality of cells;
A plurality of conductive contacts, each conductive contact having first and second ends, wherein the conductive contacts are disposed in one of the cells of the first and second interposers, wherein The first end of each of the plurality of conductive contacts is electrically connected to one of the conductor pairs of the plurality of printed circuit boards, and the second end of each of the plurality of conductive contacts is each A plurality of conductive contacts extending through each cell of the interposer and beyond the surface of the interposer;
With connector.
複数のプリント回路基板であって、各々がその両面に各々配置された少なくとも一対の導電体を有する複数のプリント回路基板を提供することと、
複数のスペーサーを2つの端部を有する列として互いに隣接させて配置することであって、各スペーサーは、前記複数のプリント回路基板のうちの1つが、そのスペーサーと前記複数のスペーサーのうちの別のスペーサーとの間に配置され得るようにされ、前記複数のスペーサーの各々の各面は隣接するプリント回路基板の前記導電体の各々のための溝を含み、前記溝はそのスペーサーと前記隣接するプリント回路基板の前記導体との間に空気スペースを設けるようにされ、前記導電体の各々は第1および第2端部を有し、前記プリント回路基板と前記複数のスペーサーとは、第1面上で、前記複数の導電体の前記第1端部のすべてを露出させ、また第2面上で、前記複数の導電体の前記第2端部のすべてを露出させるようにされる、複数のスペーサーを配置することと、
一対のエンドピースを前記複数のスペーサー列の前記両端部に各々隣接して配置することと、
第1および第2インターポーザーを前記第1および第2面に各々隣接して配置することと、前記第1および第2インターポーザー内に複数のセルを配置することであって、各インターポーザーは、前記複数のプリント回路基板の各導体対のための前記複数のセルのうちの1つを受容するようにされた開口部を有する、第1および第2インターポーザーを配することと、
複数の導電コンタクトを提供することであって、各導電コンタクトは第1および第2端部を有しまた前記セルのうちの1つに配置され、ここで、前記複数の導電コンタクトの各々の前記第1端部は前記複数のプリント回路基板の前記導電体対のうちの1つに電気的に接触し、また前記複数の導電コンタクトの各々の前記第2端部は各々のセルを通って前記インターポーザーの面を越えて延びる、複数の導電コンタクトを提供することと、
を包含する方法。 A method of manufacturing an interconnection system comprising:
Providing a plurality of printed circuit boards, each having at least a pair of conductors each disposed on both sides thereof;
A plurality of spacers arranged adjacent to each other in a row having two ends, wherein each of the spacers is one of the plurality of printed circuit boards separated from the spacer and the plurality of spacers; Each of the plurality of spacers includes a groove for each of the conductors of an adjacent printed circuit board, the groove being adjacent to the spacer. An air space is provided between the conductors of the printed circuit board, each of the conductors has first and second ends, and the printed circuit board and the plurality of spacers have a first surface. A plurality of the first ends of the plurality of conductors are exposed, and on the second surface, all of the second ends of the plurality of conductors are exposed. And placing the pacer,
Arranging a pair of end pieces adjacent to each of the both ends of the plurality of spacer rows;
Disposing first and second interposers adjacent to the first and second surfaces, and disposing a plurality of cells in the first and second interposers, wherein each interposer Disposing first and second interposers having openings adapted to receive one of the plurality of cells for each conductor pair of the plurality of printed circuit boards;
Providing a plurality of conductive contacts, each conductive contact having first and second ends and disposed in one of the cells, wherein the each of the plurality of conductive contacts The first end is in electrical contact with one of the conductor pairs of the plurality of printed circuit boards, and the second end of each of the plurality of conductive contacts passes through each cell and the first end. Providing a plurality of conductive contacts extending beyond the face of the interposer;
Including the method.
エンドプレートを提供することをさらに包含する、請求項32に記載の方法。 35. The method of claim 32, further comprising providing an end plate to receive one of the interposers and engage the end cap.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US48758003P | 2003-07-17 | 2003-07-17 | |
PCT/US2004/023098 WO2005011062A2 (en) | 2003-07-17 | 2004-07-19 | High-speed electrical connector |
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Publication Number | Publication Date |
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JP2007524196A JP2007524196A (en) | 2007-08-23 |
JP2007524196A5 true JP2007524196A5 (en) | 2007-10-04 |
JP4570619B2 JP4570619B2 (en) | 2010-10-27 |
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JP2006520397A Expired - Fee Related JP4570619B2 (en) | 2003-07-17 | 2004-07-19 | High speed electrical connector |
JP2006520396A Expired - Fee Related JP4590406B2 (en) | 2003-07-17 | 2004-07-19 | High speed electrical connector |
JP2010153286A Expired - Fee Related JP5027907B2 (en) | 2003-07-17 | 2010-07-05 | High speed electrical connector |
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JP2006520396A Expired - Fee Related JP4590406B2 (en) | 2003-07-17 | 2004-07-19 | High speed electrical connector |
JP2010153286A Expired - Fee Related JP5027907B2 (en) | 2003-07-17 | 2010-07-05 | High speed electrical connector |
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EP (2) | EP1652273A4 (en) |
JP (3) | JP4570619B2 (en) |
AU (2) | AU2004260455B8 (en) |
CA (2) | CA2532141C (en) |
WO (2) | WO2005011061A2 (en) |
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US6267604B1 (en) * | 2000-02-03 | 2001-07-31 | Tyco Electronics Corporation | Electrical connector including a housing that holds parallel circuit boards |
US6843657B2 (en) * | 2001-01-12 | 2005-01-18 | Litton Systems Inc. | High speed, high density interconnect system for differential and single-ended transmission applications |
JP4387943B2 (en) * | 2002-07-24 | 2009-12-24 | ウィンチェスター・エレクトロニクス・コーポレイション | Interconnect system |
US6712648B2 (en) * | 2002-07-24 | 2004-03-30 | Litton Systems, Inc. | Laminate electrical interconnect system |
-
2004
- 2004-07-19 WO PCT/US2004/023096 patent/WO2005011061A2/en active Application Filing
- 2004-07-19 AU AU2004260455A patent/AU2004260455B8/en not_active Ceased
- 2004-07-19 CA CA2532141A patent/CA2532141C/en not_active Expired - Fee Related
- 2004-07-19 WO PCT/US2004/023098 patent/WO2005011062A2/en active Search and Examination
- 2004-07-19 JP JP2006520397A patent/JP4570619B2/en not_active Expired - Fee Related
- 2004-07-19 EP EP04757111A patent/EP1652273A4/en not_active Withdrawn
- 2004-07-19 EP EP04757110A patent/EP1652276A4/en not_active Withdrawn
- 2004-07-19 JP JP2006520396A patent/JP4590406B2/en not_active Expired - Fee Related
- 2004-07-19 CA CA2532378A patent/CA2532378C/en not_active Expired - Fee Related
- 2004-07-19 AU AU2004260456A patent/AU2004260456C1/en not_active Ceased
-
2010
- 2010-07-05 JP JP2010153286A patent/JP5027907B2/en not_active Expired - Fee Related
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