JP2007502084A - Signal processing circuit - Google Patents

Abstract

  The signal processing circuit (1) has a first signal generator (10) that generates a DC level (DL). The second signal generator (11) generates an AC signal (AS) that is not related to the DC level (DL). The synthesis circuit (12) synthesizes the DC level (DL) and the AC signal (AS) to obtain a synthesized signal (CS). Further, the common processing circuit (13) processes the composite signal (CS).

Description

  The present invention relates to a signal processing circuit, an integrated circuit having a signal generator that is a part of the signal processing circuit, and a display device having such a signal processing circuit.

  Both scanning speed modulation (also referred to as SVM) and tilt correction are well-known features in display devices with cathode ray tubes (also referred to as CRT).

  U.S. Pat. No. 5,528,312 discloses an SVM circuit that improves the image resolution by modulating the scanning speed of the CRT electron beam by the derivation of the video signal.

  U.S. Pat. No. 5,825,131 discloses a tilt correction circuit and a degaussing circuit for a picture tube. Well-known degaussing coils are used to generate both degaussing and tilt fields. A switch is provided to connect either the tilt correction circuit or the degaussing circuit to the degaussing coil. During the degaussing operation, the switch connects the AC current generated by the degaussing circuit to the degaussing coil. After degaussing is complete, the switch connects the DC current generated by the tilt correction circuit to the degaussing coil to correct image rotation.

  In order to be able to generate both SVM signals and tilt correction signals, complex circuitry is required.

  An object of the present invention is to provide a simpler signal processing circuit.

  A first aspect of the present invention provides a signal processing circuit according to claim 1. A second aspect of the present invention provides an integrated circuit according to claim 6. A third aspect of the present invention provides a display device according to claim 7.

  According to the first aspect of the present invention, the signal processing circuit includes a first signal generator and a second signal generator for supplying a DC level and an AC signal, respectively. The DC level and the AC signal are not related to each other. Unrelated signals are, for example, signals used for different functions in a video display device. For example, the DC level is an input signal for the tilt function, and the AC signal is an input signal for the scanning speed modulation function. A combine circuit combines the DC level and the AC signal into a combined signal. A common processing circuit processes this composite signal.

  This has the advantage that these two unrelated signals can be processed by the same common processing circuit after being combined into a combined signal. Using a common processing circuit to process the composite signal reduces the cost of the signal processing circuit and the number of components. This common processing circuit may perform any signal processing operation such as, for example, filtering and / or amplification.

  In an embodiment according to the invention as defined in claim 2, the common signal generator (which is the signal processing circuit) has a common preamplifier for amplifying the composite signal. A low pass filter and a high pass filter separate out two unrelated signals at the output of the common preamplifier. Separate output amplifiers amplify the substantial DC level separated from the synthesized signal by the low pass filter and supplied via the low pass filter, and the substantial AC signal separated from the synthesized signal by the high pass filter, respectively. . These output amplifiers provide amplified DC levels and amplified AC signals to different loads.

  In an embodiment according to the invention as defined in claim 3, the first load is a tilt coil and the second load is a scanning velocity modulation coil or electrode. Therefore, the DC current to be supplied to the tilt coil and the AC signal to be supplied to the SVM coil or electrode are signals that are not related, but nevertheless these signals are combined into a combined signal. Thus, the same preamplifier can be used to amplify both DC and AC signals. In the prior art, the DC current for the tilt coil and the AC signal for the SVM are processed independently of each other. This is because tilt and SVM are independent functions and are considered to be handled separately. The embodiment according to the invention as defined in claim 3 can synthesize two unrelated signals into a composite signal, so that instead of performing the processing separately on both signals, Based on the insight that common processing can be performed on signals.

  In an embodiment according to the invention as defined in claim 4, a DC signal generator receives a set signal that determines the level of the DC level. In this way, the amount of tilt can be controlled so that the image is optimally positioned during factory assembly or normal use.

  In one embodiment according to the invention as defined in claim 5, the AC signal is a derivative of the video signal to be displayed on the CRT.

  According to the second aspect of the present invention, in an integrated circuit, only one pin is required to output a composite signal. It is not necessary to output both DC level and AC signals on separate pins.

  These and other aspects of the invention will be apparent from and will be elucidated with reference to the embodiments described hereinafter.

  FIG. 1 shows a display device having a cathode ray tube 18 (also referred to as CRT) and a circuit for driving a tilt coil L1 and a scanning speed modulation coil L2 (also referred to as SVM). Both the tilt coil L1 and the SVM coil L2 are magnetically coupled to the CRT 18. Separate circuits for generating the DC current ODL through the tilt coil L1 and the AC current OAS through the SVM coil L2 are well known in the art. It is also possible to use an SVM electrode (not shown) instead of the SVM coil L2. An AC voltage OAS is supplied to the SVM electrode.

  The signal generator 10 receives the set signal DCS and supplies a DC level DL determined by the set signal DCS. The signal generator 11 receives the video input signal VI and supplies an AC signal AS. Normally, the AC signal AS is the first derivative or the second derivative of the video signal VI. The synthesizing circuit 12 synthesizes the unrelated DC level DL and the AC signal AS and supplies the synthesized signal CS. For example, the composite signal CS has a superposition of the DC level defined by the DC level DL and the AC signal defined by the AC signal AS. The common processing circuit 13 processes the combined signal CS to obtain a processed combined signal PCS. The common processing circuit 13 may have a common preamplifier (preamplifier) 130 for preamplifying the synthesized signal CS. However, in other application examples, other common processing may be performed.

  The low pass filter 14 filters the DC component from the processed composite signal PCS to obtain a separated DC level SDL indicative of the DC level DL. The high pass filter 15 filters the AC component from the processed combined signal PCS to obtain a separated AC signal SAS indicating the AC signal AS. If the DC level and AC signal are combined in other ways, other suitable circuits may be used to separate the DC level and the AC signal.

  The output amplifier 16 amplifies the separated DC level SDL to obtain an appropriate DC current ODL passing through the tilt coil L1. The output amplifier 17 amplifies the separated AC signal SAS to obtain an appropriate AC current OAS that passes through the SVM coil L2.

  The signal processing circuit 1 includes signal generators 10 and 11, a synthesis circuit 12, a common signal processing circuit 13, filters 14 and 15, and output amplifiers 16 and 17.

  If the signal generators 10 and 11 and the synthesis circuit 12 are integrated in an integrated circuit IC, only one output pin P1 is required. If two unrelated signals DL and AS are not combined, two output pins will be required. The integrated circuit IC may also have a common processing circuit 13, in which case only one pin is required here in order to output the processed composite signal PCS. The small number of pins required for an IC package is important to keep the cost of the package as low as possible.

  FIG. 2 shows a detailed embodiment according to the present invention.

  The SVM input signal AS is essentially a high frequency signal, and the tilt input signal DL is at a DC level. The SVM input signal AS is supplied to the emitter of NPN transistor Q1 via a series arrangement of capacitor C5 and resistor R15. The tilt input signal DL is supplied to the base of the transistor Q1 via the register R10. A parallel arrangement of resistor R11 and capacitor C2 is provided between the base of transistor Q1 and ground. The resistor R9 is provided between the emitter of the transistor Q1 and the ground. The SVM input signal AS and the tilt input signal DL are synthesized by injecting the SVM input signal AS into the emitter of the transistor Q1 and supplying the DC level DL to the base of the transistor Q1. The composite signal CS occurs as a current through the collector of transistor Q1. As an alternative, the two signals AS and DL can be combined by combining two currents (not shown).

  Transistors Q1, Q2 and Q3 form a common processing circuit 13, which amplifies and buffers the combined signal CS and provides a processed combined signal PCS. The PNP transistor Q3 includes a collector connected to the ground, a base connected to the collector of the transistor Q1, and an emitter connected to the emitter of the transistor Q2 via the resistor R3. The NPN transistor Q2 includes a base connected to the base of the transistor Q3 via a series configuration part of diodes D2 and D4, and a collector connected to the power supply 15 that supplies the voltage V1. Diodes D2 and D4 are poled to conduct current in the direction of the collector of transistor Q1. The resistor R1 is provided between the collector and base of the transistor Q2. The collector current of transistor Q1 passes through two diodes D2 and D4 and the series component of resistor R1 to provide a drive voltage to the base of transistor Q2 and the base of transistor Q3, thereby causing a voltage across the emitter of transistor Q3. Which represents the processed composite signal PCS.

  Coil L and capacitor C1 form a low-pass filter 14, and transistors Q4 and Q5 form an output amplifier 16, which produces a DC current ODL through tilt coil L1, which is represented as resistance. The illustrated output amplifier 16 has a well-known inverter stage that is not described in detail here. Other output stages can be used as well.

  Capacitors C4 and C6 form a high-pass filter 15, and transistors Q6 and Q7 form an output amplifier 17, which generates an AC current OAS through SVM coil L2. The illustrated output amplifier 17 has a well-known voltage / current converter which is not described in detail here. Other output stages can be used as well.

  The above-described embodiments are illustrative rather than limiting the invention, and those skilled in the art will devise many alternative embodiments without departing from the scope of the appended claims. Note that could be possible. For example, a field effect transistor may be used instead of a bipolar transistor.

  In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb “comprise” and its conjugations does not exclude the presence of other elements or steps than those stated in a claim. The article “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.

FIG. 2 shows a display device comprising a signal processing circuit that is at least partially integrated in an integrated circuit. FIG. 4 shows a detailed embodiment according to the present invention.

Claims (7)

A first signal generator for generating a DC level;
A second signal generator for generating an AC signal not associated with the DC level;
A combining circuit that combines the DC level and the AC signal to obtain a combined signal;
And a common processing circuit for processing the synthesized signal. The common processing circuit includes a preamplifier for amplifying the combined signal to obtain an amplified combined signal, and the signal generator as the signal processing circuit further includes:
A low pass filter that separates the DC level from the amplified composite signal to obtain a separated DC level;
A high pass filter that separates the AC signal from the amplified composite signal to obtain a separated AC signal;
A first output amplifier that amplifies the separated DC level to provide an output DC level to a first load;
The signal processing circuit according to claim 1, further comprising: a second output amplifier that amplifies the separated AC signal to supply an output AC signal to a second load.   The signal processing circuit according to claim 2, wherein the first load is a tilt coil, and the second load is a scanning speed modulation coil.   The signal processing circuit according to claim 1, wherein the first signal generator has an input unit that receives a set signal and determines the DC level.   The signal processing circuit according to claim 3, wherein the second signal generator has an input for receiving a video signal and supplying the AC signal that is a derivative of the video signal. A first signal generator for generating a DC level;
A second signal generator for generating an AC signal not associated with the DC level;
A combining circuit that combines the DC level and the AC signal to obtain a combined signal;
And an output pin for supplying the synthesized signal.   4. A display device comprising: a cathode ray tube; and a signal processing circuit according to claim 3, wherein both a tilt coil and a scanning speed modulation coil are magnetically coupled to the cathode ray tube.

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