JP2007336043A - Optical transmission apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent generation of an FIFO error by executing control (centering control) so that the number of unread data in an FIFO memory is M/2 when a read pulse frequency becomes stable after completion of line switching. <P>SOLUTION: A pulse delete deletes a clock pulse of a position corresponding to stuff data from a main signal clock pulse as a writing pulse of the FIFO memory. A frequency control unit controls the frequency of the reading pulse so that the pulse to be outputted from the pulse deleting section may match the frequency of the reading pulse. A pulse number control unit controls the number of pulses to be outputted from the pulse delete so that the residual quantity of data of the FIFO memory may become a half of the FIFO memory size M, when the reading pulse frequency becomes stable after resetting the FIFO memory. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an optical transmission apparatus, and more particularly to an optical transmission apparatus having a line switching function when a line abnormality occurs and a destuffing function for deleting stuff data included in main signal data.

  STM-N and STS-N (N: integer) frame formats for synchronous optical communication networks SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network), which use optical communication capable of high-capacity transmission due to increased traffic. According to the above, user data is multiplexed and transmitted. FIG. 12 is a frame configuration diagram of 51.84 Mbps STS-1, which has 9 × 90 (bytes / 125 μs) as a whole, 3 × 9 bytes overhead OH, 87 × 9 bytes STS payload STS-1 SPE 9 bytes in the payload is a path overhead POH, and a plurality of low-order group channel packets are multiplexed on the remaining 86 × 9 bytes. In the synchronous optical network SONET, in addition to the above STS-1, the frame formats include STS-3 (155.52 Mbps), STS-12 (622.08 Mbps), STS-48 (2.488 Gbps),. . . And can be used as appropriate depending on the optical transmission path.

As a network configuration of the synchronous optical communication networks SDH and SONET, a ring configuration in which transmission devices TRU are connected in a ring shape as shown in FIG. 13 and redundancy is provided to the WDM line is known from the viewpoint of ensuring reliability. Yes. According to the ring configuration, the counterclockwise WDM link is the working (Work) optical line, and the clockwise is the protection (Protect) optical line. If a line abnormality such as a line break occurs in the working optical line, the WDM link is switched to the protection optical line. . This switching time is specified as 50 msec or less because the line is disconnected for the customer. The switching time is occupied by (1) line switching time, (2) PLL stabilization time for generating the main signal clock signal, and (3) writing main signal data to half of the FIFO memory provided in the destuff circuit. This is the time required for the FIFO (FIFO centering time) and must be 50 msec or less.
The line switching specifications of the optical transmission apparatus are defined as follows.
1. 50 msec or less until the error disappears after switching the line from the light input interruption of the unit.
Of this 50 ms, it takes a maximum of 30 msec for the device software (line switching control unit) to perform line switching from the notification of optical input interruption.
For this reason, in order to reduce the switching time to 50 msec or less, it is necessary to recover the error within 20 msec after the line is switched. That is, the PLL must stably output the main signal clock signal within 20 msec and complete the FIFO centering.

FIG. 14 is a configuration diagram of a portion related to the present invention of a conventional optical transmission device TRU. The line switching control unit 1 inputs a line switching signal to the optical switch 4 by software processing upon receiving a notification of optical disconnection from the active optical line disconnection detection unit 2 or the standby optical line disconnection detection unit 3. With this signal, the optical switch 4 switches the optical line from the working optical line to the protection optical line or from the working optical line to the protection optical line, and inputs it to the optical receiver 5.
The optical receiver 5 extracts the main signal data and the main signal clock from the optical signal, generates the light interruption alarm signal OPAL when the optical signal level is lower than the set level, and the PLL that generates the main signal clock is synchronized. When it is out of synch, CDR (Clock Data Recovery) synchronization loss alarm SOAL is generated. FIG. 15 is a configuration diagram of the optical receiver 5, a photoelectric conversion unit 5a that converts an optical signal into an electric signal, a main signal data / main signal clock extraction unit 5b, an electric signal level output from the photoelectric conversion unit, and a set level Vref. And a comparator 5c that outputs a light interruption alarm signal OPAL when it is below a set level. The main signal data / main signal clock extraction unit 8b is an amplifier 8a that amplifies the photoelectrically converted electrical signal (main signal), and a PLL circuit that generates a main signal clock included in the main signal and generates an alarm SOAL out of CDR synchronization. 8b and a flip-flop 8c that outputs main signal data in synchronization with the main signal clock.

  Returning to FIG. 14, the FIFO reset signal generator 6 resets the FIFO memory, which will be described later, when the optical signal level becomes equal to or higher than the set level after completion of the line switching and the PLL is stably out of synchronization. Generates reset signal RS. The destuffing unit 7 receives the main signal data and the main signal clock from the optical receiver 5, deletes the stuff data included in the main signal data, and sends out the data with a uniform data interval. FIG. 16 is a schematic operation explanatory diagram of the destuffing unit 7. In the main signal, a stuff byte S for synchronization is inserted on the transmission side as shown in FIG. Since the insertion position of this stuff byte S is known from the overhead OH pointer, the clock pulse (see (C)) at the position corresponding to the stuff byte is deleted from the byte clock signal of (B), and shown in (D) Generate a pulse train. At the same time, the main signal data from which the stuff byte S is deleted is recorded in the FIFO memory. As shown in (E), the main signal data is input to the FIFO memory in a state where the main signal data is extended at a position excluding the stuff byte S. After that, a FIFO read pulse with the same frequency as the pulse frequency of (D) is generated by PLL control, and if the main signal data is read from the FIFO memory by the read pulse, the main signal data is output at a uniform timing and the subsequent stage Can be sent to.

FIG. 17 is a configuration diagram of the destuffing unit 7, and FIG. 18 is a time chart for generating a PLL phase difference signal.
The conversion unit 7a converts the main signal data of the bit string into main signal data in units of bytes, for example, and the frequency divider 7b divides the main signal clock by 1 / m, for example, 1/8, as a write pulse WP of the FIFO memory. The data is input to the FIFO unit 7c and the pulse deletion unit 7d. The overhead monitoring unit 7e refers to the overhead, identifies the stuff byte position, and inputs it to the FIFO unit 7c and the pulse deletion unit 7d. The FIFO unit 7c does not write the input data to the FIFO memory at the stuff byte position, so that the main signal data excluding the stuff byte is stored in the FIFO memory by the write pulse WP. The pulse deleting unit 7d deletes a pulse at a position corresponding to the stuff data from the write pulse WP, and outputs a pulse WP ′.
The variable voltage oscillator (VCO) 7f generates a pulse with a frequency corresponding to the input voltage signal generated by the PLL control, and the frequency divider 7g divides the pulse output from the voltage variable oscillator by 1 / n to a FIFO read pulse. Generate RP. The FIFO unit 7c reads and outputs the main signal data from the FIFO memory by the FIFO read pulse RP.
The frequency divider 7h divides the read pulse RP by 1/2 to generate a pulse RP '(see FIG. 18), and the flip-flop 7i uses the frequency-divided pulse RP' as data and the pulse WP 'as a clock. Is set / reset to output a pulse WP ″. The EXOR circuit 7j outputs a signal PD indicating the phase difference between the pulse RP ′ and the pulse WP ″, and the low-pass filter 7k smoothes the phase difference signal PD and inputs it to the voltage variable oscillator 7f. Each unit 7f to 7k constitutes a PLL circuit, and finally the frequency of the read pulse RP becomes equal to the frequency of the pulse WP 'output from the pulse deletion unit 7d, and the main signal data is sent from the FIFO memory at a uniform timing. Read and output.

19 and 20 are explanatory diagrams of write / read control of the FIFO memory, and the capacity of the FIFO memory FM is M size (address 1 to address M). In a state where data is not written to the FIFO memory FM as shown in (A), the FIFO unit 7c writes the main signal data from which the stuff data has been deleted to the FIFO memory in order from the address 1, (B) As shown, the main signal data is written up to half of the memory size, and then the main signal data is read sequentially from address 1. In the figure, WAD means a write address, and RAD means a read address. Thereafter, the FIFO unit 7c performs writing and reading in parallel, and when the write pulse frequency f _WP and the read pulse frequency f _RP are equal, writing to the address M and reading from the address M / 2 as shown in (C). At the next timing, as shown in (D), writing to address 1 and reading from address M / 2 + 1 are performed simultaneously, and the above operation is repeated thereafter.

As described above, when the read pulse frequency f _RP is equal to the write pulse frequency f _WP , writing to the address 1 and reading from the address (M / 2 + 1) are performed simultaneously as shown in FIG. The address difference is M / 2, and M / 2 unread data is always stored in the FIFO memory FM. However, when the read pulse frequency f _RP is larger than the write pulse frequency f _WP , the address difference becomes M / 2 or less as shown in FIG. 20B, and the number of unread data becomes smaller than M / 2. When the read pulse frequency f _RP is smaller than the write pulse frequency f _WP , the address difference becomes larger than M / 2 and the number of unread data becomes larger than M / 2 as shown in FIG. In the state shown in FIG. 20 (B), if the read pulse frequency f _RP continues to be higher than the write pulse frequency f _WP , the main signal data can be output continuously in an underflow state where no unread data exists. Disappear. In the state shown in FIG. 20C, if the read pulse frequency f _RP continues to be lower than the write pulse frequency f _WP , the FIFO memory FM becomes full with unread data, and the main signal data is changed. Cannot write to FIFO memory. The FIFO section considers an underflow condition when the amount of unread data falls below UFL, and considers an overflow condition when it exceeds OFL and generates a FIFO error.

  FIG. 21 is a time chart from when a failure occurs in the working line until the line is restored. At time t1, a failure occurs in the working line and is notified to the line switching control unit 1, and switching to the protection line is performed at time t3. Complete. During this time, since the optical signal is not input to the optical receiver 5, the main signal clock is not generated, the output of the pulse deletion unit 7d (FIG. 17) is fixed to "1" or "0", and the phase difference of the EXOR circuit 7j The phase difference of the signal PD is fixed at a duty of 50%, the voltage variable oscillator 7f is in a free-run state, and its oscillation frequency increases as shown in FIG. In addition, the amount of unread data in the FIFO memory decreases and an underflow state occurs at time t2, resulting in a FIFO error. In this state, when switching to the protection line is completed at time t3, the main signal clock is extracted using the optical signal from the protection line, and the FIFO reset signal RS is generated at time t4. As a result, the FIFO memory is reset, and thereafter, the main signal data is written to and read from the FIFO memory described with reference to FIG.

First problem of the prior art When the read pulse frequency f _RP and the write pulse frequency f _WP are equal, the state in which M / 2 unread data is stored in the FIFO memory FM (centering state) is the lowest This is a preferable state that is unlikely to cause a flow or overflow. For this reason, the FIFO memory FM is reset by the FIFO reset signal RS when the line is restored after the line is disconnected, and the writing and reading control shown in FIG.
If the read pulse frequency f _RP is larger than the write pulse frequency f _WP at the time of FIFO reset, as shown in FIG. 22A, the address difference is made larger than M / 2 by reset, and the number of unread data is set to M / Ideally more than two. However, conventionally, as described above, by FIFO reset, the address difference is set to M / 2 and the number of unread data is set to M / 2 as shown in (B). For this reason, a difference (offset) of ΔD occurs in the number of unread data, and the number of unread data decreases as shown in (C) until the frequency of the read pulse RP stabilizes. The main signal data is written to and read from the FIFO memory while maintaining the number. However, since the number of unread data is small, temperature change, become other underflow state readout pulse frequency f _RP because there is no unread data as shown in the larger than the write pulse frequency f _WP (D) A FIFO error occurs.
If the read pulse frequency f _RP is smaller than the write pulse frequency f _WP at the time of FIFO reset, as shown in FIG. 22E, the address difference is made smaller than M / 2 by reset, and the number of unread data is set to M / Ideally less than 2. However, conventionally, as described above, by FIFO reset, the address difference is set to M / 2 and the number of unread data is set to M / 2 as shown in (F). For this reason, a difference (offset) of ΔD occurs in the number of unread data, and the number of unread data increases as shown in (G) until the frequency of the read pulse RP stabilizes. The main signal data is written to and read from the FIFO memory while maintaining the number. However, since the number of unread data is large, the overflow state where the FIFO memory becomes full with unread data as shown in (H) when the read pulse frequency f _RP becomes lower than the write pulse frequency f _WP due to temperature change or other causes And a FIFO error occurs.

Second Problem of Prior Art As described with reference to FIG. 21, when the input is interrupted, the phase difference of the phase difference signal PD of the EXOR circuit 7j is fixed to 50% duty, and a free-run state is entered. For this reason, the oscillation frequency of the voltage variable oscillator 7f increases as shown in FIG. At this time, the difference between the oscillation frequency of the variable voltage oscillator 7f (the frequency of the read pulse RP) and the frequency of the write pulse increases depending on the environment such as temperature, and it takes time to stabilize after the FIFO reset, and the worst FIFO error Occurs.
Third problem of the prior art FIFO reset after line switching is performed when the optical signal level exceeds the set level and the PLL is stable and no longer out of synchronization. 14) is performed by generating a FIFO reset signal RS. However, the FIFO reset may not be performed within 20msec due to variations in the reference voltage for detecting the light interruption alarm and variations in the CDR (Clock Data Recovery) frequency. In addition, it takes time until the unread data amount reaches M / 2 after the FIFO reset.
As a conventional technique, there is a technique in which a write clock to a memory is controlled by using a destuffing control circuit depending on the presence or absence of stuffing (Patent Document 1). However, this prior art does not solve the first to third problems.
JP-A-5-3463

From the above, the object of the present invention is to control the number of unread data in the FIFO memory to be M / 2 (centering control) when the read pulse frequency is stable after completion of line switching so that no FIFO error occurs. Is to do.
Another object of the present invention is to reduce the difference between the read pulse frequency and the write pulse frequency at the time of FIFO reset, to shorten the time until the read pulse frequency stabilizes after the FIFO reset, and to prevent a FIFO error from occurring. Is to do.
Another object of the present invention is to prevent a FIFO error from occurring by setting the remaining data amount to approximately 1/2 of the size M of the FIFO memory at a specified time when the reset control is terminated.

According to the present invention, the above object is achieved by an optical transmission apparatus having a line switching function at the time of a line abnormality and a destuffing function for deleting stuff data included in main signal data.
The optical transmission apparatus of the present invention extracts main signal data and a main signal clock from a line switching unit that detects a line abnormality and switches from one of the working optical line and the backup optical line to the other, and an optical signal input from the line switching unit. The optical receiver includes a stuffing unit that deletes stuff data included in the main signal data, and the destuffing unit includes (1) a FIFO memory that stores the main signal data from which the stuff data is deleted, and the FIFO When the memory is reset, the main signal data from which the stuff data has been deleted is sequentially written to the FIFO memory, the main signal data is written to half the memory size, and then the main signal data is read in order. (2) a read pulse generator that generates a read pulse of the FIFO memory, and (3) a main signal that becomes a write pulse of the FIFO memory A pulse deleting unit that deletes a clock pulse at a position corresponding to stuff data from the clock pulse; (4) controlling the frequency of the read pulse so that the frequency of the pulse output from the clock pulse deleting unit and the frequency of the read pulse match. (5) Reset signal generator for resetting the FIFO memory after completion of switching from one optical line to the other due to the occurrence of a line abnormality, (6) After the FIFO memory is reset, the read pulse frequency is stabilized A pulse number control unit that controls the number of pulses output from the pulse deletion unit so that the difference between the remaining data amount of the FIFO memory and 1/2 of the size M of the FIFO memory becomes zero. .
The pulse number control unit sets the difference between the write address and the read address of the FIFO memory as the remaining data amount, and if the difference is positive, controls to insert one pulse into the pulse output from the pulse deletion unit, If the difference is negative, a control unit that controls to delete one pulse from the pulse, a pulse adjustment unit that inserts one pulse into the pulse according to an instruction from the control unit, or deletes one pulse from the pulse I have.
The reset signal generator resets the FIFO memory when the data remaining in the FIFO memory becomes smaller than the first set value and when the remaining data becomes larger than the second set value, When the line is abnormal, the difference between the first set value and the second set value is narrowed to perform the FIFO memory reset control. After the set time from the line abnormal detection time or the line switching completion time, the first and second Return the set value to the normal value.
The optical transmission apparatus of the present invention further includes a fixed oscillator that generates a pulse having the same frequency as the main signal clock pulse, and a pulse output from the fixed oscillator in place of the main signal clock pulse due to the occurrence of a line abnormality to the pulse deletion unit. A pulse switching unit for inputting and a pulse deletion stop signal generating unit for generating a signal for stopping the clock pulse deleting function of the pulse deleting unit when a line abnormality occurs are provided.

According to the present invention, when the read pulse frequency of the FIFO memory is stabilized, the data remaining amount (unread data amount) of the FIFO memory is controlled (centering control) so as to be 1/2 of the size M of the FIFO memory. Therefore, it is possible to prevent the FIFO error from occurring.
According to the present invention, a pulse output from a fixed oscillator is used instead of the main signal clock pulse due to the occurrence of a line abnormality, and control is performed so that the read pulse frequency matches the pulse frequency. The difference between the read pulse frequency and the write pulse frequency at the time of memory reset can be reduced. As a result, the time until the read pulse frequency is stabilized after the FIFO reset can be shortened, and a FIFO error can be prevented from occurring.
According to the present invention, when the remaining amount of data in the FIFO memory becomes smaller than the first set value and when the remaining amount of data becomes larger than the second set value, the FIFO memory is regarded as a FIFO error. When the line is abnormal, the difference between the first set value and the second set value is narrowed to perform the FIFO memory reset control. After the set time from the line abnormality detection time or the line switching completion time, the first, Since the second set value is returned to the normal value, the reset control is frequently performed during line abnormalities, so the remaining data can be reduced to almost 1/2 of the FIFO memory size M at the specified time. The occurrence of errors can be prevented.

(A) First Embodiment FIG. 1 is a configuration diagram of a portion related to the present invention in an optical transmission apparatus TRU, and can be applied to all the following embodiments.
The line switching control unit 11 inputs a line switching signal to the optical switch 14 by software processing upon receiving a notification of optical signal disconnection from the active optical line disconnection detection unit 12 or the protection optical line disconnection detection unit 13. With this signal, the optical switch 14 switches the optical line from the working optical line to the protection optical line, or switches from the working optical line to the protection optical line, and inputs to the optical receiver 15.
The optical receiver 15 extracts the main signal data and the main signal clock from the optical signal, generates the light interruption alarm signal OPAL when the optical signal level is lower than the set level, and the PLL that generates the main signal clock is synchronized. In the out-of-band condition, the CDR out-of-sync alarm SOAL is generated. The optical receiver 15 has the configuration shown in FIG.
The FIFO reset signal generator 16 generates a FIFO reset signal RS for resetting the FIFO memory when the optical signal level becomes equal to or higher than the set level at the time of line switching and the PLL is stable and no longer out of synchronization. The line abnormality signal generation unit 17 generates a line abnormality signal when an optical signal interruption detection signal is generated from the interruption detection units 12 and 13, and generates a line abnormality signal when a line switching signal is output from the line switching control unit 11. Stop. The destuffing unit 18 receives the main signal data and the main signal clock from the optical receiver 15, deletes the stuff data included in the main signal data, and sends out the data with a uniform data interval.

FIG. 2 is a configuration diagram of the destuffing unit 18 of the first embodiment. The conversion unit 18a converts the main signal data of the bit string into, for example, main signal data in units of bytes, and the frequency divider 18b divides the main signal clock by 1 / m, for example, 1/8, as a write pulse WP of the FIFO memory The data is input to the FIFO unit 18c and the pulse deletion unit 18d. The overhead monitoring unit 18e identifies the stuff byte position with reference to the overhead, and inputs it to the FIFO unit 18c and the pulse deletion unit 18d. The FIFO unit 18c does not write the input data to the FIFO memory at the stuff byte position, so that the main signal data excluding the stuff byte is stored in the FIFO memory by the write pulse WP. The pulse deleting unit 18d deletes a pulse at a position corresponding to the stuff data from the write pulse WP and outputs a pulse WP ′.
The variable voltage oscillator (VCO) 18f generates a pulse with a frequency corresponding to the input voltage signal generated by the PLL control, and the frequency divider 18g divides the pulse output from the voltage variable oscillator by 1 / n to a FIFO read pulse. Generate RP. The FIFO unit 18c reads and outputs the main signal data from the FIFO memory by the FIFO read pulse RP.
The frequency divider 18h divides the read pulse RP by 1/2 to generate a pulse RP '(see FIG. 18), and the flip-flop 18i uses the frequency-divided pulse RP' as data and the pulse WP 'as a clock. Is set / reset to output a pulse WP ″. The EXOR circuit 18j outputs a signal PD indicating the phase difference between the pulse RP ′ and the pulse WP ″, and the low-pass filter 18k smoothes the phase difference signal PD and inputs it to the voltage variable oscillator 18f. Each unit 18f to 18k constitutes a PLL circuit. Finally, the frequency of the read pulse RP is equal to the frequency of the pulse WP ′ output from the pulse deletion unit 18d, and the main signal data is uniformly transmitted from the FIFO memory. Read and output.

FIG. 3 is a block diagram of the FIFO unit. A FIFO memory 31 having a capacity M has addresses 0 to (M−1), and main signal data is written and read in a FIFO (First In First Out) manner. It has become. The write controller 32 writes the main signal data to the predetermined address WAD of the FIFO memory 31 by the write pulse WP when the enable signal enb is input from the overhead monitor 18e, and increments the write address WAD by 1 (WAD + 1 = WAD). Since the overhead monitoring unit 18e does not output the enable signal enb only at the stuff byte position, the write control unit 32 writes main signal data other than the stuff byte in the FIFO memory 31. Further, the read control unit 33 reads and outputs the main signal data from the predetermined address RAD of the FIFO memory 31 by the read pulse RP, and increments the read address RAD by 1 (RAD + 1 = RAD).
The FIFO memory 31 is cleared by the FIFO reset signal, the write control unit 32 starts writing from the address 0 by the FIFO reset signal, and the read control unit 23 starts reading from the address M / 2 by the FIFO reset signal. The main signal data is written to and read from the FIFO memory 21. The FIFO monitor unit 34 outputs the difference (= WAD−RAD) between the write address WAD and the read address RAD of the FIFO memory as a remaining data (unread data amount) R.

  Returning to FIG. 2, the centering control unit 21 adjusts the read pulse frequency by performing control to insert a pulse in the pulse train WP ′ output from the pulse deletion unit 18d or to delete the pulse from the pulse train WP ′. Then, control is performed so that the remaining amount of data in the FIFO memory becomes M / 2 (centering control). The pulse adjustment unit 22 inserts a pulse into the pulse train WP ′ based on a pulse insertion / deletion instruction (centering signal) from the centering control unit 21, or deletes the pulse from the pulse train WP ′ and inputs it to the flip-flop 18i. To do.

When the frequency of the read pulse RP is stabilized after the line switching is completed, the number of unread data may decrease as shown in FIG. 4 (A) or increase as shown in FIG. 4 (B). Such a state is close to an underflow state or an overflow state and may develop into a FIFO error. Therefore, when the frequency of the read pulse RP is stabilized, the centering control unit 21 performs the above centering control to control the remaining data amount to be M / 2. That is, the centering control unit 21 sets the difference between the write address WAD and the read address RAD of the FIFO memory as the remaining data amount (= WAD−RAD), and the difference between the remaining data amount and 1/2 of the size M of the FIFO memory ( = If the remaining data-M / 2) is positive, control is performed so that one pulse is inserted into the pulse WP 'output from the pulse deleting unit 18d. If the difference is negative, one pulse is generated from the pulse WP'. The pulse adjusting unit 22 inserts one pulse into the pulse WP ′ according to the one-pulse insertion instruction, and deletes one pulse from the pulse WP ′ according to the one-pulse deletion instruction.
In the case of FIG. 4 (A), the pulse is deleted from the pulse WP ′, and the frequency of the read pulse RP decreases. As a result, control is performed so that the data write speed becomes higher than the data read speed, and the amount of unread data in the FIFO memory increases to M / 2, and when it becomes M / 2, the centering control ends. In the case of FIG. 4B, a pulse is inserted into the pulse WP ′, and the frequency of the read pulse RP increases. As a result, control is performed so that the data read speed becomes higher than the data write speed, and the amount of unread data in the FIFO memory decreases to M / 2, and when it becomes M / 2, the centering control ends.

FIG. 5 is a centering control processing flow. The FIFO memory is reset after the line switching is completed. When the set time T has elapsed after the reset (step 101), the centering control unit 21 reads the FIFO data remaining amount R (step 102). The set time T is a time during which the read pulse frequency can be regarded as stable. However, the FIFO remaining amount R may be read by detecting that the frequency of the read pulse RP is stable. Next, the centering control unit 21 calculates a difference d (= data remaining amount−M / 2) between the remaining data amount and 1/2 of the size M of the FIFO memory (step 103), and the difference d is 0. (Step 104), and if it is 0, the centering control is terminated.
If the difference d is not 0, the sign of d is determined (step 105). If the difference is positive, the pulse adjustment unit 22 is instructed to insert one pulse (step 106). As a result, the pulse adjustment unit 22 inserts one pulse into the pulse WP ′ output from the pulse deletion unit 18d, and decreases the amount of unread data by increasing the frequency of the read pulse RP. Thereafter, the centering control unit 21 repeats the processing from step 104 onward.
On the other hand, if the difference d is negative in step 105, the pulse adjustment unit 22 is instructed to delete one pulse (step 107). As a result, the pulse adjustment unit 22 deletes one pulse from the pulse WP ′ output from the pulse deletion unit 18d, and increases the amount of unread data by lowering the frequency of the read pulse RP. Thereafter, the centering control unit 21 repeats the processing from step 104 onward.

  FIG. 6 is a time chart of the first embodiment from when a failure occurs in the working line until the line is restored. At time t1, a failure occurs in the working line and is notified to the line switching control unit 11, and at time t3. Switching to the protection line is complete. During this time, since the optical signal is not input to the optical receiver 15, the main signal clock is not generated. Therefore, the output of the flip-flop 18j (FIG. 2) is fixed to "1" or "0", the phase difference of the phase difference signal PD of the EXOR circuit 18j is fixed to 50% duty, and the voltage variable oscillator 18f is free-running. As a result, the oscillation frequency increases as shown in FIG. 6, for example. In addition, the amount of unread data in the FIFO memory decreases and an underflow state occurs at time t2, resulting in a FIFO error. In this state, when switching to the protection line is completed at time t3, the main signal clock is extracted using the optical signal from the protection line, and the FIFO reset signal is generated from the FIFO reset signal generator 16 (FIG. 1) at time t4. RS occurs. As a result, the FIFO memory 21 is cleared, and the write address WAD is reset to 0 and the read address is reset to M / 2.

If the frequency f _RP read pulse RP during FIFO reset is greater than the frequency f _WP of the write pulse WP, an offset occurs ΔD indicated by (B) in FIG. 22, unread data number to the frequency of the read pulse RP is stable As shown in (C), the frequency of the read pulse RP is stabilized at time t5 after a predetermined time after reset. In the first embodiment, the centering control of FIG. 5 is started at time t5, and the unread data amount is set to M / 2 at time t6.
If the read pulse frequency f _RP is smaller than the write pulse frequency f _WP at the time of FIFO reset, an offset ΔD shown in FIG. 22 (F) occurs, and the number of unread data becomes (until the frequency of the read pulse RP stabilizes). As shown in G), the frequency of the read pulse RP is stabilized at time t5 after a predetermined time after reset. In the first embodiment, the centering control of FIG. 5 is started at time t5, and the unread data amount is set to M / 2 at time t6.
According to the first embodiment, when the frequency of the read pulse of the FIFO memory is stabilized, the FIFO remaining data is controlled so as to be 1/2 of the FIFO memory size M (centering control). Can be prevented.

(B) Second Embodiment FIG. 7 is a block diagram of the destuffing portion of the second embodiment of the present invention. The same parts as those of the destuffing portion of the first embodiment of FIG. . The difference is
(1) A fixed oscillator 41 for generating a pulse having the same frequency as the main signal clock pulse is provided.
(2) A pulse switching unit 42 is provided that selects a pulse output from the fixed oscillator 41 instead of the main signal clock pulse due to the occurrence of a line abnormality and inputs it to the pulse deletion unit 18d.
(3) The clock pulse deletion function of the pulse deletion unit 18d is stopped by the optical input interruption alarm signal OPAL.
The main signal clock is not generated due to a line error. Therefore, in the first embodiment, the flip-flop 18i is fixed to “0” or “1”, the phase difference of the phase difference signal PD of the EXOR circuit 18j is fixed to 50% duty, and a free-run state is set. In the free run state, the oscillation frequency of the voltage variable oscillator 18f increases as shown in FIG. At this time, the difference between the oscillation frequency of the variable voltage oscillator 18f (the frequency of the read pulse RP) and the frequency of the write pulse increases depending on the environment such as temperature, and it takes time to stabilize after the FIFO reset. May cause the worst FIFO error.
Therefore, in the second embodiment, when a line abnormality occurs, a pulse output from the fixed oscillator 41 is input to the pulse deleting unit 18d instead of the main signal clock pulse, and the clock pulse deleting function of the pulse deleting unit is stopped. The reason for stopping the clock pulse deletion function is that when a line error occurs, an arbitrary signal is input to the overhead monitoring unit 18e, and the overhead monitoring unit erroneously detects a stuff byte from the input signal and deletes the pulse deletion. This is because it instructs the unit 18d.

FIG. 8 is a time chart of the second embodiment from when a failure occurs on the working line until the line is restored, and is almost the same as the first embodiment of FIG. The difference is that the PLL control does not continue to operate in a free-run state due to the occurrence of a line abnormality, and the frequency of the read pulse RP does not vary significantly as in the first embodiment.
According to the second embodiment, the difference between the read pulse frequency and the write pulse frequency when the FIFO memory is reset after the line switching is completed can be reduced, and as a result, the time until the read pulse frequency stabilizes after the FIFO reset. The FIFO error can be prevented from occurring before the centering control is started.

(C) Third Embodiment FIG. 9 is a block diagram of the destuffing section of the third embodiment of the present invention. The same parts as those of the destuffing section of the second embodiment of FIG. . The difference is
(1) A FIFO reset unit 51 is provided to monitor whether the FIFO is underflowed or overflowed, and resets the FIFO 18c when underflowed or overflowed.
(2) The FIFO 18c is not reset by the reset signal output from the FIFO reset signal generator 16 in FIG.
(3) When the line is abnormal, as shown in Fig. 10 (B), set the first set value THu that is recognized as an underflow state to a value close to M / 2, and the second set value THo that is recognized as an overflow state. The value is close to M / 2 and the range of FIFO data remaining amount (unread data amount) that is considered normal is narrowed.
(4) A timer 52 is provided, and the first and second set values THu and THo are the normal values shown in FIG. 10 (A) after a predetermined time (a monitoring control period, for example, 50 msec) after the occurrence of a line abnormality. To return to
It is. Note that the first and second set values THu and THo can be returned to normal values after a predetermined time (for example, 20 msec) after the line switching is completed.
When normal, the FIFO reset unit 51 monitors whether the remaining FIFO data exceeds the range of THu to THo shown in FIG. 10 (A), and if it exceeds, it is regarded as a FIFO error and resets the FIFO unit 18c. Also, when the line is abnormal, the first and second set values THu and THo are close to M / 2 as shown in Fig. 10 (B), and it is monitored whether the range of THu to THo is exceeded. Deemed, the FIFO unit 18c is reset.
Further, when a time-up signal is input from the timer 52, the FIFO reset unit 51 returns the first and second set values THu and THo to the normal values shown in FIG. 10 (A).

FIG. 11 is a time chart of the third embodiment from when a failure occurs on the working line until the line is restored, and is almost the same as the second embodiment of FIG. The difference is that the range of THu to THo is narrowed during the monitoring control period (t1 to t4). Since the range of THu to THo is narrow, FIFO errors frequently occur and FIFO reset is performed. For this reason, the FIFO data remaining amount falls within the first and second set values THu and THo in FIG. 10B when the line is abnormal.
According to the third embodiment, since a FIFO error frequently occurs during a specified period after the occurrence of a line abnormality and the FIFO is reset, the remaining data amount is almost equal to the size of the FIFO memory at the specified time when the reset control ends. It can be halved, and FIFO errors can be prevented.

・ Additional notes
(Appendix 1)
In an optical transmission apparatus having a line switching function at the time of a line abnormality and a destuffing function for deleting stuff data included in main signal data,
A line switching unit that detects a line abnormality and switches from one of the working optical line and the protection optical line to the other,
An optical receiver that extracts main signal data and a main signal clock from an optical signal input from a line switching unit;
A destuffing section for deleting stuffing data included in the main signal data;
The de-staff section comprises
A FIFO memory for storing the main signal data from which the stuff data has been deleted, and when the FIFO memory is reset, the main signal data from which the stuff data has been deleted is sequentially written into the FIFO memory, and the main signal is reduced to half the memory size. A FIFO unit including a write / read control unit that sequentially reads the main signal data after writing the data;
A read pulse generator for generating a read pulse of the FIFO memory;
A pulse deletion unit for deleting a clock pulse at a position corresponding to the stuff data from a main signal clock pulse which is a write pulse of the FIFO memory;
A control unit that controls the frequency of the readout pulse so that the pulse output from the clock pulse deletion unit and the frequency of the readout pulse match;
A reset signal generator that resets the FIFO memory after completion of switching from one optical line to the other due to the occurrence of a line abnormality,
After the FIFO memory reset, when the read pulse frequency is stabilized, the pulse output from the pulse deletion unit is set so that the difference between the remaining data amount of the FIFO memory and 1/2 of the FIFO memory size M becomes zero. Pulse number control unit to control the number,
An optical transmission device comprising:
(Appendix 2)
The pulse number control unit starts the pulse number control a predetermined time after the FIFO memory is reset,
The optical transmission device as set forth in appendix 1, wherein:
(Appendix 3)
The write pulse frequency control unit
The difference between the write address and the read address of the FIFO memory is the remaining data, and if the difference is positive, control is performed so that one pulse is inserted into the pulse output from the pulse deletion unit, and if the difference is negative , A control unit that controls to delete one pulse from the pulse,
A pulse adjusting unit that inserts one pulse into the pulse according to an instruction from the control unit, or deletes one pulse from the pulse,
The optical transmission device according to appendix 1 or 2, characterized by comprising:
(Appendix 4)
The reset signal generation unit resets the FIFO memory when an optical signal level input to the optical receiver is equal to or higher than a set level and a main signal clock output from the optical receiver is stable. The optical transmission apparatus according to appendix 1.
(Appendix 5)
The reset signal generator is
When normal, when the remaining amount of data in the FIFO memory becomes smaller than the first set value and when the remaining amount of data becomes larger than the second set value, the FIFO memory is reset.
When the line is abnormal, the difference between the first set value and the second set value is narrowed to perform the FIFO memory reset control. After the set time from the line abnormal detection time or the line switching completion time, the first and second The optical transmission apparatus according to appendix 1, wherein the set value is returned to a normal value.
(Appendix 6)
A fixed oscillator for generating a pulse having the same frequency as the main signal clock pulse;
A pulse switching unit that inputs a pulse output from the fixed oscillator to the pulse deletion unit instead of the main signal clock pulse due to the occurrence of a line abnormality;
A pulse deletion stop signal generator for generating a signal for stopping the clock pulse deletion function of the pulse deletion unit due to occurrence of a line abnormality;
The optical transmission apparatus according to appendix 1, wherein the optical transmission apparatus is provided.
(Appendix 7)
In an optical transmission device having a line switching function at the time of a line abnormality and a destuffing function for deleting stuff data included in main signal data,
A line switching unit that detects a line abnormality and switches from one of the working optical line and the protection optical line to the other,
An optical receiver that extracts main signal data and a main signal clock from an optical signal input from a line switching unit;
A destuffing section for deleting stuffing data included in the main signal data;
The de-staff section comprises
A FIFO memory for storing the main signal data from which the stuff data has been deleted, and when the FIFO memory is reset, the main signal data from which the stuff data has been deleted is sequentially written into the FIFO memory, and the main signal is reduced to half the memory size. A FIFO unit including a write / read control unit that sequentially reads the main signal data after writing the data;
A read pulse generator for generating a read pulse of the FIFO memory;
A pulse deletion unit for deleting a clock pulse at a position corresponding to the stuff data from a main signal clock pulse which is a write pulse of the FIFO memory;
A control unit that controls the frequency of the readout pulse so that the pulse output from the clock pulse deletion unit and the frequency of the readout pulse match;
A fixed oscillator that generates a pulse having the same frequency as the main signal clock pulse;
A pulse switching unit that inputs a pulse output from the fixed oscillator to the pulse deletion unit instead of the main signal clock pulse due to the occurrence of a line abnormality;
A pulse deletion stop signal generator for generating a signal for stopping the clock pulse deletion function of the pulse deletion unit due to occurrence of a line abnormality;
A reset signal generator that resets the FIFO memory after completion of switching from one optical line to the other due to the occurrence of a line abnormality,
An optical transmission device comprising:

It is a block diagram of the part relevant to this invention in the optical transmission apparatus TRU. It is a block diagram of the destuffing part of 1st Example. It is a block diagram of a FIFO part. It is explanatory drawing of the number of unread data when the frequency of read-out pulse RP is stabilized after completion | finish of line switching. It is a centering control processing flow. 6 is a time chart of the first embodiment from when a failure occurs on the working line until the line is restored. It is a block diagram of the destuffing part of 2nd Example of this invention. 6 is a time chart of a second embodiment from when a failure occurs in an active line until the line is restored. It is a block diagram of the destuffing part of 3rd Example of this invention. It is explanatory drawing of 1st setting value THu recognized as an underflow state, and 2nd setting value THo recognized as an overflow state. FIG. 10 is a time chart of the third embodiment from when a failure occurs in an active line until the line is restored. It is a frame block diagram of STS-1. It is explanatory drawing of the transmission network which connected the transmission apparatus TRU in the ring shape. It is a principal part block diagram of the conventional optical transmission apparatus TRU. It is a block diagram of an optical receiver. It is a schematic operation | movement explanatory drawing of a destuffing part. It is a block diagram of the conventional destuffing part. It is a time chart of PLL phase difference signal generation. FIG. 3 is a first explanatory diagram of write / read control to a FIFO memory. FIG. 10 is a second explanatory diagram of writing / reading control to / from the FIFO memory. Time chart from the failure of the working line to the restoration of the line FIG. 4 is a relationship diagram between a magnitude relationship between a read pulse frequency and a write pulse frequency and an unread data amount (FIFO data amount).

Explanation of symbols

18 Destuffing section 18a Conversion section 18b Frequency divider 18c FIFO section 18d Pulse deletion section 18e Overhead monitoring section 18f Variable voltage oscillator (VCO)
18j EXOR circuit 18k Low pass filter 21 Centering control unit 22 Pulse adjustment unit

Claims (5)

In an optical transmission device having a line switching function at the time of a line abnormality and a destuffing function for deleting stuff data included in main signal data,
A line switching unit that detects a line abnormality and switches from one of the working optical line and the protection optical line to the other,
An optical receiver that extracts main signal data and a main signal clock from an optical signal input from a line switching unit;
A destuffing section for deleting stuffing data included in the main signal data;
The de-staff section comprises
FIFO memory for storing the main signal data from which the stuff data has been deleted, and when the FIFO memory is reset, the main signal data from which the stuff data has been deleted is sequentially written into the FIFO memory, and the main signal is reduced to half the memory size. A FIFO unit including a write / read control unit that sequentially reads the main signal data after writing the data;
A read pulse generator for generating a read pulse of the FIFO memory;
A pulse deletion unit for deleting a clock pulse at a position corresponding to the stuff data from a main signal clock pulse which is a write pulse of the FIFO memory;
A control unit that controls the frequency of the readout pulse so that the pulse output from the clock pulse deletion unit and the frequency of the readout pulse match;
A reset signal generator that resets the FIFO memory after completion of switching from one optical line to the other due to the occurrence of a line abnormality,
After the reset of the FIFO memory, when the read pulse frequency is stabilized, the pulse output from the pulse deletion unit so that the difference between the remaining data amount of the FIFO memory and 1/2 of the size M of the FIFO memory becomes zero A pulse number control unit for controlling the number of
An optical transmission device comprising: The pulse number control unit
The difference between the write address and read address of the FIFO memory is the remaining data, and if the difference is positive, control is performed so that one pulse is inserted into the pulse output from the pulse deletion unit, and if the difference is negative , A control unit that controls to delete one pulse from the pulse,
A pulse adjusting unit that inserts one pulse into the pulse according to an instruction from the control unit, or deletes one pulse from the pulse,
The optical transmission apparatus according to claim 1, further comprising: The reset signal generator is
When normal, when the remaining amount of data in the FIFO memory becomes smaller than the first set value and when the remaining amount of data becomes larger than the second set value, the FIFO memory is reset.
When the line is abnormal, the difference between the first set value and the second set value is narrowed to perform the FIFO memory reset control. After the set time from the line abnormal detection time or the line switching completion time, the first and second 2. The optical transmission apparatus according to claim 1, wherein the set value is returned to a normal value. A fixed oscillator for generating a pulse having the same frequency as the main signal clock pulse;
A pulse switching unit that inputs a pulse output from the fixed oscillator to the pulse deletion unit instead of the main signal clock pulse due to the occurrence of a line abnormality;
A pulse deletion stop signal generator for generating a signal for stopping the clock pulse deletion function of the pulse deletion unit due to occurrence of a line abnormality;
The optical transmission apparatus according to claim 1, further comprising: In an optical transmission device having a line switching function at the time of a line abnormality and a destuffing function for deleting stuff data included in main signal data,
A line switching unit that detects a line abnormality and switches from one of the working optical line and the protection optical line to the other,
An optical receiver that extracts main signal data and a main signal clock from an optical signal input from a line switching unit;
A destuffing section for deleting stuffing data included in the main signal data;
The de-staff section comprises
FIFO memory for storing the main signal data from which the stuff data has been deleted, and when the FIFO memory is reset, the main signal data from which the stuff data has been deleted is sequentially written into the FIFO memory, and the main signal is reduced to half the memory size. A FIFO unit including a write / read control unit that sequentially reads the main signal data after writing the data;
A read pulse generator for generating a read pulse of the FIFO memory;
A pulse deletion unit for deleting a clock pulse at a position corresponding to the stuff data from a main signal clock pulse which is a write pulse of the FIFO memory;
A control unit that controls the frequency of the readout pulse so that the pulse output from the clock pulse deletion unit and the frequency of the readout pulse match;
A fixed oscillator that generates a pulse having the same frequency as the main signal clock pulse;
A pulse switching unit that inputs a pulse output from the fixed oscillator to the pulse deletion unit instead of the main signal clock pulse due to the occurrence of a line abnormality;
A pulse deletion stop signal generator for generating a signal for stopping the clock pulse deletion function of the pulse deletion unit due to occurrence of a line abnormality;
A reset signal generator that resets the FIFO memory after completion of switching from one optical line to the other due to the occurrence of a line abnormality,
An optical transmission device comprising:

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