JP2007336013A - Soft mute circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a soft mute circuit for adjusting a signal level of an FM signal according to received electric field strength and capable of achieving various mute characteristics to be required. <P>SOLUTION: The soft mute circuit is configured of: a mute circuit 108 including resistance value switching means SW0 to SW13 for switching resistance values R0 to R13 and adjusting the signal level to an optional level by switching the resistance value; a digital conversion circuit for digitizing the received electric field strength to generate received electric field strength data; a plurality of logic circuits 107a, b for operating the resistance value switching means SW0 to SW13 according to the received electric field strength data to achieve a prescribed mute characteristic; and a selection means SWb for selecting the logic circuit 107a or 107b for achieving the desired mute characteristic from the logic circuits 107a, b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a mute circuit that reduces noise by performing mute processing on an output signal or the like in accordance with a decrease in reception level of a radio receiver.

  Generally, a radio IC (Integrated Circuit) includes a mute circuit that performs mute processing on an output signal gradually (stepwise) in accordance with a decrease in reception level. By this mute processing, the sense of noise felt by the listener is reduced to improve the sense of hearing.

  The mute process is realized by adjusting the gain of the mute circuit according to the received electric field intensity detected by the RSSI circuit or the like. The soft mute process is realized by digitally controlling the gain of the mute circuit in accordance with received field strength data obtained by digitizing the received field strength.

  Patent Document 1 discloses a soft mute correction in which when a sensitivity varies depending on a reception frequency in a wideband receiver or the like, a mute amount is not increased and a sound fluctuation does not occur when a weak electric field is received. A circuit is disclosed.

Patent Document 2 discloses that the size of an IC can be reduced by reducing the number of terminals for the entire IC by reducing the number of terminals for connecting external components to obtain optimum time constant characteristics for each of the mute circuit and the search stop signal detection circuit. A semiconductor integrated circuit for an FM receiver that realizes a reduction in cost and cost is disclosed.
JP 2000-165266 A JP 2001-267951 A

  However, the quality of hearing depends on the subjectivity of the listener. For example, when a radio IC is manufactured, there is a problem in that it is necessary to prepare a radio IC having a different mute circuit for each manufacturer because different mute characteristics are required for each manufacturer receiving the IC.

  The present invention has been made in view of the above-described problems, and a problem to be solved is to provide a mute circuit capable of realizing various required mute characteristics.

  In order to solve the above-described problem, a soft mute circuit according to the present invention includes a resistance value switching unit that switches a resistance value in a soft mute circuit that adjusts the signal level of an FM signal according to the received electric field strength. A mute circuit that adjusts the signal level to an arbitrary level by switching a value, a digital conversion circuit that digitizes the received electric field strength to generate received electric field strength data, and the resistance value according to the received electric field strength data A digital control circuit having a plurality of logic circuits for realizing a predetermined mute characteristic by operating the switching means, and a selection means for selecting a logic circuit for realizing a desired mute characteristic from the plurality of logic circuits; .

  According to the present invention, each logic circuit realizes a predetermined mute characteristic by operating the resistance switching means included in the mute circuit. And it becomes possible to perform the mute process which implement | achieves a desired mute characteristic by switching a logic circuit using the selection means which a digital control circuit has.

  As described above, according to the present invention, a mute circuit capable of realizing various required mute characteristics can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. The soft mute circuit according to the present embodiment is formed on a semiconductor circuit substrate by a CMOS process that can manufacture p-channel and n-channel MOS transistors.

FIG. 1 is a block diagram showing a configuration example of an FM radio receiver 100 using a soft mute circuit according to an embodiment of the present invention.
An FM radio receiver 100 shown in FIG. 1 is a main part of a superheterodyne FM radio receiver, and an RF (Radio Frequency) unit 101 for generating a stereo signal from a received broadcast wave, and an IF (Intermediate Frequency). ) IF section 102 that generates a signal, limiter amplifier 103, FM detector circuit 104, RSSI circuit (Received Signal Strength Indicator) 105 that detects the received electric field strength, and ADC that digitizes the received electric field strength and generates received electric field strength data (Analog to Digital Converter) circuit 106, digital control circuit 107 that controls mute circuit 108 according to received field strength data, and FM signal output by FM detection circuit 104 Comprising a muting circuit 108, for performing muting processing and.

  The broadcast wave received by the antenna 109 is amplified to a level necessary for subsequent processing by the RF unit 101, and signals other than the desired wave are attenuated. The IF unit 102 is converted into an IF signal by mixing with, for example, a signal of a local oscillation circuit.

  The IF signal becomes an FM signal having a constant amplitude, the amplitude of which is limited by the limiter amplifier 103. Then, FM detection is performed by the FM detection circuit 104 configured by a pulse detection circuit or the like, and is input to the buffer 110 or the like via the mute circuit 108. In the buffer 110 or the like, a stereo signal is generated from the FM signal and output to a speaker or the like.

  On the other hand, the output signal (IF signal) of the limiter amplifier 103 is also output to the RSSI circuit 105. The received electric field strength is detected by the RSSI circuit 105. The ADC circuit 106 digitizes the detected received field strength to generate received field strength data, and outputs the received field strength data to the digital control circuit 107. The digital control circuit 107 generates a mute signal corresponding to the received electric field strength data and outputs it to the mute circuit 108.

  The mute circuit 108 performs a mute process according to the mute signal on the FM signal input from the FM detection circuit 104. That is, the level of the output signal to the buffer 110 or the like is reduced as the received electric field strength data becomes smaller.

The digital control circuit 107 includes a plurality of logic circuits that generate mute signals. Each logic circuit realizes different mute characteristics.
In the above description, the soft mute circuit according to the embodiment of the present invention includes the ADC circuit 106, the digital control circuit 107, and the mute circuit 108.

  FIG. 2 is a diagram illustrating a soft mute circuit according to an embodiment of the present invention. The soft mute circuit according to this embodiment includes an ADC circuit 106, a digital control circuit 107, and a mute circuit 108. The ADC circuit 106 converts an analog signal (received electric field intensity) into a digital signal (received electric field intensity data). Description is omitted because it is a general circuit for converting to.

The digital control circuit 107 includes logic circuits 107a and 107b and a switch SWb that selects the logic circuit.
The logic circuits 107 a and 107 b operate independently, and generate a mute signal according to the received electric field strength data input from the ADC circuit 106. Note that the mute signal according to the present embodiment is, for example, a 4-bit control signal for controlling ON / OFF of the switches SW0 to SW15 of the mute circuit 108.

  Therefore, the logic circuits 107a and 107b adjust the gain of the mute circuit 108 by controlling ON / OFF of the switches SW0 to SW15 according to the received electric field strength data, thereby realizing a predetermined mute characteristic.

  The logic circuits 107a and 107b in the digital control circuit 107 according to the present embodiment can be realized by, for example, an FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device).

The mute circuit 108 includes an operational amplifier 21, a resistor Ra and resistors R0 to R15, and switches SW0 to SW15 that are switched ON / OFF according to a mute signal.
The resistors R0 to R15 of the negative feedback section are connected in series. In this embodiment, the resistance value of the resistor R0 is r, and the resistance value of the resistors R1 to R15 is 2r. The resistance value of the resistor Ra is 31r. However, this is for the sake of simplicity, and does not limit the resistance values of the resistors R0 and R1 to R15. An appropriate resistance value may be used as necessary.

  Further, SW0 to SW15 are connected between the resistors of the negative feedback section, and the resistance value can be changed from r to 31 * r by switching on / off according to the mute signal from the digital control circuit 107.

Here, the gain of the mute circuit 108 can be obtained by the following equation (1).
Gain = 20 * log ((r + 2r * n) / 31r)
= 20 * log ((1 + 2 * n) / 31) (1)
Therefore, in the soft mute circuit according to the present embodiment, the gain can be changed from −29.8 to 0.0 by controlling the mute circuit 108 by the digital control circuit 107.

The operation of the digital control circuit 107 according to the embodiment of the present invention will be described below with reference to FIGS.
FIG. 3 is a diagram for explaining the operation of the logic circuit 107a according to the embodiment of the present invention. The table shown in FIG. 3 shows the relationship between the received electric field strength detected by the RSSI circuit 105, the received electric field strength data obtained by digitizing the received electric field strength, and the switch that is turned on according to the received electric field strength data.

  For example, when the logic circuit 107a receives the received electric field strength data “001011 (binary number, the same applies hereinafter)” from the ADC circuit 106, the mute signal is transmitted to the mute circuit 108 to turn on the switch SW1 and other switches. Is turned off. Similarly, when receiving the received electric field strength data “001100” from the ADC circuit 106, the logic circuit 107a transmits a mute signal to the mute circuit 108 to turn on the switch SW2 and turn off the other switches.

  Similarly, a mute signal corresponding to the received electric field strength data sequentially received from the ADC circuit 106 is transmitted to the mute circuit 108 to switch ON / OFF of the switches SW0 to SW15.

  FIG. 4 is a diagram for explaining the operation of the logic circuit 107b according to the embodiment of the present invention. 4, the received electric field strength detected by the RSSI circuit 105, the received electric field strength data obtained by digitizing the received electric field strength, and a switch that is turned on according to the received electric field strength data, as in FIG. The relationship is shown.

  For example, when the logic circuit 107b receives the received field strength data “001100” or “001101” from the ADC circuit 106, the logic circuit 107b transmits a mute signal to the mute circuit 108 to turn on the switch SW1 and turn off the other switches. Put it in a state. Similarly, when the logic circuit 107b receives the reception field strength data “001110” or “001111” from the ADC circuit 106, the logic circuit 107b transmits a mute signal to the mute circuit 108 to turn on the switch SW2 and turn off the other switches. Put it in a state.

Similarly, a mute signal corresponding to the received electric field strength data sequentially received from the ADC circuit 106 is transmitted to the mute circuit 108 to switch the switch ON / OFF.
Here, in order for the logic circuits 107a and 107b to switch the switches SW0 to SW15 as described above by a mute signal, for example, a transfer gate configured by connecting a p-channel MOS transistor and an n-channel MOS transistor in parallel is used. Then, it is only necessary to generate a mute signal for setting the gate voltage of the transfer gate constituting the target switch to High.

  Through the processing described above, the FM signal detected by the FM detection circuit 104 is subjected to mute processing according to the mute signal from the digital control circuit 107 in the operational amplifier 21 and is output to the buffer 110 or the like.

FIG. 5 is a diagram illustrating a mute characteristic of the soft mute circuit according to the embodiment of the present invention.
FIG. 5 shows the relationship between the received electric field intensity detected by the RSSI circuit 105 and the gain of the mute circuit 108.

  The mute characteristic indicated by the solid line indicates the mute characteristic obtained when the mute circuit 108 is controlled by the logic circuit 107a that performs the operation shown in FIG. Further, the mute characteristic indicated by the one-dot broken line indicates the mute characteristic obtained when the mute circuit 108 is controlled by the logic circuit 107b performing the operation shown in FIG.

As shown in FIG. 5, different mute characteristics can be obtained by switching the logic circuit operating in the digital control circuit 107.
In the above description, the digital control circuit 107 according to the present embodiment shows an example in which a logic circuit that realizes two different mute characteristics is used. However, the present invention is not limited to this. Of course, the digital control circuit 107 may be provided with a plurality of logic circuits that realize different mute characteristics as required.

  As described above, a desired mute characteristic can be obtained by providing a plurality of logic circuits that realize different mute characteristics in the digital control circuit and switching the logic circuit to be used as necessary.

  As a result, it is possible to realize a soft mute circuit that realizes mute characteristics according to various uses (requests) of users. In addition, it is possible to provide a radio IC that realizes mute characteristics according to various uses (requests) of a user with one IC, and it is possible to reduce manufacturing costs.

It is a block diagram which shows the structural example of the FM radio receiver which uses the soft mute circuit based on the Example of this invention. It is a figure explaining the soft mute circuit based on the Example of this invention. It is a figure explaining operation | movement of the logic circuit 107a based on the Example of this invention. It is a figure explaining operation | movement of the logic circuit 107b which concerns on the Example of this invention. It is a figure which shows the mute characteristic of the soft mute circuit based on the Example of this invention.

Explanation of symbols

104 ... FM detection circuit 105 ... RSSI circuit 106 ... ADC circuit 107 ... digital control circuit 107a ... logic circuit 107b ... logic circuit 108 ... mute circuit

Claims (3)

In the soft mute circuit that adjusts the signal level of the FM signal according to the received electric field strength,
A mute circuit having a resistance value switching means for switching a resistance value, and adjusting the signal level to an arbitrary level by switching the resistance value;
A digital conversion circuit that digitizes the received electric field strength to generate received electric field strength data;
A plurality of logic circuits for realizing a predetermined mute characteristic by operating the resistance value switching means according to the received electric field strength data, and a selection means for selecting a logic circuit for realizing a desired mute characteristic from the plurality of logic circuits A digital control circuit comprising:
A soft mute circuit. The mute circuit is an inverting amplifier circuit having the resistance value switching means in a negative feedback section.
The soft mute circuit according to claim 1. The logic circuit realizes a mute characteristic that decreases the signal level as the received electric field strength data decreases.
The soft mute circuit according to claim 1.

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