JP2008278117A - Offset cancel circuit of digital to analog converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an offset cancel circuit capable of canceling an offset of a DAC (Digital to Analog Converter), without incurring increase in the size of a chip or the number of terminals. <P>SOLUTION: The offset cancel circuit is a means for canceling an offset of a digital to analog converter 3 which converts a digital input signal DI into an analog output voltage AO. The circuit comprises a comparator 7 comparing the analog output voltage AO with a predetermined bias voltage BIAS to generate a comparison result signal SBO, a first computation unit 8 for generating a feedback signal phO according to the digital input signal DI and the comparison result signal SBO, an integrator 10 for integrating the feedback signal phO to generate an integration result signal (Σ(A×phO) in Figure 1), and a second computation unit 11 for applying feedback to the digital input signal DI according to the integration result signal to output a corrected digital input signal DI' to the digital to analog converter 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an offset cancel circuit of a digital / analog converter (hereinafter referred to as DAC [Digital / Analog Converter]), and an electric device using the same.

  FIG. 5 is a block diagram showing a conventional example of an audio device equipped with a DAC.

  The audio apparatus according to the conventional example includes a DAC 101, a high-pass filter (coupling capacitor) 102, a speaker amplifier 103, a line output switch 104, and a buffer amplifier 105, and a digital sound source (CD) (not shown). A digital input signal DI input from a player or the like is converted into an analog output voltage AO to perform speaker output or line output.

  In the audio apparatus having the above-described configuration, the offset generated by the DAC 101 (the difference between the analog output voltage AO and the bias voltage BIAS when there is no sound) may cause a pop sound generated when the line output is switched on / off. In the case of speaker output, power consumption is increased when there is no sound.

  Therefore, in the conventional audio equipment, as shown in FIG. 5, offset countermeasures for the DAC 101 are taken by providing a high-pass filter 102 between the DAC 101 and the speaker amplifier 103 or using a soft switch as the line output switch 104. It was.

  As an example of conventional technology related to DAC offset cancellation, Patent Document 1 discloses a waveform generator that generates a digital modulation signal waveform corresponding to transmission data and band-limited, and the digital modulation signal waveform and In a digital wireless communication apparatus including an analog front end that converts an addition output of correction data into a differential output analog signal and a quadrature converter that modulates a carrier wave with the differential output of the analog front end, the analog signal is output when not transmitting. A voltage comparator for detecting a front-end differential offset, and by correcting the negative offset detected by the voltage comparator in a negative direction and correcting it in a positive direction when it is negative. A digital wireless communication apparatus comprising: a correction data generation circuit for reducing a differential offset It has been proposed.

  Further, Patent Document 2 discloses a digital / analog converting means for converting a speed command supplied to a servo amplifier from a digital value to an analog signal, an amplifying means for amplifying the converted analog signal, and the amplified servo signal. An offset changing unit that changes an offset of an analog signal supplied to an amplifier, and an offset adjusting device that adjusts the offset by changing a resistance value of a variable resistor provided in the offset changing unit. As the variable resistor, a control variable resistance means whose resistance value can be varied by an external control signal, a detection means for detecting an analog signal supplied to the servo amplifier, and the detected analog signal is digitally converted. Analog-to-digital conversion means for converting to a value and the offset based on the converted digital value. As bets are reduced, and a control means for changing the resistance value, the offset adjustment apparatus comprising the disclosed and propose outputs the control signal to the controlled variable resistance means.

In addition, as an example of conventional technology related to a soft switch, Patent Document 3 discloses an analog switch in which an NMOS transistor and a PMOS transistor are connected in parallel, and the analog switch by controlling the gate voltage of the NMOS transistor and the PMOS transistor. A soft changeover switch is disclosed and proposed, which includes a switch control circuit that complements the on-resistance in an intermediate state between the on-state and the off-state.
Japanese Patent Application Laid-Open No. 07-030596 JP 2002-095285 A JP 2004-194118 A

  Certainly, with the conventional configuration shown in FIG. 5, even if an offset occurs in the DAC 101, the above-described problem does not become apparent.

  However, in the conventional configuration in which the high-pass filter 102 is provided, a coupling capacitor must be built in or externally attached to the IC, which increases the chip size and the number of terminals, and further increases the cost. It was.

  In the conventional configuration using a soft switch as the line output switch 104, an increase in circuit scale has been a problem.

  On the other hand, it is conceivable to cancel the offset of the DAC 101 itself by the trimming process. For this purpose, a trimming fuse must be built in the IC, and this leads to an increase in chip size and cost. It was the same.

  Note that the prior art of Patent Document 1 is a technique for canceling a differential offset, and has an essential configuration different from that of the present invention.

  In addition, the prior art of Patent Document 2 requires an analog / digital conversion circuit and a microcomputer, which increases the circuit scale and increases the cost.

  In view of the above problems, the present invention provides an offset cancel circuit capable of appropriately canceling an offset of a digital / analog converter without increasing the chip size or the number of terminals, and an electric circuit using the offset cancel circuit. The purpose is to provide equipment.

  In order to achieve the above object, an offset cancel circuit according to the present invention is an offset cancel circuit for canceling an offset of a digital / analog converter that converts a digital input signal into an analog output voltage. A comparison unit that compares the bias voltages of the first and second comparators to generate a comparison result signal, a first calculation unit that generates a feedback signal according to the digital input signal and the comparison result signal, and an integration result obtained by integrating the feedback signal An integration unit that generates a signal; and a second operation unit that feeds back the digital input signal in accordance with the integration result signal and outputs the corrected digital input signal to the digital / analog converter. It is set as the structure (1st structure) which consists of.

  In the offset cancellation circuit having the first configuration, the first calculation unit includes an expected value generation unit that generates an expected value of the comparison result signal according to the digital input signal, and an actual value of the comparison result signal. And a feedback signal generation unit that generates the feedback signal by taking a difference between the expected value and the expected value (second configuration).

  Further, in the offset cancel circuit having the second configuration, the expected value generation unit is configured to delay the output of the expected value by a group delay in the digital / analog converter (third configuration). Good.

  In the offset cancel circuit having the second or third configuration, the feedback signal generation unit may multiply a difference value between an actual value and an expected value of the comparison result signal by a coefficient proportional to the digital input signal. Thus, the configuration for generating the feedback signal (fourth configuration) may be used.

  Further, in the offset cancel circuit having any one of the first to fourth configurations, the integration unit includes a limiter function for limiting the integration result signal so as not to exceed a predetermined upper limit value or lower limit value. (Fifth configuration) is preferable.

  The offset cancel circuit having any one of the first to fifth configurations includes a feedback amount adjustment unit that multiplies the feedback signal by a predetermined coefficient and then outputs the feedback signal to the integration unit (sixth configuration). Configuration).

  In the offset cancel circuit having the sixth configuration, the feedback amount adjustment unit may be configured to set a coefficient to be multiplied by the feedback signal to be larger than normal (seventh configuration) during a predetermined calibration period. .

  The offset cancel circuit having any one of the first to seventh configurations includes an input control unit that uses the digital input signal as a no-signal code during a predetermined calibration period (eighth). (Configuration).

  The offset cancel circuit having any one of the first to eighth configurations includes an output control unit that prohibits external output of the analog output voltage during a predetermined calibration period (ninth configuration). ).

  In the offset cancel circuit having any one of the seventh to ninth configurations, the calibration period may be set to a configuration (tenth configuration) set immediately after the circuit is activated.

  Further, in the offset cancel circuit having any one of the seventh to tenth configurations, the first calculation unit is a code when the digital input signal is no signal or a code in the vicinity thereof after the calibration period has elapsed. At this time, a configuration (eleventh configuration) for outputting a zero value as the feedback signal may be used.

  An electrical apparatus according to the present invention includes a digital / analog converter that converts a digital input signal into an analog output voltage, and an offset cancellation circuit having any one of the first to eleventh configurations. (Twelfth configuration).

  With the offset cancel circuit according to the present invention and an electric device using the same, it is possible to appropriately cancel the offset of the digital / analog converter without increasing the chip size or the number of terminals.

  FIG. 1 is a block diagram illustrating an embodiment of an audio device including a DAC.

  As shown in FIG. 1, the audio device according to the present embodiment has a serial interface unit 1, a × 8 interpolator 2, a DAC 3, a speaker amplifier 4, a line output switch 5, and a buffer amplifier 6. A unit 7, a first calculation unit 8, a feedback amount adjustment unit 9, an integration unit 10, a second calculation unit 11, and a speaker output switch 12 are included.

  The serial interface unit 1 is means for converting a serial signal (reproduced audio data) input from a digital sound source (not shown) such as a CD player into a parallel signal and sending the parallel signal to the x8 interpolator 2. The serial interface unit 1 of the present embodiment receives the parallel signal (and thus the digital input signal DI transmitted from the x8 interpolator 2) during the predetermined calibration period as the center code when there is no signal. The mute function is provided, which will be described in detail later.

  The x8 interpolator 2 is means for generating a desired digital input signal DI by performing predetermined oversampling interpolation processing on the parallel signal input from the serial interface unit 1.

  The DAC 3 converts a digital input signal DI (more precisely, a corrected digital input signal DI ′ input via the second arithmetic unit 11) input from the x8 interpolator 2 into an analog output voltage AO. It is. Note that any conversion method such as the ΔΣ method may be used as the conversion method of the DAC 3.

  The speaker amplifier 4 is means for amplifying the analog output voltage AO input through the speaker output switch 12 with a predetermined gain and driving the speaker using the amplified output.

  The line output switch 5 is a means (output control unit) for prohibiting line output of the analog output voltage AO during a predetermined calibration period, and either one of the analog output voltage AO and the predetermined bias voltage BIAS is output as the line output voltage. Is selectively output to the buffer amplifier 6.

  The buffer amplifier 6 is means for buffering and amplifying the line output voltage input from the line output switch 5 and outputting it to the outside of the apparatus.

  The comparator 7 is an analog comparator that compares the analog output voltage AO with a predetermined bias voltage BIAS (a reference voltage to be output from the DAC 3 when there is no signal) to generate a comparison result signal SBO. Note that the comparator 7 of this embodiment is configured such that the analog output voltage AO is applied to the inverting input terminal (−) and the bias voltage (+) is applied to the non-inverting input terminal (+). Therefore, the comparison result signal SBO becomes high level (H) when the analog output voltage AO is lower than the bias voltage BIAS, and conversely, becomes low level (L) when the analog output voltage AO is higher than the bias voltage BIAS. Become.

  The first calculation unit 8 is a unit that generates a feedback signal phO in accordance with the digital input signal DI and the comparison result signal SBO, and includes an expected value generation unit 8a and a feedback signal generation unit 8b.

  The expected value generation unit 8a is means for generating an expected value SBI of the comparison result signal SBO according to the digital input signal DI.

  In the present embodiment, the expected value generation unit 8a determines whether the digital input signal DI and predetermined threshold values + ZLV, -ZLV (the digital input signal DI is a center code at the time of no signal or a code in the vicinity thereof. And a digital comparator that generates an expected value SBI of three values (high level (H) / middle level (M) / low level (L)).

  The expected value generation unit 8a is configured to delay the output of the expected value SBI by the group delay in the DAC 3. With this configuration, the timing at which the actual value of the comparison result signal SBO is input to the feedback signal generation unit 8b can be matched with the timing at which the expected value SBI is input. Can be generated.

  The feedback signal generation unit 8b is means for generating a feedback signal phO by taking the difference between the actual value of the comparison result signal SBO and the expected value SBI.

  The operation of the first calculation unit 8 having the above configuration will be described in detail later.

  The feedback amount adjustment unit 9 is a unit that multiplies the feedback signal phO by a predetermined coefficient A and outputs the multiplication result to the integration unit 10. With the configuration having such a feedback amount adjusting unit 9, it is possible to arbitrarily control the strength of feedback control by changing the coefficient A.

  The integration unit 10 integrates the feedback signal phO input from the first calculation unit 8 (more precisely, the adjusted feedback signal A × phO input through the feedback amount adjustment unit 9), and the integration result. This is means for generating a signal Σ (A × phO).

  Note that the integration unit 10 of this embodiment includes a limiter function that limits the integration result signal Σ (A × phO) so as not to exceed a predetermined upper limit value or lower limit value. With this configuration, it is possible to prevent excessive feedback from being applied to the digital input signal DI.

  The second arithmetic unit 11 is a means (feedback in this embodiment) that feeds back the digital input signal DI according to the integration result signal Σ (A × phO) and outputs the corrected digital input signal DI ′ to the DAC 3. is there.

  The speaker output switch 12 is a means (output control unit) that is provided between the DAC 3 and the speaker amplifier 4 and prohibits the speaker output of the analog output voltage AO during a predetermined calibration period.

  Next, the operation of generating the feedback signal phO by the first arithmetic unit 8 will be described in detail with reference to FIGS.

  FIG. 2 is a logical value table for explaining the operation of generating the feedback signal phO, showing the correlation among the digital input signal DI, the expected value SBI, the actual value of the comparison result signal SBO, and the feedback signal phO. Yes. In FIG. 2, three types of feedback signals phO (type 1 to type 3) are shown, but here, a detailed description is given by taking as an example the case where a type 1 feedback signal phO is generated. To do.

  FIGS. 3A and 3B are waveform diagrams for explaining the operation of generating the feedback signal phO, respectively, and the digital input signal DI and analog are sequentially shown from the upper side of the drawing with the horizontal axis as the time axis. The behavior of the output voltage AO, the expected value SBI, the actual value of the comparison result signal SBO, and the feedback signal phO is shown. FIG. 3A shows a case where a positive offset occurs, and FIG. 3B shows a case where a negative offset occurs.

  As shown in FIG. 2, when the digital input signal DI is less than the threshold value −ZLV, the expected value generation unit 8a expects the analog output voltage AO to be lower than the bias voltage BIAS, and the expected value SBI is set to the high level (H ) Is output. At this time, if the actual value of the comparison result signal SBO is a high level (H), the feedback signal generator 8b outputs a zero value (0) as the feedback signal phO (= SBI (H) −SBO (H)). To do. On the other hand, if the actual value of the comparison result signal SBO is a low level (L), the feedback signal generator 8b outputs a positive value (+1) as the feedback signal phO (= SBI (H) −SBO (L)). .

  As shown in FIG. 3A, when a positive offset occurs in the DAC 3, the timing when the digital input signal DI crosses the threshold −ZLV and the timing when the analog output voltage AO crosses the bias voltage BIAS. An error period (a period in which the actual value of the comparison result signal SBO is at the low level (L) and the expected value SBI is at the high level (H)) occurs between the DAC 3 and the error period is positive. A feedback signal phO having a value (+1) is output. As a result, since the value of the integration result signal Σ (A × phO) subtracted from the digital input signal DI is increased, feedback is applied in the direction of canceling the positive offset of the DAC 3.

  As shown in FIG. 2, when the digital input signal DI is larger than the threshold value + ZLV, the expected value generation unit 8a expects the analog output voltage AO to be higher than the bias voltage BIAS, and the expected value SBI is low level ( L) is output. At this time, if the actual value of the comparison result signal SBO is a low level (L), the feedback signal generator 8b outputs a zero value (0) as the feedback signal phO (= SBI (L) −SBO (L)). To do. On the other hand, if the actual value of the comparison result signal SBO is high level (H), the feedback signal generator 8b outputs a negative value (−1) as the feedback signal phO (= SBI (L) −SBO (H)). To do.

  As shown in FIG. 3B, when a negative offset occurs in the DAC 3, the timing between the digital input signal DI straddling the threshold value + ZLV and the timing at which the analog output voltage AO straddles the bias voltage BIAS. In addition, an error period corresponding to the negative offset of the DAC 3 (a period in which the actual value of the comparison result signal SBO is high level (H) and the expected value SBI is low level (L)) occurs, and the error period has a negative value. The feedback signal phO of (-1) is output. As a result, the value of the integration result signal Σ (A × phO) subtracted from the digital input signal DI becomes small, so that feedback is applied in the direction of canceling the negative offset of the DAC 3.

  However, even if a positive or negative offset occurs in the DAC 3, the difference between the expected value SBI and the actual value of the comparison result signal SBO is zero (0) in the range where the absolute value of the digital input signal DI is sufficiently large. Therefore, the value of the integration result signal Σ (A × phO) does not change.

  That is, the offset cancel circuit of the present embodiment is configured such that when the DAC 3 has an offset, the zero cross timing of the digital input signal DI (the timing at which the digital input signal DI straddles the center code when there is no signal) and the analog output voltage AO It was created by paying attention to the fact that an error occurs between the zero cross timing (the timing at which the analog output voltage AO crosses the bias voltage BIAS), and in the vicinity of the zero cross of the digital input signal DI (center) so as to eliminate the error. Only in the vicinity of the code), the offset correction amount (integration result signal Σ (A × phO)) is updated.

  On the other hand, as shown in FIG. 2, when the digital input signal DI is not less than the threshold value −ZLV and not more than the threshold value + ZLV, the expected value generating unit 8a outputs the middle level (M) as the expected value SBI for convenience. At this time, if the actual value of the comparison result signal SBO is low level (L), the feedback signal generation unit 8b outputs a positive value (+1) as the feedback signal phO (= SBI (M) −SBO (L)). To do. On the other hand, if the actual value of the comparison result signal SBO is high level (H), the feedback signal generator 8b outputs a negative value (−1) as the feedback signal phO (= SBI (M) −SBO (H)). To do.

  That is, when the feedback signal generation unit 8b determines that the digital input signal DI is the center code at the time of no signal or a code in the vicinity thereof, the actual value of the comparison result signal SBO is regarded as the offset of the DAC 3 and is canceled. The feedback signal phO is generated as described above.

  FIG. 4 is a waveform diagram for explaining the offset cancel operation in the audio device of the present embodiment. The digital input signal DI, the feedback signal phO, and the offset amount are sequentially arranged from the upper side of the drawing with the horizontal axis as the time axis. The behavior of is shown. FIG. 4 shows how the positive offset of the DAC 3 is canceled.

  As shown in FIG. 4, in the audio device of the present embodiment, a calibration period of a predetermined length (several tens to several hundreds [ms]) is set immediately after activation.

  During the calibration period, the serial interface unit 1 ignores the input serial signal and sends it to the x8 interpolator 2 (and thus the digital input signal sent from the x8 interpolator 2). DI) is the center code when there is no signal.

  Therefore, the expected value generation unit 8a outputs the middle level (M) as the expected value SBI, and the feedback signal generation unit 8b regards the actual value of the comparison result signal SBO as an offset of the DAC 3 and cancels it. Operate to generate feedback signal phO.

  That is, as shown in FIG. 4, when a positive offset occurs in the DAC 3, a positive value (+1) feedback signal phO is continuously output during the calibration period until this is canceled. It will be.

  During the calibration period, the speaker output switch 12 blocks the signal path from the DAC 3 to the speaker amplifier 4 so as to prohibit the speaker output of the analog output voltage AO. Further, the line output switch 5 selectively outputs the bias voltage BIAS to the buffer amplifier 6 so as to prohibit the line output of the analog output voltage AO. With such a configuration, it is possible to prevent power from being consumed by the speaker and pop noise from being generated in the line output during the calibration period.

  Further, during the calibration period, the feedback amount adjustment unit 9 sets the coefficient A by which the feedback signal phO is multiplied to be larger than usual. With such a configuration, it is possible to quickly cancel the offset of the DAC 3.

  When the calibration period elapses, the serial interface unit 1 releases the mute of the digital input signal DI, and the speaker output switch 12 and the line output switch 5 permit the external output of the analog output voltage AO. In the feedback amount adjusting unit 9, the coefficient A multiplied by the feedback signal phO is returned to the normal value. At this time, since the offset of the DAC 3 is completely or sufficiently reduced through the calibration period, the increase in power consumption of the speaker and the pop sound of the line output due to the offset of the DAC 3 are eliminated, or It becomes possible to reduce.

  Thereafter, as described with reference to FIG. 2 and FIG. 3, the feedback signal phO is generated by taking the difference between the actual value of the comparison result signal SBO and the expected value SBI, and the integration result signal Σ ( In accordance with (A × phO), feedback is applied in a direction in which the offset of the DAC 3 is canceled.

  As the offset cancellation of the DAC 3 proceeds, a positive value (+1) and a negative value (−1) appear at the same frequency as the feedback signal phO, and the value of the integration result signal Σ (A × phO) is Stabilizes and completes a series of offset cancel operations.

  As described above, the offset cancel circuit according to the present invention compares the analog output voltage AO with the predetermined bias voltage BIAS to generate the comparison result signal SBO, the digital input signal DI, and the comparison result. A first calculation unit 8 that generates a feedback signal phO according to the signal SBO, an integration unit 10 that integrates the feedback signal phO to generate an integration result signal Σ (A × phO), and an integration result signal Σ (A × phO) ) In response to the digital input signal DI, and outputs a corrected digital input signal DI ′ to the DAC 3.

  With such a configuration, the offset of the DAC 3 can be canceled appropriately without using an analog / digital conversion circuit or a microcomputer. Therefore, it is not necessary to provide a high-pass filter after the DAAC 3, and it is not necessary to use a soft switch as the line output switch 5. Therefore, it is possible to reduce the chip size and the number of terminals. Further, the offset cancel circuit according to the present invention can dynamically correct the offset even during the normal operation of the DAC 3.

  In the offset cancel circuit according to the present invention, since the offset characteristic of the analog output voltage AO is determined according to the offset characteristic of the comparator 7, a low-offset comparator 7 is necessary, but for the offset cancellation of the DAC 3 itself. In comparison, the low offset comparator 7 can be easily realized.

  Further, in the above embodiment, the explanation has been given by taking the offset cancel circuit of the audio reproduction DAC mounted on the audio player or the like as an example. However, the application target of the present invention is not limited to this, and the FM is not limited thereto. The present invention can be widely applied to all DAC offset cancellation circuits that handle a digital input signal that is a predetermined center code when there is no signal, such as an FM modulation DAC offset cancellation circuit mounted on a transmitter or the like.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  For example, in the above-described embodiment, a configuration in which the existing serial interface unit 1 has a mute function as an input control unit that uses the digital input signal DI as a center code when there is no signal during a predetermined calibration period is exemplified. Although described, the configuration of the present invention is not limited to this, and any configuration may be adopted as long as a similar operation can be realized.

  Further, in the above embodiment, the actual value of the comparison result signal SBO is regarded as the offset of the DAC 3 as the feedback signal phO when the digital input signal DI is the center code at the time of no signal or a code in the vicinity thereof, and this is canceled. The configuration for generating the feedback signal phO (see type 1 in FIG. 2) has been described as an example. However, the configuration of the present invention is not limited to this, and for example, the first arithmetic unit 8 Is configured to output a zero value (0) as the feedback signal phO when the digital input signal DI is a code at the time of no signal or a code in the vicinity thereof after the calibration period has elapsed (the type 2 in FIG. 2). Reference).

  Thus, if the offset correction amount (integration result signal Σ (A × phO)) is not updated when the digital input signal DI is at a very small signal level (equivalent to zero), the noise superimposed on the analog output voltage AO is reduced. As a result, even when the logic of the comparison result signal SBO becomes unstable, it is possible to minimize the influence on the offset cancel operation.

  In the above embodiment, the difference value (+1 or −1) between the actual value of the comparison result signal SBO and the expected value SBI is directly output as the positive or negative feedback signal phO (type 1 in FIG. 2). However, the configuration of the present invention is not limited to this. For example, the feedback signal generation unit 8b uses the actual value and the expected value of the comparison result signal SBO. The feedback signal phO may be generated by multiplying the difference value (+1 or −1) from SBI by a coefficient (K × DI) proportional to the digital input signal DI (see type 3 in FIG. 2). With this configuration, it is possible to control the strength of feedback control according to the magnitude of the digital input signal DI. In addition, when employ | adopting the said structure, it is good to set threshold value + ZLV and -ZLV slightly.

  In the above embodiment, when the operation of generating the feedback signal phO in the first arithmetic unit 8 is described, a configuration in which the feedback signal phO is generated by taking the difference between the actual value of the comparison result signal SBO and the expected value SBI. Although described by way of example, the configuration of the present invention is not limited to this, as long as the feedback signal phO similar to the above can be generated according to the digital input signal DI and the comparison result signal SBO. Any calculation process may be performed by the first calculation unit 8.

  The present invention is a very useful technique for canceling an offset of a DAC (sound reproduction DAC, FM modulation DAC, etc.) that handles a digital input signal that becomes a predetermined center code when there is no signal.

FIG. 2 is a block diagram illustrating an embodiment of an audio device including a DAC. FIG. 4 is a logical value table for explaining the operation of generating the feedback signal phO. These are waveform diagrams for explaining the operation of generating the feedback signal phO. These are waveform diagrams for explaining an offset cancel operation. These are the block diagrams which show the prior art example of the audio equipment provided with DAC.

Explanation of symbols

1 Serial interface part (input control part)
2 x 8 interpolator (oversampling interpolator)
3 Digital / analog converter (DAC)
4 Speaker amplifier 5 Line output switch (Output controller)
6 Buffer amplifier 7 Comparison part (analog comparator)
8 First operation unit 8a Expected value generation unit (digital comparator)
8b Feedback signal generation unit 9 Feedback amount adjustment unit 10 Integration unit 11 Second operation unit (digital subtractor)
12 Speaker output switch (output controller)
DI Digital input signal DI 'Correction digital input signal AO Analog output voltage BIAS Bias voltage SBO Comparison result signal (actual value)
SBI Expected value phO Feedback signal

Claims (12)

  An offset cancel circuit for canceling an offset of a digital / analog converter that converts a digital input signal into an analog output voltage, and compares the analog output voltage with a predetermined bias voltage to generate a comparison result signal; A first calculation unit that generates a feedback signal according to the digital input signal and the comparison result signal; an integration unit that integrates the feedback signal to generate an integration result signal; and the digital signal according to the integration result signal. An offset cancellation circuit, comprising: a second arithmetic unit that applies feedback to the input signal and outputs the corrected digital input signal to the digital / analog converter.   A first calculation unit configured to generate an expected value of the comparison result signal according to the digital input signal; and taking a difference between an actual value and an expected value of the comparison result signal to obtain the feedback signal. The offset cancellation circuit according to claim 1, further comprising a feedback signal generation unit that generates the offset signal generation unit.   The offset cancellation circuit according to claim 2, wherein the expected value generation unit delays the output of the expected value by a group delay in the digital / analog converter.   The feedback signal generation unit generates the feedback signal by multiplying a difference value between an actual value and an expected value of the comparison result signal by a coefficient proportional to the digital input signal. Item 4. The offset cancel circuit according to Item 3.   The offset cancel according to any one of claims 1 to 4, wherein the integration unit includes a limiter function for limiting the integration result signal so as not to exceed a predetermined upper limit value or lower limit value. circuit.   6. The offset cancel circuit according to claim 1, further comprising a feedback amount adjustment unit that multiplies the feedback signal by a predetermined coefficient and outputs the multiplication result to the integration unit.   The offset cancellation circuit according to claim 6, wherein the feedback amount adjustment unit sets a coefficient to be multiplied by the feedback signal larger than normal during a predetermined calibration period.   8. The offset cancel circuit according to claim 1, further comprising an input control unit that uses the digital input signal as a no-code code during a predetermined calibration period.   9. The offset cancel circuit according to claim 1, further comprising an output control unit that prohibits external output of the analog output voltage during a predetermined calibration period.   The offset cancellation circuit according to claim 7, wherein the calibration period is set immediately after the circuit is activated.   The first arithmetic unit outputs a zero value as the feedback signal when the digital input signal is a code at the time of no signal or a code in the vicinity thereof after the calibration period elapses. The offset cancel circuit according to claim 10.   An electrical apparatus comprising: a digital / analog converter that converts a digital input signal into an analog output voltage; and an offset cancel circuit according to any one of claims 1 to 11.

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