JP2007335827A - Fine particles layer structure and forming method of same, semiconductor device, and separation region - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with no contamination, damage, and disturbance in a fine particle layer, provided with a fine particles layer structure including a separated fine particle layer. <P>SOLUTION: A semiconductor device has (A) a wall-like two layer structure formed on a substrate 11, with a side wall of a lower layer 31 composed of a separation region 30 having an undercut shape with respect to the side wall of an upper layer 32, and (B) an active element formed on a part of the substrate 11 surrounded by the separation region 30. The active element includes fine particles 22 composed of a conductor or a semiconductor and a conductive route 21 formed of an organic semiconductor molecule bonded to the fine particles 22, and the fine particle layer 20 composed of the fine particles 22 is separated at the side wall of the separation region 30. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a fine particle layer structure, a method for forming the same, a semiconductor device, and a separation region.

  In recent years, various devices using fine particles (nanoparticles) have been actively studied. Nanoparticles often exhibit physical properties different from those in the bulk state because of their characteristic small size. For example, in the case of nanometer-sized fine particles, the ratio of the surface-to-volume ratio to the number of atoms in the interior is very large compared to the bulk. Development of applications such as type solar cells, molecular sensors, catalysts, and adsorption / desorption materials is underway. In addition, it is known that a specific quantum effect due to the smallness is expressed in terms of electrons, magnetism, and light. Nanodevices such as high-density memory using magnetic particles, light-emitting devices using semiconductor nanoparticles that generate color depending on size, and single-electron transistors using the Coulomb blockade phenomenon have attracted attention as devices for next-generation electronics. ing.

  Further, a semiconductor device having a conductive path composed of fine particles and organic semiconductor molecules bonded to the fine particles is known from, for example, Japanese Patent Application Laid-Open Nos. 2004-088090, 2005-210107, and 2006-080257. Furthermore, a method for forming a fine particle layer is known from, for example, WO2005 / 015792.

JP 2004-088090 A JP-A-2005-210107 JP 2006-080257 A WO2005 / 015792

  By the way, although it is an important technique to arrange fine particles (nanoparticles) in a single layer, close-packed, in a large area and in a state of being separated into a desired region, the achievement is achieved. It is very difficult. Japanese Patent Application Laid-Open No. 2004-088090, Japanese Patent Application Laid-Open No. 2005-210107, and Japanese Patent Application Laid-Open No. 2006-080257 do not mention any such separation technique.

  WO2005 / 015792 (for example, page 24, line 14 to page 25, line 12) and FIGS. 13A, 13B, and 13C disclose a method of forming a fine particle (nanoparticle) layer. Specifically, this method is a so-called lift-off method. Then, for example, the sacrificial layer 304 made of a photosensitive resist is finally removed using a solvent. However, when the sacrificial layer 304 is removed using a solvent, the MPN (molecularly protected monoparticle) 340 may be contaminated, and the MPN 340 may be damaged by the solvent. Furthermore, the arrangement of the formed monolayers of the fine particles (nanoparticles) may be disturbed.

  Accordingly, an object of the present invention is to provide a fine particle layer structure including a separated fine particle layer, which does not cause contamination, damage, disorder of arrangement, etc. in the fine particle layer, a method for forming the fine particle layer, and a semiconductor including the fine particle layer structure. An object of the present invention is to provide an apparatus and a separation region as a kind of base for obtaining such a separated fine particle layer.

In order to achieve the above object, the fine particle layer structure according to the first aspect of the present invention comprises:
(A) a separation region formed on a substrate, having a wall-like two-layer structure, in which a lower side wall is undercut, and
(B) a fine particle layer formed on the portion of the substrate surrounded by the separation region;
A fine particle layer structure comprising:
The fine particle layer is separated on the side wall of the separation region.

The method for forming the fine particle layer structure according to the first aspect of the present invention for achieving the above-described object comprises:
(A) After forming a resist layer having an opening on the substrate,
(B) A lower layer and an upper layer constituting the separation region are sequentially formed on the resist layer and on the portion of the base exposed in the opening, and then
(C) After etching the lower sidewall so that the lower sidewall is undercut,
(D) removing the resist layer and leaving an isolation region on the substrate;
(E) forming a particulate layer separated on the side wall of the separation region on the portion of the substrate surrounded by the separation region;
It comprises the process.

In order to achieve the above object, a semiconductor device according to the first aspect of the present invention includes:
(A) a separation region formed on a substrate, having a wall-like two-layer structure, in which a lower side wall is undercut, and
(B) an active element formed on the portion of the substrate surrounded by the isolation region;
A semiconductor device comprising:
The active element includes a fine particle made of a conductor or a semiconductor, and a conductive path made of an organic semiconductor molecule bonded to the fine particle,
The fine particle layer composed of the fine particles is separated on the side wall of the separation region.

  In order to achieve the above object, the separation region according to the first aspect of the present invention has a wall-like two-layer structure formed on a substrate, and the lower side wall is undercut. And

To achieve the above object, the fine particle layer structure according to the second aspect of the present invention comprises:
(A) a separation region having a wall-shaped single layer structure formed on a substrate and having a side wall in an undercut shape; and
(B) a fine particle layer formed on the portion of the substrate surrounded by the separation region;
A fine particle layer structure comprising:
The fine particle layer is separated on the side wall of the separation region.

The method for forming the fine particle layer structure according to the second aspect of the present invention for achieving the above object is as follows:
(A) After forming a photosensitive resin layer on the substrate, the resin layer is exposed and developed to leave a separation region on the substrate whose side wall is made of an undercut resin layer;
(B) forming a fine particle layer separated on the side wall of the separation region on the portion of the substrate surrounded by the separation region;
It comprises the process.

  In the method for forming a fine particle layer structure according to the second aspect of the present invention, the resin layer is a single layer as a whole, but the resin layer may be composed of one kind of resin or two kinds. It is good also as a laminated structure of the layer which consists of the above resin.

In order to achieve the above object, a semiconductor device according to the second aspect of the present invention includes:
(A) a separation region having a wall-shaped single layer structure formed on a substrate and having a side wall in an undercut shape; and
(B) an active element formed on the portion of the substrate surrounded by the isolation region;
A semiconductor device comprising:
The active element includes a fine particle made of a conductor or a semiconductor, and a conductive path made of an organic semiconductor molecule bonded to the fine particle,
The fine particle layer composed of the fine particles is separated on the side wall of the separation region.

  In order to achieve the above object, the separation region according to the second aspect of the present invention is characterized in that it has a wall-shaped single-layer structure formed on a substrate, and the side wall has an undercut shape. .

  The fine particle layer structure according to the first aspect and the second aspect of the present invention, a method for forming the structure, or a semiconductor device (hereinafter, these may be collectively referred to simply as the fine particle layer structure of the present invention). In some cases, the fine particle layer may be left on the top surface of the separation region, and in some cases, the fine particle layer is removed from the top surface of the separation region by some method (for example, peel-off method). It may be.

The fine particle layer structure according to the first aspect of the present invention including the above-described form, a method for forming the same, a semiconductor device, or a separation region (hereinafter collectively referred to as the first aspect of the present invention). The material constituting the lower layer and the material constituting the upper layer may be essentially any material as long as they are different materials, and may be an insulating material or have conductivity. It may be a material, an inorganic material, or an organic material (for example, a resist material commonly referred to as a photosensitive polyimide resin or a permanent resist). Examples of the combination of the constituent material and the constituent material of the upper layer) include (oxide, nitride) or (nitride, oxide). More specifically, SiO _x can be exemplified as the oxide, and SiN _Y can be exemplified as the nitride more specifically. However, it is not limited to these. The lower side wall becomes undercut (for example, the lower side wall has its upper end protruding beyond the portion where the lower side wall rises from the base, or the upper side wall has an upper portion on the lower side. For example, the lower side wall is etched so that the side wall protrudes from the side wall or the upper side wall protrudes from the lower side wall. In addition, the material constituting the lower layer and the upper layer is resistant to the solvent that constitutes the solution of the organic semiconductor molecule that is used when the organic semiconductor molecule and the fine particles are chemically bonded at the time of manufacturing the semiconductor device (organic solvent resistant Sex) is required. If the lower layer or the upper layer is dissolved by such a solvent, there is a possibility that the fine particle layer or the like is contaminated.

  In addition, the fine particle layer structure according to the second aspect of the present invention including the above form, a method for forming the same, a semiconductor device, or a separation region (hereinafter collectively referred to simply as the second aspect of the present invention) In some cases, an organic material (for example, a photosensitive polyimide resin or a resist material commonly referred to as a permanent resist) can be exemplified as a material constituting the separation region.

In the fine particle layer structure of the present invention including the form and configuration described above, when the average particle size of the fine particles is R _AVE , the height H of the separation region is (H / R _AVE ) ≧ 5 × 10 ^1. Preferably, (H / R _AVE ) ≧ 1 × 10 ² is satisfied. The length L of one side of the wall-shaped separation region satisfies (L / H) ≧ 1 × 10 ¹ , preferably (L / H) ≧ 1 × 10 ² . Here, the length L of one side of the wall-shaped separation region is the length (width) of the separation region lying between the portion of the substrate on which the active element is to be formed and the portion of the substrate on which the active element is to be formed. means. As described above, if the value of the height H of the separation region is not sufficiently larger than the value of the average particle diameter R _AVE of the fine particles, there is a possibility that the so-called “step break” does not occur reliably in the fine particle layer. If the value of the length L of one side of the wall-shaped separation region is not sufficiently larger than the value of the height H of the separation region as described above, for example, in the first aspect of the present invention, the lower side wall When the side wall of the lower layer is etched so as to have an undercut shape, there is a possibility that the laminated structure of the separation region composed of the lower layer and the upper layer cannot be maintained.

  The semiconductor device according to the first aspect or the second aspect of the present invention including the preferred embodiments and configurations described above (hereinafter, these may be collectively referred to as the semiconductor device of the present invention). Therefore, it is preferable that the functional group that the organic semiconductor molecule has at the terminal is chemically bonded to the fine particle, and further, the organic semiconductor molecule and the fine particle are chemically bonded to each other by the functional group that the organic semiconductor molecule has at both ends. It is preferable that a network-like conductive path is constructed by coupling (alternately). A conductive path may be constituted by a single layer of a conjugate of fine particles and organic semiconductor molecules, or a three-dimensional network-like conductive path is constituted by a laminated structure of a conjugate of fine particles and organic semiconductor molecules. May be. By constructing a network-like conductive path in this way, charge transfer in the conductive path occurs predominantly in the axial direction of the molecule along the main chain of the organic semiconductor molecule, and electron transfer between molecules in the conductive path As a result, the mobility is not limited by intermolecular electron movement, which was the cause of low mobility in semiconductor devices using conventional organic semiconductor materials, and the molecular movement in the axial direction. For example, since high mobility due to delocalized π electrons can be utilized to the maximum extent, it is possible to realize unprecedented high mobility.

  Furthermore, in the semiconductor device of the present invention, the conductive path can be used as a wiring or various electrodes, and the conductivity of the conductive path can be controlled by an electric field applied to the conductive path. In the latter case, the active element in the semiconductor device of the present invention includes a field effect transistor (FET) having a gate electrode, a gate insulating layer, a channel formation region, and source / drain electrodes, and forms a channel by a conductive path. It can be set as the structure where an area | region is comprised. In such a structure, it is possible to operate as an optical sensor or the like by using a dye that absorbs light near the visible region as an organic semiconductor molecule having a conjugated system.

In the fine particle layer structure and the like of the present invention including the preferred embodiments and configurations described above, the average particle diameter R _AVE of the fine particles is 5.0 × 10 ⁻¹⁰ m ≦ R _AVE , preferably 5. It is desirable that 0 × 10 ⁻¹⁰ m ≦ R _AVE ≦ 1.0 × 10 ⁻⁶ m, more preferably 5.0 × 10 ⁻¹⁰ m ≦ R _AVE ≦ 1.0 × 10 ⁻⁸ m. Examples of the shape of the fine particles include, but are not limited to, a spherical shape, a triangular shape, a tetrahedron, a cube, a rectangular parallelepiped, a cone, a cylindrical shape (rod), a triangular prism, a fiber shape, a hairball shape fiber, and the like. Can be mentioned. The average particle size R _AVE of the fine particles when the shape of the fine particles is other than a spherical shape is assumed to be a sphere having the same volume as the measured volume of the fine particles other than the spherical shape, and the average value of the diameters of the spheres is calculated as The particle size R _AVE may be used. The average particle size R _AVE of the fine particles can be obtained, for example, by measuring the particle size of the fine particles observed with a transmission electron microscope (TEM).

In the fine particle layer structure and the like of the present invention, the fine particles are gold (Au), silver (Ag), platinum (Pt), copper (Cu), aluminum (Al), palladium (Pd), chromium (Cr) as conductors. Made of metals such as nickel (Ni) and iron (Fe), or alloys made of these metals, or cadmium sulfide (CdSe), cadmium selenide (CdSe), and cadmium telluride as semiconductors. (CdTe), gallium arsenide (GaAs), titanium oxide (TiO ₂ ), or silicon (Si) can be used. The fine particles as a conductor refer to fine particles made of a material having a volume resistivity of the order of 10 ⁻⁴ Ω · m (10 ⁻² Ω · cm) or less. The fine particles as a semiconductor refer to fine particles made of a material having a volume resistivity on the order of 10 ⁻⁴ Ω · m (10 ⁻² Ω · cm) to 10 ¹² Ω · m (10 ¹⁴ Ω · cm). .

  In the fine particle layer structure of the present invention including the form and configuration described above, the fine particles on the substrate are regularly arranged two-dimensionally and in a packed state in a plane substantially parallel to the surface of the substrate. Thus, the fine particle layer can be formed, and the fine particles are preferably arranged in a close packed state. Here, in the semiconductor device of the present invention, “fine particles are arranged in a packed state” means more specifically that a conductive path composed of organic semiconductor molecules bonded to the fine particles is at least between the source / drain electrodes, for example. The state in which fine particles are arranged to such an extent that they are formed. Needless to say, the fine particle layer may have some depletion and defects. In the fine particle layer structure of the present invention, “the fine particles are arranged in a close packed state” means that when the fine particles are regarded as a rigid body, the two-dimensional plane or three-dimensional space is physically It means a state of regular arrangement at the maximum density that can be occupied. However, here, since the organic semiconductor molecules always exist between the fine particles, the fine particles are not in contact with each other. The distance between the surfaces of adjacent fine particles is equal to or less than the length of the organic semiconductor molecule used in the major axis direction. In addition, when the fine particles are regularly arranged two-dimensionally in a plane substantially parallel to the surface of the substrate on the substrate, more specifically, such a two-dimensionally regularly arranged layer has a single layer. Even if it is a layer, it may exist in multiple layers in a three-dimensional close-packed state. “Two-dimensionally regularly arranged” means that fine particles having a uniform particle diameter are arranged in a packed space, preferably in a close packed state, in a space of at least approximately one layer of fine particles. Means that Note that “in a plane substantially parallel to the surface of the substrate” means that when there are minute irregularities on the surface of the substrate by the manufacturing method of the substrate, the surface is substantially parallel to the minute irregularities.

  In the fine particle layer structure of the present invention, the fine particle layer separated by the separation region is formed, for example, after a thin film made of a solution containing fine particles is formed on the substrate and the separation region based on a coating method such as a dipping method or a casting method. It can be obtained by evaporating the solvent contained in the thin film, whereby the fine particles can be arranged in a close packed manner in the fine particle layer. In this case, when evaporating the solvent contained in the thin film, it is desirable to evaporate the solvent contained in the thin film while controlling the evaporation rate. Alternatively, in the fine particle layer structure or the like of the present invention, the separated fine particle layer is formed by forming a thin film from a solution containing fine particles based on a method similar to the LB (Langmuir-Blodgett) method, for example. It can also be obtained by transferring the thin film onto the substrate and the separation region, and this can also arrange the fine particles in the fine particle layer by close packing. More specifically, after forming a thin film on the water surface based on a solution containing fine particles, the fine particle film formed by evaporating the solvent contained in the thin film is transferred onto the substrate and the separation region to form the fine particle layer. In this case as well, in the step of evaporating the solvent contained in the thin film, it is more preferable to evaporate the solvent contained in the thin film while controlling the evaporation rate.

  In the semiconductor device of the present invention, after the formation of the fine particle layer, the step of bringing the organic semiconductor molecules into contact with the separation region is performed at least once, whereby the fine particles and the organic semiconductor molecules can be combined. A single layer of the conjugate can be formed by performing the formation of the fine particle layer and the contact with the organic semiconductor molecule once, or by repeating the formation of the fine particle layer and the contact with the organic semiconductor molecule twice or more. A laminated structure of a combined body can be formed.

  Alternatively, in the fine particle layer structure or the like of the present invention, the fine particle layer separated by the separation region is mixed with a solution containing fine particles composed of a conductor or a semiconductor and an organic semiconductor molecule, whereby the fine particle and the organic semiconductor molecule are mixed. After obtaining clusters formed by bonding (reaction), a thin film containing these clusters can be formed on the substrate and the separation region and dried. The method of mixing the solution containing the fine particles with the organic semiconductor molecules may be appropriately determined based on the solution containing the fine particles to be used and the organic semiconductor molecules to be used. Depending on the solution containing fine particles and the organic semiconductor molecules to be used, it is possible to obtain a cluster consisting of fine particles and organic semiconductor molecules bonded by simply adding the powdered organic semiconductor molecules to the solution containing the fine particles and mixing them lightly. Sometimes you can. Examples of a method for forming a thin film including clusters include a coating method such as a dipping method and a casting method, and an LB method. The cluster arrangement state includes a state where the clusters are arranged one-dimensionally (a state where they are arranged linearly), a state where the clusters are arranged two-dimensionally (a state where they are arranged in a plane), and a state where the clusters are 3 It may be in any of a dimensionally arranged state (a three-dimensionally arranged state), for example, depending on the application state of a solution containing clusters.

  Here, the cluster formed by bonding fine particles and organic semiconductor molecules is more specifically a combination of fine particles and fine particles, for example, three-dimensionally via organic semiconductor molecules. In this case, several thousand to several millions are gathered together via organic semiconductor molecules, and the size is on the order of 0.1 μm to 1 μm. When a cluster is arranged between source / drain electrodes, on a gate insulating layer, or on a substrate, an organic semiconductor exists on the surface of the cluster between the clusters or between the clusters and the source / drain electrodes. Depending on the molecule or, in some cases, in addition thereto, the organic semiconductor molecule solution in which the organic semiconductor molecule is dissolved is applied to the cluster and dried to be bonded to each other. In the cluster, there are a large number of “fine particle-organic semiconductor molecule” conduction paths. If a cubic cluster of 100 nm square is assumed and fine particles with a particle size of 5 nm are stacked in a cubic lattice, 8,000 fine particles are present in the cubic cluster. A large number of organic semiconductor molecules are bonded and crosslinked between these fine particles. Therefore, the number of conduction paths is remarkably increased, resulting in an increase in the amount of current.

  Examples of the solvent contained in the thin film include nonpolar or low polarity organic solvents such as toluene, chloroform, hexane, and ethanol.

The surface of the fine particles before bonding with the organic semiconductor molecules is preferably covered with a protective film made of chain-like insulating organic molecules from the viewpoint of preventing aggregation of the fine particles. Although the molecules constituting the protective film are bonded to the fine particles, the magnitude of the binding force greatly affects the final particle size distribution of the aggregate when the fine particles covered with the protective film are produced. . It is preferable that one end of the insulating organic molecule constituting the protective film has a functional group that chemically reacts (bonds) with the fine particles. For example, mention may be made of a thiol group (-SH) as a functional group, alkanethiol [e.g., dodecanethiol (C ₁₂ H ₂₅ SH)] as one of the molecules with the thiol group at the end can be exemplified. It is thought that when the thiol group of dodecanethiol is bonded to fine particles such as gold, the hydrogen atom is released to become C ₁₂ H ₂₅ S—Au. Alternatively, as an insulating organic molecule constituting the protective film, an alkylamine molecule [for example, dodecylamine (C ₁₂ H ₂₅ NH ₂ )] can be exemplified. When the fine particles are brought into contact with the organic semiconductor molecules, the organic semiconductor molecules are replaced with the organic molecules constituting the protective film, and as a result, a chemical conjugate of the fine particles and the organic semiconductor molecules is formed.

  One kind of organic semiconductor molecule that plays a role of crosslinking between fine particles has functional groups capable of binding to the fine particles at both ends. By the way, when the distance between the fine particles is longer than the total length of the organic semiconductor molecules, and the fine particles are fixed on the substrate and cannot move, the conductive path is cut there. As a result, the organic semiconductor The number of conductive paths constituted by molecules and fine particles is reduced, leading to deterioration of the characteristics of the semiconductor device. When an attempt is made to obtain a semiconductor device having excellent characteristics, when this semiconductor device is composed of, for example, a field effect transistor (FET), there is no break from one source / drain electrode to the other source / drain electrode. The conductive path needs to be connected. In addition, the number of conductive paths greatly affects the improvement of FET characteristics. In order to increase the number of conductive paths, it is desirable that the fine particles are adjacent to each other at a distance closer than the length of the organic semiconductor molecule, and further, the fine particles are two-dimensionally arranged in a hexagonal close packed manner. More specifically, the surface of the fine particle before being bonded to the organic semiconductor molecule is covered with a protective film made of, for example, a chain-like insulating organic molecule. Therefore, the distance between the fine particles is about twice as long as the length of the molecules constituting the protective film (actually, the distance between the particles is slightly shorter because the molecules slightly overlap at the tip). It is preferable that the length of the organic semiconductor molecule that crosslinks these fine particles is not longer than the distance between the fine particles thus determined.

In the semiconductor device of the present invention, the organic semiconductor molecule is an organic semiconductor molecule having a conjugated bond, and at both ends of the molecule, a thiol group (—SH), an amino group (—NH ₂ ), an isocyano group (—NC), It preferably has a cyano group (—CN), a thioacetyl group (—SCOCH ₃ ), or a carboxy group (—COOH). A thiol group, an amino group, an isocyano group, a cyano group, and a thioacetyl group are functional groups that bind to fine particles as a conductor such as Au, and a carboxy group is a functional group that binds to fine particles as a semiconductor. Further, the functional groups located at both ends of the molecule may be different, and it is more preferable that the functional groups at both ends are close to the fine particles. The organic semiconductor molecule is a π-conjugated molecule, and most preferably has a functional group that is chemically bonded to the fine particles in at least two places.

  Specifically, as the organic semiconductor molecule, for example, 4,4′-biphenyldithiol (BPDT) of the structural formula (1), 4,4′-diisocyanobiphenyl of the structural formula (2), structural formula (3) 4,4'-diisocyano-p-terphenyl, and 2,5-bis (5'-thioacetyl-2'-thiophenyl) thiophene of structural formula (4), 4,4'-di of structural formula (5) Isocyanophenyl, benzidine (biphenyl-4,4′-diamine) of structural formula (6), TCNQ (tetracyanoquinodimethane) of structural formula (7), biphenyl-4,4′- of structural formula (8) Dicarboxylic acid, 1,4-di (4-thiophenylacetylinyl) -2-ethylbenzene of structural formula (9), 1,4-di (4-isocyanophenylacetylinyl)-of structural formula (10) 2-ethylbenzene or yes It can be exemplified Bovine Serum Albumin, Horse Radish Peroxidase, the Antibody-Antigen.

Structural formula (1): 4,4′-biphenyldithiol

Structural formula (2): 4,4′-diisocyanobiphenyl

Structural formula (3): 4,4′-diisocyano-p-terphenyl

Structural formula (4): 2,5-bis (5′-thioacetyl-2′-thiophenyl) thiophene

Structural formula (5): 4,4′-diisocyanophenyl

Structural formula (6): benzidine (biphenyl-4,4′-diamine)

Structural formula (7): TCNQ (tetracyanoquinodimethane)

Structural formula (8): Biphenyl-4,4′-dicarboxylic acid

Structural formula (9): 1,4-di (4-thiophenylacetylinyl) -2-ethylbenzene

Structural formula (10): 1,4-di (4-isocyanophenylacetylinyl) -2-ethylbenzene

  A dendrimer represented by the structural formula (11) can also be used as the organic semiconductor molecule.

Structural formula (11): Dendrimer

Alternatively, an organic molecule represented by the structural formula (12) can also be used as the organic semiconductor molecule. “X” in the structural formula (12) is represented by any one of the formula (13-1), the formula (13-2), the formula (13-3), and the formula (13-4). “Y ₁ ” and “Y ₂ ” in (12) are represented by any one of formulas (14-1) to (14-9), and “Z ₁ ”, “Z ₂ ”, “Z ₃ ”. , “Z ₄ ” is represented by any one of formula (15-1) to formula (15-11). Here, the value of “n” is 0 or a positive integer. X is a unit in which a unit represented by any one of formula (13-1), formula (13-2), formula (13-3), and formula (13-4) is repeatedly bonded one or more times. Yes, including repetition by different units. Further, the side chains Z ₁ , Z ₂ , Z ₃ , Z ₄ may change to different ones during the repetition.

When the active element in the semiconductor device of the present invention is composed of a bottom gate / bottom contact field effect transistor (FET), the bottom gate / bottom contact field effect transistor is
(A) a gate electrode formed on a support;
(B) a gate insulating layer (corresponding to a substrate) formed on the gate electrode;
(C) source / drain electrodes formed on the gate insulating layer, and
(D) a channel formation region formed between the source / drain electrodes and on the gate insulating layer and configured by a conductive path;
It has.

Alternatively, when the active element in the semiconductor device of the present invention is configured from a bottom gate / top contact field effect transistor (FET), the bottom gate / top contact field effect transistor is:
(A) a gate electrode formed on a support;
(B) a gate insulating layer (corresponding to a substrate) formed on the gate electrode;
(C) a channel formation region forming layer including a channel formation region formed on the gate insulating layer and configured by a conductive path; and
(D) Source / drain electrodes formed on the channel forming region constituting layer,
It has.

Alternatively, when the active element in the semiconductor device of the present invention is configured from a top gate / bottom contact type field effect transistor (FET), the top gate / bottom contact type field effect transistor is:
(A) Source / drain electrodes formed on the substrate,
(B) a channel forming region formed on the substrate between the source / drain electrodes and constituted by a conductive path;
(C) a gate insulating layer formed on the source / drain electrode and the channel formation region, and
(D) a gate electrode formed on the gate insulating layer;
It has.

Alternatively, when the active element in the semiconductor device of the present invention is configured from a top gate / top contact field effect transistor (FET), the top gate / top contact field effect transistor is:
(A) a channel forming region constituting layer including a channel forming region formed on a substrate and configured by a conductive path;
(B) a source / drain electrode formed on the channel forming region constituting layer;
(C) a gate insulating layer formed on the source / drain electrode and the channel formation region, and
(D) a gate electrode formed on the gate insulating layer;
It has.

In the first aspect of the present invention or the second aspect of the present invention, the substrate is made of a silicon oxide-based material (for example, SiO _x or spin-on glass (SOG)); silicon nitride (SiN _Y ); aluminum oxide (Al ₂ O). ₃ ); It can be composed of a metal oxide high dielectric insulating film. When the base is composed of these materials, the base may be formed on a support appropriately selected from the following materials (or above the support). That is, as a support or as a substrate other than the above-described substrates, polymethyl methacrylate (polymethyl methacrylate, PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyethersulfone (PES), polyimide, Examples include organic polymers exemplified by polycarbonate and polyethylene terephthalate (PET) (having the form of polymer materials such as flexible plastic films, plastic sheets, and plastic substrates made of polymer materials). Or, alternatively, mica. If a substrate made of such a polymer material having flexibility is used, for example, a semiconductor device can be incorporated or integrated into a display device or electronic device having a curved shape. Alternatively, as a substrate (or support), various glass substrates, various glass substrates having an insulating layer formed on the surface, a quartz substrate, a quartz substrate having an insulating layer formed on the surface, and an insulating layer formed on the surface A silicon substrate can be mentioned. As the electrically insulating support, an appropriate material may be selected from the materials described above. Other examples of the support include a conductive substrate (a substrate made of a metal such as gold or highly oriented graphite). In addition, depending on the configuration and structure of the semiconductor device, the semiconductor device is provided on a support, but this support can also be made of the above-described materials.

  When a field effect transistor (FET) is used as an active element in a semiconductor device, platinum (Pt), gold (Au), palladium (Pd), chromium is used as a material for forming gate electrodes, source / drain electrodes, and various wirings. (Cr), nickel (Ni), aluminum (Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), etc. Metals or alloys containing these metal elements, conductive particles made of these metals, conductive particles of alloys containing these metals, conductive materials such as polysilicon containing impurities, A layered structure of layers containing these elements can also be used. Furthermore, an organic material (conductive polymer) such as poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS] is used as a material constituting the gate electrode, the source / drain electrode, and various wirings. It can also be mentioned. The material constituting the gate electrode, source / drain electrode, and various wirings may be the same material as the fine particles, or may be a different material.

  Various chemical vapor deposition methods (CVD methods) including physical vapor deposition (PVD method) and MOCVD methods, depending on the materials constituting the gate electrodes, source / drain electrodes, and wiring. ); Spin coating method; various printing methods such as screen printing method, inkjet printing method, offset printing method, gravure printing method; air doctor coater method, blade coater method, rod coater method, knife coater method, squeeze coater method, reverse roll coater Various coating methods such as stamping method, lift-off method, shadow mask method; Electrolytic plating and electroless methods · The method or plating method such as those combinations; and can include any of a spraying method, a combination of a patterning technique as necessary. In addition, as the PVD method, (a) various vacuum deposition methods such as electron beam heating method, resistance heating method, flash deposition, (b) plasma deposition method, (c) bipolar sputtering method, direct current sputtering method, direct current magnetron sputtering method Various sputtering methods such as high-frequency sputtering method, magnetron sputtering method, ion beam sputtering method, bias sputtering method, (d) DC (direct current) method, RF method, multi-cathode method, activation reaction method, electric field evaporation method, high-frequency method Various ion plating methods such as an ion plating method and a reactive ion plating method can be given.

Furthermore, when an active element in a semiconductor device is a field effect transistor (FET), a silicon oxide-based material, silicon nitride (SiN _Y ), metal as a material constituting a gate insulating layer (which may correspond to a base) Examples include organic insulating materials exemplified by polymethyl methacrylate (PMMA), polyvinyl phenol (PVP), and polyvinyl alcohol (PVA) as well as inorganic insulating materials exemplified by oxide high dielectric insulating films. It is possible to use a combination of these. Silicon oxide-based materials include silicon oxide (SiO _x ), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin-on-glass), low dielectric constant SiO ₂ -based material (for example, polyaryl) And ether, cycloperfluorocarbon polymer and benzocyclobutene, cyclic fluororesin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon, and organic SOG).

In addition, as a method for forming a lower layer and an upper layer constituting the separation region, or a single layer structure constituting the separation region, and a gate insulating layer, various PVD methods described above; various CVD methods; spin coating methods; various printing methods described above; Any of the above-described various coating methods; immersion methods; casting methods; and spray methods can be used. Alternatively, the gate insulating layer can be formed by oxidizing or nitriding the surface of the gate electrode, or can be obtained by forming an oxide film or a nitride film on the surface of the gate electrode. As a method for oxidizing the surface of the gate electrode, although depending on the material constituting the gate electrode, an oxidation method using O ₂ plasma and an anodic oxidation method can be exemplified. Further, as a method of nitriding the surface of the gate electrode, although it depends on the material constituting the gate electrode, a nitriding method using N ₂ plasma can be exemplified. Alternatively, for example, for an Au electrode, it is immersed by an insulating molecule having a functional group that can form a chemical bond with the gate electrode, such as a linear hydrocarbon modified at one end with a mercapto group. A gate insulating layer can also be formed on the surface of the gate electrode by covering the surface of the gate electrode in a self-organized manner by a method such as a method.

  When the semiconductor device of the present invention is applied to and used in a display device or various electronic devices, it may be a monolithic integrated circuit in which a large number of semiconductor devices are integrated on a support, or each semiconductor device is cut and individualized, and discrete It may be used as a part. Further, the semiconductor device may be sealed with resin.

  In the first aspect of the present invention, the separation region formed on the substrate has a wall-like two-layer structure, and the lower side wall has an undercut shape. In the second aspect of the present invention, the separation region formed on the substrate has a wall-shaped single layer structure, and the side wall has an undercut shape (specifically, for example, the lower part of the side wall is It is undercut with respect to the upper part of the side wall). The form of the upper side wall in the first aspect of the present invention and the form of the upper part of the side wall in the second aspect of the present invention may be any form, and the point is that in the first aspect of the present invention. The lower side wall and the lower part of the side wall in the second aspect of the present invention may be at least partially undercut (reversely tapered) with respect to the substrate. That is, for example, it is only necessary that the lower side wall upper end protrudes from the portion where the lower side wall rises from the base. And since it has such a structure and state, when the fine particle layer is formed on the separation region and the portion of the substrate surrounded by the separation region, the fine particle layer is surely formed on the side wall of the separation region. In addition, as a result of so-called “step breaks”, the fine particle layer can be reliably separated (isolated). In addition, since the wall-shaped separation region is not removed, the fine particle layer is not contaminated, damaged, or disordered. Therefore, for example, there is no deterioration in the characteristics of the active element in the obtained semiconductor device. Further, since the fine particle layer can be reliably separated, for example, a leakage current between the gate electrode and the fine particle layer in the semiconductor device can be reduced. Furthermore, in the semiconductor device of the present invention, as a result of bonding the fine particles and the organic semiconductor molecules, charge transfer in the conductive path is dominantly generated in the axial direction of the molecules along the main chain of the organic semiconductor molecules. Since the structure has a structure and the mobility in the axial direction of the molecule, for example, the high mobility due to delocalized π electrons can be utilized to the maximum, it is possible to realize high mobility. In addition, a high-temperature process or a vacuum process is not necessary for forming a channel formation region or the like, a conductive path having a desired thickness can be easily formed, and a semiconductor device can be manufactured at low cost.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

  Example 1 relates to a fine particle layer structure according to a first aspect of the present invention, a method for forming the same, a semiconductor device, and an isolation region. FIG. 1A shows a schematic partial end view of the fine particle layer structure, the semiconductor device, and the separation region of Example 1, and FIGS. 2A and 2B show conceptual diagrams of the conductive path 21 and the like. Shown in

The fine particle layer structure of Example 1 is
(A) A separation region 30 formed on the substrate 11 and having a wall-like (projection-like) two-layer structure in which the side wall of the lower layer 31 is undercut (specifically, the side wall of the upper layer 32 is the lower layer) Separation region 30) protruding from the side wall of 31, and
(B) the fine particle layer 20 formed on the portion of the substrate 11 surrounded by the separation region 30;
Consists of. And this fine particle layer 20 is isolate | separated in the side wall of the isolation | separation area | region 30 which is a protrusion part. In addition, the planar shape of the part of the base | substrate 11 enclosed by the isolation | separation area | region 30 is substantially rectangular, for example. The same applies to the following.

The semiconductor device of Example 1 is
(A) A separation region 30 formed on the substrate 11 and having a wall-like (projection-like) two-layer structure in which the side wall of the lower layer 31 is undercut (specifically, the side wall of the upper layer 32 is the lower layer) Separation region 30) protruding from the side wall of 31, and
(B) an active element formed on the portion of the substrate 11 surrounded by the isolation region 30;
Consists of. The active element includes fine particles 22 made of a conductor or a semiconductor (in the first embodiment, a conductor) and conductive paths 21 made of organic semiconductor molecules 23 bonded to the fine particles 22. Further, the fine particle layer 20 composed of the fine particles 22 is separated on the side wall of the separation region 30. In other words, the isolation region 30 as the protrusion corresponds to a so-called element isolation region in a normal semiconductor device.

  Further, the separation region 30 of the first embodiment serving as the protrusion has a wall-like (projection-like) two-layer structure formed on the base 11, and the wall surface of the lower layer 31 is undercut. Specifically, the wall surface of the upper layer 32 protrudes from the wall surface of the lower layer 31 or is in a state of protruding from the wall surface of the lower layer 31.

  Here, the active element in the semiconductor device of Example 1 is a field effect transistor (FET) having a gate electrode 12, a gate insulating layer 13 (corresponding to the base 11), a channel formation region 15, and a source / drain electrode 14. The channel formation region 15 is constituted by the conductive path 21. The fine particles 22 are arranged two-dimensionally regularly and in a filled state in a plane substantially parallel to the surface of the substrate 11 (gate insulating layer 13) to constitute the fine particle layer 20. Specifically, the active element in the semiconductor device of the first embodiment is a bottom gate / bottom contact type FET (more specifically, a TFT), and the conductivity of the conductive path 21 by an electric field applied to the conductive path 21. Is controlled. A conceptual diagram of charge transfer is shown by arrows in FIGS.

More specifically, the active element in the semiconductor device of Example 1 is shown in a schematic partial end view in FIG.
(A) a gate electrode 12 formed on the support 10;
(B) a gate insulating layer 13 (corresponding to the substrate 11) formed on the support 10 and the gate electrode 12;
(C) a source / drain electrode 14 formed on the gate insulating layer 13, and
(D) a channel forming region 15 formed between the source / drain electrodes 14 and on the gate insulating layer 13 and configured by the conductive path 21;
It is composed of

In Example 1, gold fine particles (gold nanoparticles) having an average particle size R _AVE = 5 nm are used as the fine particles 22 made of a conductor, and the organic semiconductor molecules 23 are organic semiconductor molecules having a conjugated bond. 4,4′-biphenyldithiol (BPDT) having thiol groups (—SH) at both ends thereof is used. The support 10 is composed of a glass substrate 10A and an insulating layer 10B made of SiO ₂ formed on the surface thereof, and the base 11 is made of a gate insulating layer 13 (specifically SiO ₂ ). A silicon semiconductor substrate can also be used as the substrate 10A.

  Hereinafter, see FIGS. 3A to 3C, FIGS. 4A and 4B, and FIGS. 5A and 5B which are schematic partial end views of the substrate and the like. The outline of the method for forming the fine particle layer structure of Example 1 and the method for manufacturing the semiconductor device will be described. 4A and 4B and FIGS. 5A and 5B are a region corresponding to the separation region and a region of a part of two parts of the substrate surrounded by the separation region. Is shown.

[Step-100]
First, the gate electrode 12 is formed on the support 10. Specifically, a resist layer (not shown) from which a portion for forming the gate electrode 12 is removed is formed on the insulating layer 10B made of SiO ₂ formed on the surface of the glass substrate 10A based on the lithography technique. To do. Thereafter, a titanium (Ti) layer (not shown) as an adhesion layer and a gold (Au) layer as a gate electrode 12 are sequentially formed on the entire surface by vacuum deposition, and then the resist layer is removed. To do. Thus, the gate electrode 12 can be obtained based on the so-called lift-off method (see FIG. 3A).

[Step-110]
Next, the gate insulating layer 13 corresponding to the base 11 is formed on the support 10 including the gate electrode 12 (more specifically, the insulating layer 10B formed on the surface of the glass substrate 10A) (FIG. 3). (See (B)). Specifically, the gate insulating layer 13 made of SiO ₂ is formed on the gate electrode 12 and the insulating layer 10B based on the sputtering method. The gate insulating layer 13 may be formed, and then the gate insulating layer 13 may be patterned based on a photolithography process. When the gate insulating layer 13 is formed, a part of the gate electrode 12 is hardened. By covering with a mask, an extraction portion (not shown) of the gate electrode 12 may be formed without a photolithography process.

[Step-120]
Thereafter, a source / drain electrode 14 made of a gold (Au) layer is formed on the gate insulating layer 13 (see FIG. 3C). Specifically, a titanium (Ti) layer (not shown) having a thickness of about 0.5 nm as the adhesion layer and a gold (Au) layer having a thickness of about 25 nm as the source / drain electrodes 14 are sequentially vacuumed. It forms based on a vapor deposition method. When these layers are formed, the source / drain electrode 14 can be formed without a photolithography process by covering a part of the gate insulating layer 13 with a hard mask. Alternatively, the source / drain electrode 14 may be formed by sequentially forming an adhesion layer and a gold (Au) layer based on a vacuum deposition method and then patterning based on a photolithography process.

[Step-130]
Thereafter, a resist layer 41 having an opening 42 is formed on the substrate 11 (gate insulating layer 13). Specifically, a resist layer 41 made of a negative resist material and having a thickness of 1.7 μm is applied on the gate insulating layer 13 corresponding to the substrate 11 by spin coating, and then baked. Next, based on the photolithography technique, the resist layer 41 is exposed and developed so that the portion of the substrate 11 where the isolation region 30 is to be formed is exposed and the portion of the substrate 11 where the active element is to be formed is covered. Thus, the structure shown in FIG. 4A can be obtained.

[Step-140]
Next, the lower layer 31 and the upper layer 32 constituting the separation region 30 are sequentially formed on the resist layer 41 and the portion of the base 11 exposed in the opening 42 by a sputtering method. In the first embodiment, the lower layer 31 is made of SiO _{X having a} thickness of 0.7 μm, and the upper layer 32 is made of SiN _{Y having a} thickness of 0.1 μm. The height H of the separation region 30 is 0.8 μm. In this way, the structure shown in FIG. 4B can be obtained.

[Step-150]
Thereafter, the side wall of the lower layer 31 is undercut (specifically, the side wall of the upper layer 32 protrudes from or protrudes from the side wall of the lower layer 31, or The side wall of the lower layer 31 is etched (see FIG. 5A) so that the upper end of the side wall of the lower layer 31 protrudes from the portion where the side wall rises from the base 11. Specifically, the lower layer 31 made of SiO _x is selectively isotropic using a mixed acid based on hydrofluoric acid (made of ammonium hydrogen fluoride NH ₄ F · HF and ammonium fluoride NH ₄ F). Etch into. Since the upper layer 32 made of SiN _Y is formed on the top surface of the lower layer 31, only the side wall of the lower layer 31 (and a part of the substrate 11) is etched.

[Step-160]
Next, the resist layer 41 is removed using an organic solvent, and the separation region 30 is left on the substrate 11, whereby the separation region 30 can be completed (see FIG. 5B). Note that the length L of one side of the wall-shaped isolation region 30 [the length (width) of the isolation region 30 lying between the portion of the base 11 where the active element is to be formed and the portion of the base 11 where the active element is to be formed. ] Was set to 100 μm.

[Step-170]
Thereafter, the fine particle layer 20 separated on the side wall of the separation region 30 is formed on the portion of the substrate 11 surrounded by the separation region 30.

[Step-180]
Next, a channel formation region constituting layer 15 </ b> A including the channel formation region 15 is formed based on the fine particle layer 20.

[Step-190]
Finally, by forming a passivation film (not shown) on the entire surface, the bottom gate / bottom contact type FET (specifically, TFT) shown in FIG. 1A can be obtained.

Isolation is realized by physically cutting the particulate layer 20 by the characteristic undercut structure (reverse taper structure) of the separation region 30. From the experiments so far, it is known that the fine particle layer 20 is not cut at the end of the source / drain electrode 14 when the thickness of the source / drain electrode 14 is about five times the average particle diameter of the fine particles 22. . In Example 1, since the relationship between the height H of the separation region 30 and the average particle size R _AVE of the fine particles 22 is (H / R _AVE ) = (800/5), the fine particle layer 20 is separated. In region 30, it is surely physically cut.

  Here, in [Step-170], the self-organization phenomenon caused by the fine particles 22 is actively used to achieve the two-dimensional regular arrangement. Specifically, the fine particle layer 20 is based on a solution containing fine particles 22 (for example, a fine particle colloid solution), and for example, a gold nanoparticle having a hydrophobic surface on a hydrophilic solvent (for example, water) is two-dimensionally formed as a single layer. Floating so as to have a regular arrangement, or conversely, floating a gold nanoparticle having a hydrophilic surface on a hydrophobic solvent so as to have a two-dimensional regular arrangement in a single layer, as in the LB method The image is transferred onto the substrate 11 and the separation region 30. However, the method for forming the fine particle layer 20 is not limited to such a method, and for example, the fine particle layer 20 can be formed based on a casting method.

Then, in [Step-180], the functional group which the organic semiconductor molecule 23 has at the terminal is chemically bonded to the fine particles 22. More specifically, the functional group which the organic semiconductor molecule 23 has at both ends (in Example 1, it is an organic semiconductor molecule having a conjugated bond, which is a thiol group having both ends of 4,4′-biphenyldithiol (BPDT). The organic semiconductor molecules 23 and the fine particles 22 are chemically (alternatively) bonded to each other by [—SH]), whereby the network-like conductive path 21 is constructed. Here, the conductive path 21 is constituted by a single layer of a conjugate of the fine particles 22 and the organic semiconductor molecules 23, or the conductive path 21 is constituted by a laminated structure of the conjugate of the fine particles 22 and the organic semiconductor molecules 23. Yes. That is, by arranging the fine particles 22 regularly two-dimensionally in a plane substantially parallel to the surface of the substrate in a packed state, and then bringing the organic semiconductor molecules 23 into contact with each other once, A single layer of a conjugate of the fine particles 22 and the organic semiconductor molecules 23 can be formed, and a layer composed of a conjugate of the fine particles 22 and the organic semiconductor molecules 23 is laminated by performing two or more times. A structure can be obtained. Alternatively, the step of forming the fine particle layer 20 is repeated a plurality of times to arrange the fine particles 22 regularly in a three-dimensional manner and in a filled state, and then contact the organic semiconductor molecules 23 at least. By performing the process once, it is possible to obtain a stacked structure of a combined body in which layers composed of a combined body of the fine particles 22 and the organic semiconductor molecules 23 are stacked. Incidentally, when the fine particle layer 20 and the organic semiconductor molecule 23 are brought into contact with each other, a solution of the organic semiconductor molecule is used, and this solution contains ethanol as a solvent. Since the separation region 30 is composed of SiO _x and SiN _y , the separation region 30 is not dissolved by the solvent upon contact between the fine particle layer 20 and the organic semiconductor molecule 23, and therefore the fine particle layer 20 is formed. The occurrence of adverse effects on the conductive path 21 can be reliably avoided.

  Thus, since the channel formation region 15 can be formed by forming the fine particle layer 20 one by one, the channel formation region 15 having a desired thickness can be formed by repeating this process. it can. The channel formation region 15 obtained in this way is composed of a combined body in which the fine particles 22 and the organic semiconductor molecules 23 are bonded in a network shape, and carrier movement is controlled by the gate voltage applied to the gate electrode 12. Specifically, for example, when the gate voltage applied to the gate electrode 12 is 0 volt, a source / drain current flows between the source / drain electrodes 14. Furthermore, the source / drain current flowing between the source / drain electrodes 14 can be controlled by controlling the direction (plus or minus) and the value of the gate voltage applied to the gate electrode 12. The same applies to the semiconductor devices obtained in Examples 2 to 4 below. In forming the fine particle layer 20 one by one, the fine particle layer 20 is reliably separated on the side wall of the separation region 30.

  In the channel forming region 15, the fine particles 22 are two-dimensionally or three-dimensionally connected by the organic semiconductor molecules 23, and a conductive path in the fine particles 22 and a conductive path along the molecular skeleton in the organic semiconductor molecules 23 are formed. A connected network-like conductive path 21 is formed. Then, as shown in the conceptual diagram of FIG. 2B, the conductive path 21 does not include intermolecular electron transfer that is a cause of low mobility in a channel formation region made of a conventional organic semiconductor, In addition, since the electron movement in the molecule is performed through a conjugated system formed along the molecular skeleton, high mobility is expected. Electron conduction in the channel formation region 15 is performed through a network-like conductive path 21 as indicated by an arrow in FIG. 2A, and the conductivity of the channel formation region 15 is applied to the gate electrode 12. Controlled by voltage.

Alternatively, in [Step-180], 200 milligrams of powdery BPDT is added to 10 milliliters of a toluene solution obtained by diluting a toluene solution stock solution containing 30% by weight of gold fine particles (gold nanoparticles) 200 times with toluene, By mixing, gold microparticles and BPDT react in a short time to form a three-dimensional networked cluster consisting of microparticles and organic semiconductor molecules bonded together, and as a precipitate at the bottom of the solution Precipitate. That is, the functional group that the organic semiconductor molecule 23 has at the terminal (the organic semiconductor molecule having a conjugated bond, and the thiol group [—SH] at both ends of 4,4′-biphenyldithiol (BPDT)) is chemically bonded to the fine particles 22. More specifically, the organic semiconductor molecules 23 and the fine particles 22 are chemically (alternately) bonded to each other by the functional groups (thiol groups) of the organic semiconductor molecules 23 at both ends. Organic semiconductor molecules 23 are combined in a three-dimensional network to form a cluster. And the cluster obtained in this way is apply | coated to the whole surface, and is naturally dried. Also by this, the fine particle layer 20 formed on the portion of the substrate 11 surrounded by the separation region 30 and separated on the side wall of the separation region 30 can be obtained. Since the separation region 30 is composed of SiO _x and SiN _y , the separation region 30 is not dissolved by toluene when the fine particle layer 20 and the organic semiconductor molecule 23 are in contact with each other. Generation of adverse effects on the conductive path 21 can be reliably avoided.

Instead of the semiconductor device having the structure shown in FIG. 1A, the following semiconductor substrate was prototyped as a prototype of Example 1. That is, a silicon semiconductor substrate doped with impurities at a high concentration is used as the support 10, the formation of the gate electrode 12 is omitted, the silicon semiconductor substrate itself is used as the gate electrode, and the gate insulating layer 13 (substrate 11) was composed of SiO ₂ formed by thermally oxidizing the surface of the silicon semiconductor substrate. Then, by bringing probes into contact with the silicon semiconductor substrate and the source electrode, when a voltage is applied to V _g between the probes, the current flowing between the probe I _g - was measured (gate electrode leakage current I _g between the source electrode) . The measurement results are shown in FIG. 10, and the leakage current _Ig was 10 ⁻¹² amperes or less when a voltage of 1 volt was applied. On the other hand, a comparative semiconductor device in which the wall-shaped isolation region is about 10 times the area of the wall-shaped isolation region in the prototype of Example 1 was manufactured. This comparative semiconductor device has the same structure except that the area of the isolation region is very large compared to the active element in the prototype semiconductor device of Example 1, and this active element is very It is covered with a fine particle layer having a large area. In such a comparative semiconductor device, when the leakage current _Ig was measured in the same manner, it was 20 × 10 ⁻¹² amperes to 30 × 10 ⁻¹² amperes when a voltage of 1 volt was applied.

The second embodiment is a modification of the first embodiment. The active element in the semiconductor device of Example 2 whose schematic partial end view is shown in FIG. 1B is a bottom gate / top contact type FET (specifically, TFT). That is, this active element is
(A) a gate electrode 12 formed on the support 10;
(B) a gate insulating layer 13 (corresponding to the substrate 11) formed on the gate electrode 12,
(C) a channel formation region constituting layer 15A including the channel formation region 15 formed on the gate insulating layer 13 and constituted by the conductive path 21, and
(D) source / drain electrodes 14 formed on the channel formation region constituting layer 15A;
It has.

  The outline of the method for manufacturing the semiconductor device of Example 2 will be described below.

[Step-200]
First, after forming the gate electrode 12 on the support 10 in the same manner as [Step-100] in Example 1, the support including the gate electrode 12 in the same manner as [Step-110] in Example 1. A gate insulating layer 13 corresponding to the base 11 is formed on (more specifically, the insulating layer 10B).

[Step-210]
Next, steps similar to [Step-130] to [Step-160] in Example 1 are performed to complete the separation region 30 on the substrate 11, and then [Step-170] in Example 1. The fine particle layer 20 separated on the side wall of the separation region 30 is formed on the portion of the substrate 11 surrounded by the separation region 30 by performing the same process as in Step 1. -180], the channel formation region constituting layer 15A including the channel formation region 15 is formed based on the fine particle layer 20.

[Step-220]
Thereafter, the source / drain electrodes 14 are formed on the channel formation region constituting layer 15A so as to sandwich the channel formation region 15. Specifically, a gold (Au) layer as the source / drain electrode 14 is formed based on the vacuum deposition method in the same manner as in [Step-120] of Example 1. When forming this layer, the source / drain electrode 14 can be formed without a photolithography process by covering a part of the channel formation region constituting layer 15A with a hard mask. The source / drain electrode 14 may be formed by forming a gold (Au) layer based on a vacuum deposition method and then patterning based on a photolithography process.

[Step-230]
Finally, by forming a passivation film (not shown) on the entire surface, the semiconductor device of Example 2 shown in FIG. 1B can be completed.

The third embodiment is also a modification of the first embodiment. The active element in the semiconductor device of Example 2 whose schematic partial end view is shown in FIG. 6A is a top gate / bottom contact type FET (specifically, TFT). That is, this active element is
(A) source / drain electrodes 14 formed on the substrate 11;
(B) a channel forming region 15 formed on the substrate 11 between the source / drain electrodes 14 and configured by the conductive path 21;
(C) a gate insulating layer 13 formed on the source / drain electrode 14 and the channel formation region 15, and
(D) a gate electrode 12 formed on the gate insulating layer 13;
It has.

  The outline of the method for manufacturing the semiconductor device of Example 3 will be described below.

[Step-300]
First, a base 11 made of SiO ₂ is formed on the surface of a support 10 made of a glass substrate by, for example, a CVD method. Then, the source / drain electrode 14 is formed on the substrate 11 in the same manner as in [Step-120] of the first embodiment. Specifically, a titanium (Ti) layer (not shown) as an adhesion layer and a gold (Au) layer as a source / drain electrode 14 are sequentially formed based on a vacuum deposition method. When these layers are formed, the source / drain electrode 14 can be formed without a photolithography process by covering a part of the substrate 11 with a hard mask. Alternatively, the source / drain electrode 14 may be formed by sequentially forming an adhesion layer and a gold (Au) layer based on a vacuum deposition method and then patterning based on a photolithography process.

[Step-310]
Next, steps similar to [Step-130] to [Step-160] in Example 1 are performed to complete the separation region 30 on the substrate 11, and then [Step-170] in Example 1. The fine particle layer 20 separated on the side wall of the separation region 30 is formed on the portion of the substrate 11 surrounded by the separation region 30 by performing the same process as in Step 1. -180], the channel formation region constituting layer 15A including the channel formation region 15 is formed based on the fine particle layer 20.

[Step-320]
Thereafter, in the same manner as in [Step-110] in Example 1, the gate insulating layer 13 is formed on the entire surface, and then the gate electrode 12 is formed on the portion of the gate insulating layer 13 located on the channel formation region 15. To do. Specifically, a titanium (Ti) layer (not shown) as an adhesion layer and a gold (Au) layer as a gate electrode 12 are sequentially formed based on a vacuum deposition method. When these layers are formed, the gate electrode 12 can be formed without a photolithography process by covering a part of the gate insulating layer 13 with a hard mask. Note that the adhesion layer and the gold (Au) layer may be sequentially formed based on a vacuum deposition method, and then patterned based on a photolithography process to form the gate electrode 12.

[Step-330]
Finally, by forming a passivation film (not shown) on the entire surface, the semiconductor device of Example 3 shown in FIG. 6A can be completed.

The fourth embodiment is also a modification of the first embodiment. The active element in the semiconductor device of Example 2 whose schematic partial end view is shown in FIG. 6B is a top gate / top contact type FET (specifically, TFT). That is, this active element is
(A) a channel formation region constituting layer 15A including the channel formation region 15 formed on the base 11 and constituted by the conductive path 21;
(B) source / drain electrodes 14 formed on the channel formation region constituting layer 15A;
(C) a gate insulating layer 13 formed on the source / drain electrode 14 and the channel formation region 15, and
(D) a gate electrode 12 formed on the gate insulating layer 13;
It has.

  The outline of the method of manufacturing the semiconductor device of Example 4 will be described below.

[Step-400]
First, a base 11 made of SiO ₂ is formed on the surface of a support 10 made of a glass substrate by, for example, a CVD method. Then, by performing the same steps as [Step-130] to [Step-160] in Example 1, the separation region 30 is completed on the substrate 11, and then [Step-170] in Example 1 is set. By performing the same process, the fine particle layer 20 separated on the side wall of the separation region 30 is formed on the portion of the substrate 11 surrounded by the separation region 30, and further, [Step- 180], the channel formation region constituting layer 15A including the channel formation region 15 is formed based on the fine particle layer 20.

[Step-410]
Thereafter, the source / drain electrodes 14 are formed on the channel formation region constituting layer 15A in the same manner as in [Step-120] of the first embodiment. Specifically, a gold (Au) layer as the source / drain electrode 14 is formed based on a vacuum deposition method. When forming this layer, the source / drain electrode 14 can be formed without a photolithography process by covering a part of the channel formation region constituting layer 15A with a hard mask. The source / drain electrode 14 may be formed by forming a gold (Au) layer based on a vacuum deposition method and then patterning based on a photolithography process.

[Step-420]
Thereafter, in the same manner as in [Step-320] in Example 3, the gate insulating layer 13 is formed on the entire surface, and then the gate electrode 12 is formed on the portion of the gate insulating layer 13 located on the channel formation region 15. To do.

[Step-430]
Finally, by forming a passivation film (not shown) on the entire surface, the semiconductor device of Example 4 shown in FIG. 6B can be completed.

  Example 5 relates to the fine particle layer structure according to the second aspect of the present invention, a method for forming the same, a semiconductor device, and an isolation region. A schematic partial end view of the fine particle layer structure, the semiconductor device, and the separation region of Example 5 is shown in FIG. The conceptual diagram of the conductive path 21 and the like is as shown in FIGS.

The fine particle layer structure of Example 5 is
(A) A separation region 130 having a wall-like (projection-like) single-layer structure formed on the substrate 11 and having a side wall with an undercut shape; and
(B) the fine particle layer 20 formed on the portion of the substrate 11 surrounded by the separation region 130;
Consists of. And this fine particle layer 20 is isolate | separated in the side wall of the isolation | separation area | region 130 which is a protrusion part. In addition, the planar shape of the part of the base | substrate 11 enclosed by the isolation | separation area | region 130 is a substantially rectangular shape, for example. The same applies to the following.

The semiconductor device of Example 5 is
(A) A separation region 130 having a wall-like (projection-like) single-layer structure formed on the substrate 11 and having a side wall with an undercut shape; and
(B) an active element formed on the portion of the substrate 11 surrounded by the isolation region 130;
Consists of. The active element includes fine particles 22 made of a conductor or a semiconductor (a conductor in the fifth embodiment) and conductive paths 21 made of organic semiconductor molecules 23 bonded to the fine particles 22. Further, the fine particle layer 20 composed of the fine particles 22 is separated at the side wall of the separation region 130. That is, the isolation region 130 which is a protrusion corresponds to a so-called element isolation region in a normal semiconductor device.

  In addition, the separation region 130 of Example 5 serving as a protrusion has a wall-like (projection-like) single-layer structure formed on the base 11, and the side wall has an undercut shape. More specifically, in the separation region 130, the upper part of the side wall protrudes or protrudes from the lower part of the side wall, and the side wall is undercut with respect to the base 11. That is, the upper end of the side wall protrudes from the portion where the side wall rises from the base 11.

  Here, the active element in the semiconductor device of Example 5 includes the gate electrode 12, the gate insulating layer 13 (corresponding to the base 11), the channel formation region 15, and the source / drain electrode 14 as in Example 1. The channel formation region 15 is configured by the conductive path 21. The fine particles 22 are arranged two-dimensionally regularly and in a filled state in a plane substantially parallel to the surface of the substrate 11 (gate insulating layer 13) to constitute the fine particle layer 20. Specifically, the active element in the semiconductor device of Example 5 is a bottom gate / bottom contact type FET (more specifically, a TFT), and the conductivity of the conductive path 21 by an electric field applied to the conductive path 21. Is controlled. The conceptual diagram of charge transfer is the same as that indicated by the arrows in FIGS.

More specifically, the active element in the semiconductor device of the fifth embodiment is similar to the first embodiment as shown in the schematic partial end view of FIG.
(A) a gate electrode 12 formed on the support 10;
(B) a gate insulating layer 13 (corresponding to the substrate 11) formed on the support 10 and the gate electrode 12;
(C) a source / drain electrode 14 formed on the gate insulating layer 13, and
(D) a channel forming region 15 formed between the source / drain electrodes 14 and on the gate insulating layer 13 and configured by the conductive path 21;
It is composed of

In Example 5, the fine particles 22 made of a conductor, the organic semiconductor molecules 23, the support 10, the insulating layer 10B formed on the surface, the gate electrode 12, the source / drain electrodes 14, the channel formation region 15, and the channel formation The region constituting layer 15A includes the same fine particles 22, organic semiconductor molecules 23, support 10 as in Example 1, and the insulating layer 10B, gate electrode 12, source / drain electrodes 14, and channel formation region 15 formed on the surface thereof. , And a channel formation region constituting layer 15A. The substrate 11 is also made of a gate insulating layer 13 (specifically, SiO ₂ ) as in the first embodiment. A silicon semiconductor substrate can also be used as the substrate 10A.

  3 (A) to 3 (C), which are schematic partial end views of the substrate and the like, and FIG. 8, a method for forming the fine particle layer structure of Example 5, and further, a semiconductor device An outline of the manufacturing method will be described.

[Step-500]
First, the gate electrode 12 is formed on the support 10 in the same manner as in [Step-100] of Example 1 (see FIG. 3A).

[Step-510]
Next, in the same manner as in [Step-110] in Example 1, a gate insulating layer 13 corresponding to the base 11 is formed on the support 10 including the gate electrode 12 (see FIG. 3B).

[Step-520]
Thereafter, in the same manner as in [Step-120] of Example 1, a source / drain electrode 14 made of a gold (Au) layer is formed on the gate insulating layer 13 (see FIG. 3C).

[Step-530]
Next, after forming a photosensitive resin layer 131 on the substrate 11 (gate insulating layer 13), the resin layer 131 is exposed and developed, so that the separation region 130 is formed of the resin layer 131 whose side walls are undercut. Is left on the substrate 11 (see FIG. 8).

Specifically, a resin layer 131 made of a negative permanent resist material (manufactured by Tokyo Ohka Kogyo Co., Ltd .: TELR-N101PM) is applied on the gate insulating layer 13 corresponding to the substrate 11 by spin coating, Next, after pre-baking at 100 ° C. for 1 minute on a hot plate, a photolithography technique with an exposure amount of 50 mJ / cm ² , a post at 120 ° C. for 1.5 minutes on the hot plate -Exposure baking, development, rinsing, and post-baking on a hot plate at 180 ° C to 200 ° C for about 20 minutes to form a resin layer 131 on the portion of the substrate 11 where the separation region 130 is to be formed The remaining structure can be obtained. This permanent resist material is used, for example, for a cathode separator (for partition walls) of an organic EL display. The separation region 130 as the protruding portion thus obtained has an undercut shape (undercut structure, reverse taper structure), that is, a shape in which the upper portion of the side wall protrudes from the lower portion of the side wall constituting the separation region 130. Such a shape can be achieved by using a negative permanent resist material. The height H of the separation region 130 is about 1.4 μm. Also, the length L of one side of the wall-shaped isolation region 130 [the length (width) of the isolation region 130 lying between the portion of the base 11 where the active element is to be formed and the portion of the base 11 where the active element is to be formed. ] Was set to 100 μm, for example.

  In addition, the separation region 130 made of the photocured product of the resin layer 131 thus obtained is subjected to various heat treatments (post baking, etc.), and thus has high resistance to an organic solvent. As a result, it is not dissolved by the organic solvent used in the subsequent process, and the surface of the substrate exposed after forming the separation region can be cleaned using an organic solvent or ultrasonic waves. . Depending on the material constituting the separation region, physical treatment, chemical treatment, or thermal treatment can be applied to impart high resistance to the organic solvent, and the separation region is formed. It becomes possible to clean the surface of the substrate exposed later using an organic solvent or ultrasonic waves.

[Step-540]
Thereafter, in the same manner as in [Step-170] of Example 1, the fine particle layer 20 separated on the side wall of the separation region 130 is formed on the portion of the substrate 11 surrounded by the separation region 130.

[Step-550]
Next, in the same manner as in [Step-180] of Example 1, a channel formation region constituting layer 15A including the channel formation region 15 is formed based on the fine particle layer 20.

[Step-560]
Finally, a passivation film (not shown) is formed on the entire surface in the same manner as in [Step-190] of the first embodiment, so that the bottom gate / bottom contact FET (shown in FIG. Specifically, a TFT) can be obtained.

Isolation is realized by physically cutting the particulate layer 20 by the characteristic undercut structure (reverse taper structure) of the separation region 130. In Example 5, since the relationship between the height H of the separation region 130 and the average particle size R _AVE of the fine particles 22 is (H / R _AVE ) = (1400/5), the fine particle layer 20 is separated. In the area 130, the cut is surely physically performed.

  Here, in [Step-540], as in [Step-170] of Example 1, the self-organization phenomenon by the fine particles 22 itself is actively used to achieve the two-dimensional regular arrangement. Further, in the same manner as [Step-180] in Example 1, in [Step-550], the functional group at the terminal of the organic semiconductor molecule 23 is chemically bonded to the fine particles 22. More specifically, the functional group which the organic semiconductor molecule 23 has at both ends (in Example 5, an organic semiconductor molecule having a conjugated bond, which is a thiol group having both ends of 4,4′-biphenyldithiol (BPDT). The organic semiconductor molecules 23 and the fine particles 22 are chemically (alternatively) bonded to each other by [—SH]), whereby the network-like conductive path 21 is constructed. Since the channel forming region 15 can be formed by forming the fine particle layer 20 one by one, the channel forming region 15 having a desired thickness can be formed by repeating this process. The channel forming region 15 obtained in this way is composed of a combined body in which the fine particles 22 and the organic semiconductor molecules 23 are bonded in a network shape, and carrier movement is controlled by the gate voltage applied to the gate electrode 12. Specifically, for example, when the gate voltage applied to the gate electrode 12 is 0 volt, a source / drain current flows between the source / drain electrodes 14. Furthermore, the source / drain current flowing between the source / drain electrodes 14 can be controlled by controlling the direction (plus or minus) and the value of the gate voltage applied to the gate electrode 12. The same applies to the semiconductor devices obtained in Examples 6 to 8 below. In forming the fine particle layer 20 one by one, the fine particle layer 20 is reliably separated on the side wall of the separation region 130.

  Also in Example 5, in the channel forming region 15, the fine particles 22 are two-dimensionally or three-dimensionally connected by the organic semiconductor molecules 23, and the conductive path in the fine particles 22 and the molecular skeleton in the organic semiconductor molecules 23 are connected. A network-like conductive path 21 is formed in which the conductive paths along the path are connected. Then, as shown in the conceptual diagram of FIG. 2B, the conductive path 21 does not include intermolecular electron transfer that is a cause of low mobility in a channel formation region made of a conventional organic semiconductor, In addition, since the electron movement in the molecule is performed through a conjugated system formed along the molecular skeleton, high mobility is expected. Electron conduction in the channel formation region 15 is performed through a network-like conductive path 21 as indicated by an arrow in FIG. 2A, and the conductivity of the channel formation region 15 is applied to the gate electrode 12. Controlled by voltage.

  Alternatively, in [Step-550], as described in Example 1, a three-dimensionally networked cluster formed by combining fine particles and organic semiconductor molecules is applied to the entire surface, and natural The fine particle layer 20 formed on the portion of the base 11 surrounded by the separation region 130 and separated on the side wall of the separation region 130 can also be obtained by drying.

A prototype similar to that described in Example 1 was prototyped instead of the semiconductor device having the structure shown in FIG. Then, by bringing probes into contact with the silicon semiconductor substrate and the source electrode, when a voltage is applied to V _g between the probes, the current flowing between the probe I _g - was measured (gate electrode leakage current I _g between the source electrode) . As a result, when a voltage V _g from −1 volt to +1 volt was applied between the probes, the maximum value of the current I _g flowing between the probes was 3 picoamperes, and a very small leakage current value was obtained. Incidentally, when 1 volt was applied to the gate electrode, a large current close to 1 milliampere flowed between the source electrode and the drain electrode.

The sixth embodiment is a modification of the fifth embodiment. The active element in the semiconductor device of Example 6 whose schematic partial end view is shown in FIG. 7B is a bottom gate / top contact type FET (specifically, TFT). That is, this active element is similar to the second embodiment,
(A) a gate electrode 12 formed on the support 10;
(B) a gate insulating layer 13 (corresponding to the substrate 11) formed on the gate electrode 12,
(C) a channel formation region constituting layer 15A including the channel formation region 15 formed on the gate insulating layer 13 and constituted by the conductive path 21, and
(D) source / drain electrodes 14 formed on the channel formation region constituting layer 15A;
It has.

  The outline of the method for manufacturing the semiconductor device of Example 6 will be described below.

[Step-600]
First, after forming the gate electrode 12 on the support 10 in the same manner as in [Step-500] in Example 5, the support including the gate electrode 12 in the same manner as in [Step-510] in Example 5. A gate insulating layer 13 corresponding to the base 11 is formed on (more specifically, the insulating layer 10B).

[Step-610]
Next, the same process as [Step-530] in Example 5 is performed to complete the separation region 130 on the substrate 11, and then the same process as [Step-540] in Example 5 is performed. As a result, the fine particle layer 20 separated on the side wall of the separation region 130 is formed on the portion of the substrate 11 surrounded by the separation region 130, and further, the same as [Step-550] of the fifth embodiment. By executing the process, the channel formation region constituting layer 15 </ b> A including the channel formation region 15 is formed based on the fine particle layer 20.

[Step-620]
Thereafter, the source / drain electrodes 14 are formed on the channel formation region constituting layer 15A so as to sandwich the channel formation region 15. Specifically, a gold (Au) layer as the source / drain electrode 14 is formed based on the vacuum deposition method in the same manner as in [Step-220] of the second embodiment.

[Step-630]
Finally, by forming a passivation film (not shown) on the entire surface, the semiconductor device of Example 6 shown in FIG. 7B can be completed.

The seventh embodiment is also a modification of the fifth embodiment. The active element in the semiconductor device of Example 6 whose schematic partial end view is shown in FIG. 9A is a top gate / bottom contact type FET (specifically, TFT). That is, this active element is the same as in Example 3,
(A) source / drain electrodes 14 formed on the substrate 11;
(B) a channel forming region 15 formed on the substrate 11 between the source / drain electrodes 14 and configured by the conductive path 21;
(C) a gate insulating layer 13 formed on the source / drain electrode 14 and the channel formation region 15, and
(D) a gate electrode 12 formed on the gate insulating layer 13;
It has.

  The outline of the method for manufacturing the semiconductor device of Example 7 will be described below.

[Step-700]
First, a base 11 made of SiO ₂ is formed on the surface of a support 10 made of a glass substrate by, for example, a CVD method. Then, the source / drain electrodes 14 are formed on the substrate 11 in the same manner as in [Step-300] of the third embodiment.

[Step-710]
Next, the same process as [Step-530] in Example 5 is performed to complete the separation region 130 on the substrate 11, and then the same process as [Step-540] in Example 5 is performed. As a result, the fine particle layer 20 separated on the side wall of the separation region 130 is formed on the portion of the substrate 11 surrounded by the separation region 130, and further, the same as [Step-550] of the fifth embodiment. By executing the process, the channel formation region constituting layer 15 </ b> A including the channel formation region 15 is formed based on the fine particle layer 20.

[Step-720]
Thereafter, in the same manner as in [Step-320] in Example 3, the gate insulating layer 13 is formed on the entire surface, and then the gate electrode 12 is formed on the portion of the gate insulating layer 13 located on the channel formation region 15. To do.

[Step-730]
Finally, by forming a passivation film (not shown) on the entire surface, the semiconductor device of Example 7 shown in FIG. 9A can be completed.

The eighth embodiment is also a modification of the fifth embodiment. The active element in the semiconductor device of Example 6 whose schematic partial end view is shown in FIG. 9B is a top gate / top contact type FET (specifically, TFT). That is, this active element is similar to the fourth embodiment,
(A) a channel formation region constituting layer 15A including the channel formation region 15 formed on the base 11 and constituted by the conductive path 21;
(B) source / drain electrodes 14 formed on the channel formation region constituting layer 15A;
(C) a gate insulating layer 13 formed on the source / drain electrode 14 and the channel formation region 15, and
(D) a gate electrode 12 formed on the gate insulating layer 13;
It has.

  The outline of the method for manufacturing the semiconductor device of Example 8 will be described below.

[Step-800]
First, a base 11 made of SiO ₂ is formed on the surface of a support 10 made of a glass substrate by, for example, a CVD method. Then, the same process as [Step-530] in Example 5 is performed to complete the separation region 130 on the substrate 11, and then the same process as [Step-540] in Example 5 is performed. Thus, the fine particle layer 20 separated on the side wall of the separation region 130 is formed on the portion of the substrate 11 surrounded by the separation region 130, and further, the same process as [Step-550] of the fifth embodiment. As a result, the channel formation region constituting layer 15A including the channel formation region 15 is formed based on the fine particle layer 20.

[Step-810]
Thereafter, the source / drain electrodes 14 are formed on the channel formation region constituting layer 15A in the same manner as in [Step-410] of the fourth embodiment.

[Step-820]
Thereafter, in the same manner as in [Step-720] in Example 7, the gate insulating layer 13 is formed on the entire surface, and then the gate electrode 12 is formed on the portion of the gate insulating layer 13 located on the channel formation region 15. To do.

[Step-830]
Finally, by forming a passivation film (not shown) on the entire surface, the semiconductor device of Example 8 shown in FIG. 9B can be completed.

As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to these Examples. The structure and configuration of the separation region, the fine particle layer structure, and the semiconductor device, the formation conditions, and the manufacturing conditions are examples, and can be changed as appropriate. When the field effect transistor (FET) obtained by the present invention is applied to and used in a display device and various electronic devices, a monolithic integrated circuit in which a large number of FETs are integrated on a support or a support member may be used. The FET may be cut and individualized and used as a discrete component. The fine particles are not limited to gold (Au), but are not limited to other metals (for example, silver and platinum), cadmium sulfide, cadmium selenide, silicon and the like as semiconductors, but also poly (3,4- It can also be composed of a conductive organic material such as ethylenedioxythiophene) / polystyrene sulfonic acid [PEDOT / PSS], polythiophene, polyaniline. Further, the organic semiconductor molecule is not limited to 4,4′-biphenyldithiol (BPDT). Furthermore, in the first to fourth embodiments, the lower layer 31 constituting the separation region 30 may be made of, for example, SiN _Y , and the upper layer 32 may be made of, for example, SiO _x . Furthermore, in the embodiments, the isolation region, the fine particle layer structure and the method for forming the same according to the present invention are applied to the element isolation region in the semiconductor device, but it is also required to form a separate fine particle layer. It can be applied to any field and area.

FIGS. 1A and 1B are schematic partial end views of the fine particle layer structure, the semiconductor device, and the separation region of Example 1 and Example 2. FIG. 2A is a conceptual diagram of a part of the semiconductor device according to the first embodiment, and FIG. 2B is a conceptual diagram of a conductive path constituted by fine particles and organic semiconductor molecules. 3A to 3C are schematic partial end views of a substrate and the like for explaining the method for forming the fine particle layer structure of Example 1. FIG. 4 (A) and 4 (B) are schematic partial end views of the substrate and the like for explaining the method for forming the fine particle layer structure of Example 1 following FIG. 3 (C). FIGS. 5A and 5B are schematic partial end views of a substrate and the like for explaining the method of forming the fine particle layer structure of Example 1 following FIG. 4B. 6A and 6B are schematic partial end views of the fine particle layer structure, the semiconductor device, and the separation region of Example 3 and Example 4. FIG. 7A and 7B are schematic partial end views of the fine particle layer structure, the semiconductor device, and the separation region of Example 5 and Example 6. FIG. FIG. 8 is a schematic partial end view of a substrate and the like for explaining the method for forming the fine particle layer structure of Example 5 following FIG. 9A and 9B are schematic partial end views of the fine particle layer structure, the semiconductor device, and the separation region of Example 7 and Example 8. FIG. FIG. 10 is a graph showing the measurement result of the leakage current in the prototype of the semiconductor device of Example 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Support body, 10A ... Glass substrate, 10B ... Insulating layer, 11 ... Base | substrate, 12 ... Gate electrode, 13 ... Gate insulating layer, 14 ... Source / drain electrode 15 ... channel forming region, 15A ... channel forming region constituting layer, 20 ... fine particle layer, 21 ... conductive path, 22 ... fine particle, 23 ... organic semiconductor molecule, 30, 130 ... Separation region, 31 ... lower layer, 32 ... upper layer, 41 ... resist layer, 42 ... opening, 131 ... photosensitive resin layer

Claims (25)

(A) a separation region formed on a substrate, having a wall-like two-layer structure, in which a lower side wall is undercut, and
(B) a fine particle layer formed on the portion of the substrate surrounded by the separation region;
A fine particle layer structure comprising:
The fine particle layer structure, wherein the fine particle layer is separated on a side wall of the separation region.   2. The fine particle layer structure according to claim 1, wherein a combination of (material constituting the lower layer and material constituting the upper layer) is (oxide, nitride) or (nitride, oxide). When the average particle size of the fine particles is R _AVE , the height H of the separation region is
(H / R _AVE ) ≧ 5 × 10 ¹
The fine particle layer structure according to claim 1, wherein: (A) After forming a resist layer having an opening on the substrate,
(B) A lower layer and an upper layer constituting the separation region are sequentially formed on the resist layer and on the portion of the base exposed in the opening, and then
(C) After etching the lower sidewall so that the lower sidewall is undercut,
(D) removing the resist layer and leaving an isolation region on the substrate;
(E) forming a particulate layer separated on the side wall of the separation region on the portion of the substrate surrounded by the separation region;
A method of forming a fine particle layer structure comprising the steps.   The combination of (material constituting the lower layer, material constituting the upper layer) is (oxide, nitride) or (nitride, oxide). Forming method. When the average particle size of the fine particles is R _AVE , the height H of the separation region is
(H / R _AVE ) ≧ 5 × 10 ¹
The method for forming a fine particle layer structure according to claim 4, wherein: (A) a separation region formed on a substrate, having a wall-like two-layer structure, in which a lower side wall is undercut, and
(B) an active element formed on the portion of the substrate surrounded by the isolation region;
A semiconductor device comprising:
The active element includes a fine particle made of a conductor or a semiconductor, and a conductive path made of an organic semiconductor molecule bonded to the fine particle,
A semiconductor device, wherein the fine particle layer composed of the fine particles is separated on a side wall of the separation region.   8. The semiconductor device according to claim 7, wherein the functional group at the terminal of the organic semiconductor molecule is chemically bonded to the fine particles.   9. The semiconductor device according to claim 8, wherein a network-like conductive path is constructed by chemically bonding the organic semiconductor molecule and the fine particles by the functional groups possessed by the organic semiconductor molecule at both ends.   8. The semiconductor device according to claim 7, wherein the conductivity of the conductive path is controlled by an electric field applied to the conductive path. The active element comprises a field effect transistor having a gate electrode, a gate insulating layer, a channel formation region, and a source / drain electrode,
The semiconductor device according to claim 10, wherein a channel formation region is formed by the conductive path.   8. The semiconductor device according to claim 7, wherein the combination of (material constituting the lower layer and material constituting the upper layer) is (oxide, nitride) or (nitride, oxide). When the average particle size of the fine particles was R _AVE, the height H of the separation region,
(H / R _AVE ) ≧ 5 × 10 ¹
The semiconductor device according to claim 7, wherein:   A separation region having a wall-like two-layer structure formed on a substrate, wherein a lower wall surface has an undercut shape. (A) a separation region having a wall-shaped single layer structure formed on a substrate and having a side wall in an undercut shape; and
(B) a fine particle layer formed on the portion of the substrate surrounded by the separation region;
A fine particle layer structure comprising:
The fine particle layer structure, wherein the fine particle layer is separated on a side wall of the separation region. When the average particle size of the fine particles is R _AVE , the height H of the separation region is
(H / R _AVE ) ≧ 5 × 10 ¹
The fine particle layered structure according to claim 15, wherein: (A) After forming a photosensitive resin layer on the substrate, the resin layer is exposed and developed to leave a separation region on the substrate whose side wall is made of an undercut resin layer;
(B) forming a fine particle layer separated on the side wall of the separation region on the portion of the substrate surrounded by the separation region;
A method of forming a fine particle layer structure comprising the steps. When the average particle size of the fine particles is R _AVE , the height H of the separation region is
(H / R _AVE ) ≧ 5 × 10 ¹
The method for forming a fine particle layer structure according to claim 17, wherein: (A) a separation region having a wall-shaped single layer structure formed on a substrate and having a side wall in an undercut shape; and
(B) an active element formed on the portion of the substrate surrounded by the isolation region;
A semiconductor device comprising:
The active element includes a fine particle made of a conductor or a semiconductor, and a conductive path made of an organic semiconductor molecule bonded to the fine particle,
A semiconductor device, wherein the fine particle layer composed of the fine particles is separated on a side wall of the separation region.   20. The semiconductor device according to claim 19, wherein the functional group at the terminal of the organic semiconductor molecule is chemically bonded to the fine particles.   21. The semiconductor device according to claim 20, wherein a network-like conductive path is constructed by chemically bonding the organic semiconductor molecules and the fine particles by the functional groups possessed by the organic semiconductor molecules at both ends.   The semiconductor device according to claim 19, wherein conductivity of the conductive path is controlled by an electric field applied to the conductive path. The active element comprises a field effect transistor having a gate electrode, a gate insulating layer, a channel formation region, and a source / drain electrode,
23. The semiconductor device according to claim 22, wherein a channel formation region is formed by the conductive path. When the average particle size of the fine particles is R _AVE , the height H of the separation region is
(H / R _AVE ) ≧ 5 × 10 ¹
The semiconductor device according to claim 19, wherein:   A separation region having a wall-like single layer structure formed on a substrate and having a side wall having an undercut shape.

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