JP2007329493A5 - - Google Patents
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- JP2007329493A5 JP2007329493A5 JP2007196840A JP2007196840A JP2007329493A5 JP 2007329493 A5 JP2007329493 A5 JP 2007329493A5 JP 2007196840 A JP2007196840 A JP 2007196840A JP 2007196840 A JP2007196840 A JP 2007196840A JP 2007329493 A5 JP2007329493 A5 JP 2007329493A5
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- JP
- Japan
- Prior art keywords
- mold
- film
- cavity
- circuit device
- chip support
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims 18
- 238000004519 manufacturing process Methods 0.000 claims 9
- 239000011347 resin Substances 0.000 claims 5
- 229920005989 resin Polymers 0.000 claims 5
- 239000000758 substrate Substances 0.000 claims 4
- 238000000465 moulding Methods 0.000 claims 3
- 238000007789 sealing Methods 0.000 claims 3
- 238000004804 winding Methods 0.000 claims 1
Claims (12)
(b)凹凸が形成された第1面、および前記第1面とは反対側の第2面を有する樹脂系のフィルムと、組み立て体とを、前記第1金型の前記第1キャビティと前記第2金型の前記第2金型面との間に配置する工程、
(c)前記第1金型および前記第2金型を閉じ、前記第1キャビティ内にモールド樹脂を充填し、前記組み立て体に封止部を形成する工程、
(d)前記(c)工程の後、前記第1金型と前記第2金型を開いて、前記封止部が形成された前記組み立て体を前記モールド金型から離型する工程、
を含み、
前記(b)工程では、前記フィルムの前記第1面が前記第1キャビティと対向するように、前記第1キャビティと前記第2金型面との間に前記フィルムを、前記フィルムと前記第2金型面との間に前記組み立て体を配置し、
前記(c)工程では、前記フィルムと前記組み立て体との間に前記モールド樹脂を供給することを特徴とする半導体集積回路装置の製造方法。 (A) a first mold surface , a first mold having a first cavity formed on the first mold surface, and a second mold surface having a second mold surface facing the first mold surface. preparing a molding die a composed of a mold,
(B) a first surface on which irregularities are formed, and a film of the resin system having a second surface opposite the first surface, and assembly, and the first cavity of the first mold wherein step to place between the second mold surface of the second mold,
(C) closing Ji previous SL first mold and the second mold, a molding resin to Hama charge within the first cavity, forming a seal on the assembly,
After; (d) (c) step, the first open mold and the second mold, a step of releasing the assembly the sealing portion is formed from the mold,
Only including,
In the step (b), the film is placed between the first cavity and the second mold surface so that the first surface of the film faces the first cavity. Place the assembly between the mold surface and
In the step (c), the mold resin is supplied between the film and the assembly .
前記モールド金型の前記第1金型には、前記第1キャビティに開口する吸引口が設けられており、
前記モールド樹脂を前記第1キャビティ内に充填する前に、前記吸引口を介して前記フィルムを吸引し、前記フィルムの前記第1面を前記第1キャビティに密着させることを特徴とする半導体集積回路装置の製造方法。 And have you to claim 1,
The first mold of the mold is provided with a suction port that opens to the first cavity;
Before filling the molding resin into the first cavity, the film was drawn through the suction port, a semiconductor integrated characterized by Rukoto brought into close contact with the first surface of the film to the first cavity A method of manufacturing a circuit device.
前記(b)工程では、前記フィルムを前記第1金型の前記第1キャビティと前記第2金型の前記第2金型面との間に配置し、前記フィルムを吸引してから、前記フィルムと前記第2金型の前記第2金型面との間に前記組み立て体を配置することを特徴とする半導体集積回路装置の製造方法。 And have you to claim 2,
Wherein in the step (b), the film is disposed between the second die surface of said second mold and said first mold the first cavity, after sucking the film, the A manufacturing method of a semiconductor integrated circuit device , wherein the assembly is disposed between a film and the second mold surface of the second mold .
前記第1金型の前記第1キャビティと前記第2金型の前記第2金型面との間に前記フィルムを配置する前に、前記フィルムにイオン化されたドライエアーを供給することを特徴とする半導体集積回路装置の製造方法。 And have you to claim 4,
Before the film is disposed between the first cavity of the first mold and the second mold surface of the second mold, ionized dry air is supplied to the film. A method for manufacturing a semiconductor integrated circuit device.
前記フィルムは、フィルム供給ローラにより前記第1金型の前記第1キャビティと前記第2金型の前記第2金型面との間に供給され、
前記封止部を形成し、前記第1金型と前記第2金型を開いた後、フィルム巻取りローラにより前記第1金型の前記第1キャビティと前記第2金型の前記第2金型面との間から前記フィルムを巻き取ることを特徴とする半導体集積回路装置の製造方法。 And have you to claim 4,
The film is supplied between the first cavity of the first mold and the second mold surface of the second mold by a film supply roller,
After forming the sealing portion and opening the first mold and the second mold, the first cavity of the first mold and the second mold of the second mold by a film winding roller. A method for manufacturing a semiconductor integrated circuit device, wherein the film is wound from between mold surfaces .
前記組み立て体は、チップ支持部材と、前記チップ支持部材上に搭載された半導体チップとで構成され、The assembly is composed of a chip support member and a semiconductor chip mounted on the chip support member,
前記(b)工程では、前記第1キャビティと前記半導体チップとの間に前記フィルムを配置することを特徴とする半導体集積回路装置の製造方法。In the step (b), the film is disposed between the first cavity and the semiconductor chip. A method of manufacturing a semiconductor integrated circuit device, comprising:
前記チップ支持部材は、基板電極が形成されたチップ支持面、および前記チップ支持面とは反対側の裏面を有し、The chip support member has a chip support surface on which a substrate electrode is formed, and a back surface opposite to the chip support surface,
前記半導体チップは、パッドが形成された主面を有し、The semiconductor chip has a main surface on which pads are formed,
前記組み立て体は、前記チップ支持部材と、前記半導体チップと、前記チップ支持部材の前記基板電極と前記半導体チップの前記パッドとを電気的に接続する接続部材とで構成されることを特徴とする半導体集積回路装置の製造方法。The assembly includes the chip support member, the semiconductor chip, and a connection member that electrically connects the substrate electrode of the chip support member and the pad of the semiconductor chip. A method of manufacturing a semiconductor integrated circuit device.
前記接続部材はボンディングワイヤであることを特徴とする半導体集積回路装置の製造方法。The method for manufacturing a semiconductor integrated circuit device, wherein the connecting member is a bonding wire.
前記チップ支持部材は、基板電極がそれぞれに形成された複数のチップ支持面、および前記複数のチップ支持面とは反対側の裏面を有し、The chip support member has a plurality of chip support surfaces each having a substrate electrode formed thereon, and a back surface opposite to the plurality of chip support surfaces.
前記半導体チップは、パッドが形成された主面を有し、The semiconductor chip has a main surface on which pads are formed,
前記組み立て体は、前記チップ支持部材の前記複数のチップ支持面上のそれぞれに搭載された複数の前記半導体チップと、前記チップ支持部材の前記基板電極と複数の前記半導体チップのそれぞれの前記パッドとを電気的に接続する接続部材とで構成されることを特徴とする半導体集積回路装置の製造方法。The assembly includes a plurality of the semiconductor chips mounted on each of the plurality of chip support surfaces of the chip support member, the substrate electrode of the chip support member, and the pads of the plurality of semiconductor chips. And a connecting member for electrically connecting the semiconductor integrated circuit device.
前記接続部材はボンディングワイヤであることを特徴とする半導体集積回路装置の製造方法。The method for manufacturing a semiconductor integrated circuit device, wherein the connecting member is a bonding wire.
前記(c)工程では、トランスファー方式により前記モールド樹脂を充填することを特徴とする半導体集積回路装置の製造方法。In the step (c), the mold resin is filled by a transfer method.
前記モールド金型から離型された前記封止部の表面は、粗面に形成されていることを特徴とする半導体集積回路装置の製造方法。The method of manufacturing a semiconductor integrated circuit device, wherein a surface of the sealing part released from the mold is formed into a rough surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007196840A JP4397942B2 (en) | 2007-07-30 | 2007-07-30 | Manufacturing method of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007196840A JP4397942B2 (en) | 2007-07-30 | 2007-07-30 | Manufacturing method of semiconductor integrated circuit device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005116766A Division JP4012210B2 (en) | 2005-04-14 | 2005-04-14 | Manufacturing method of semiconductor integrated circuit device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009199137A Division JP5119221B2 (en) | 2009-08-31 | 2009-08-31 | Manufacturing method of semiconductor integrated circuit device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007329493A JP2007329493A (en) | 2007-12-20 |
JP2007329493A5 true JP2007329493A5 (en) | 2009-03-19 |
JP4397942B2 JP4397942B2 (en) | 2010-01-13 |
Family
ID=38929709
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007196840A Expired - Fee Related JP4397942B2 (en) | 2007-07-30 | 2007-07-30 | Manufacturing method of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
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JP (1) | JP4397942B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5235506B2 (en) * | 2008-06-02 | 2013-07-10 | キヤノン株式会社 | Pattern transfer apparatus and device manufacturing method |
JP5148376B2 (en) * | 2008-06-11 | 2013-02-20 | 日本写真印刷株式会社 | Injection mold and method of manufacturing resin molded product using the same |
JP5119221B2 (en) * | 2009-08-31 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor integrated circuit device |
WO2017145924A1 (en) * | 2016-02-26 | 2017-08-31 | キヤノン株式会社 | Imprint device, operating method for same, and method for manufacturing article |
JP6603678B2 (en) * | 2016-02-26 | 2019-11-06 | キヤノン株式会社 | Imprint apparatus, operation method thereof, and article manufacturing method |
-
2007
- 2007-07-30 JP JP2007196840A patent/JP4397942B2/en not_active Expired - Fee Related
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