JP2007329292A - Semiconductor optical integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor optical integrated circuit which can prevent a malfunction of the circuit due to incident light from a pad without installing an additional element. <P>SOLUTION: Around the pad 1, diodes 2 and 3 are arranged which are static electricity prevention elements. Negative charge generated in a semiconductor substrate 10 due to the incident light from the pad 1 moves to a power supply Vcc via the diode 2, while positive charge moves to a ground potential GND via the diode 3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor optical integrated circuit in which an optical device composed of a semiconductor material and an electronic device are integrated.

  Conventionally, a semiconductor optical integrated circuit in which a photodiode and a circuit element for signal processing are integrated is known. In such a semiconductor optical integrated circuit, light is blocked by a light-shielding film made of an aluminum wiring layer or the like on the circuit element so that unnecessary light from the outside enters the semiconductor substrate and excess photocurrent flows and the circuit does not malfunction. is doing. However, since the light shielding film must be opened on the pad portion for performing signal input from the outside or signal output to the outside, the circuit may malfunction due to incident light from the pad portion.

  Therefore, in order to prevent an excessive photocurrent generated in the semiconductor substrate due to incident light from the pad portion from entering a peripheral circuit including an NPN transistor and the like and malfunctioning of the circuit, a dummy photodiode is adjacent to the photodiode. And a method of covering the peripheral circuit portion and the upper portion of the dummy photodiode with aluminum wiring has been proposed (for example, see Patent Document 1).

However, if a new element such as a dummy photodiode is provided to absorb unnecessary light, there is a problem that the chip area increases and the cost increases.
JP-A-9-293847

  In view of the above problems, the present invention provides a new element by adopting a configuration in which an electrostatic protection element formed around a pad portion absorbs charges generated inside the semiconductor substrate by incident light from the pad portion. An object of the present invention is to provide a semiconductor optical integrated circuit that can prevent malfunction of the circuit due to incident light from the pad portion.

  The semiconductor optical integrated circuit according to claim 1 of the present invention is formed around a circuit element on a semiconductor substrate, a pad portion for performing signal input from the outside or signal output to the outside, and the periphery of the pad portion. An electrostatic protection element including a static electricity protection element through which a current for dropping or raising the voltage when a voltage exceeding a predetermined voltage range is applied to the pad portion. The element is configured to absorb charges generated in the semiconductor substrate by incident light from the pad portion.

  A semiconductor optical integrated circuit according to a second aspect of the present invention is the semiconductor optical integrated circuit according to the first aspect, wherein the electrostatic protection element is a diode. A semiconductor optical integrated circuit according to a third aspect of the present invention is the semiconductor optical integrated circuit according to the first aspect, wherein the electrostatic protection element includes an NPN transistor and a diode.

  According to the present invention, since the electrostatic protection element for preventing the destruction of the internal circuit due to external static electricity absorbs the charge generated in the semiconductor substrate by the incident light from the pad portion, the incident light from the pad portion Can prevent malfunction of the circuit. Further, it is not necessary to provide a new element such as a dummy photodiode, and the chip area can be suppressed.

(Embodiment 1)
Hereinafter, Embodiment 1 of the present invention will be described in detail with reference to the drawings.
The semiconductor optical integrated circuit according to the first embodiment includes a photodiode on a semiconductor substrate, a circuit element for signal processing, a pad portion for performing signal input from the outside or signal output to the outside, The electrostatic protection element formed around is provided in a state separated by a separation region. When a voltage exceeding a predetermined voltage range is applied to the pad portion, the electrostatic protection element flows a current for decreasing or increasing the voltage by the amount exceeding the predetermined voltage range, thereby preventing damage to the internal circuit due to static electricity.

  FIG. 1 is a plan view showing a pad portion of a semiconductor optical integrated circuit according to Embodiment 1 of the present invention. 2 is a cross-sectional view taken along line AA shown in FIG. FIG. 3 is a schematic circuit diagram of the semiconductor optical integrated circuit according to the first embodiment of the present invention.

  As shown in FIGS. 1 and 2, a diode portion 2 and a diode portion 3, which are electrostatic protection elements, are formed around the pad portion 1. Further, as shown in FIG. 3, the pad portion 1 and the internal circuit (signal processing circuit element) are connected, and the diode portion 2 and the diode portion 3 are applied with a high voltage due to static electricity to the internal circuit. To prevent.

  As shown in FIG. 2, the pad portion 1 includes an N-type island region 12 formed on a P-type semiconductor substrate 10 and separated by a P-type isolation region 11, and an N-type island region 12. It is comprised by the electrode 12a connected to.

  The diode portion 2 formed around the pad portion 1 has an N-type island region 13 formed on the P-type semiconductor substrate 10 and separated by the P-type isolation region 11 as a cathode, and the N-type The P + type region 14 formed on the surface of the island region 13 is an anode, and the electrode 13a is connected to the N type island region 13 and the electrode 14a is connected to the P + type region 14. The power supply Vcc is connected to the electrode 13a (cathode), and the electrode 12a of the pad portion 1 is connected to the electrode 14a (anode).

  The diode portion 3 formed around the diode portion 2 is formed on the P-type semiconductor substrate 10 and has an N-type island region 15 separated by the P-type isolation region 11 as a cathode, and a P-type semiconductor. The electrode 10a is connected to the N-type island region 15 and the electrode 11a is connected to the P-type isolation region 11. Is connected. Further, the electrode 12a of the pad portion 1 is connected to the electrode 15a (cathode), and the ground potential GND is connected to the electrode 11a (anode).

  With the above configuration, even when an excessive voltage exceeding a predetermined voltage range is applied to the pad unit 1 from the outside due to static electricity when the semiconductor optical integrated circuit is not operating, the diode unit 2 is forward biased in the case of a positive voltage. The current flows to the power supply Vcc and the voltage drops by an amount exceeding the predetermined voltage range. In the case of a negative voltage, the diode unit 3 is forward-biased and the current flows to the ground potential GND. Since the voltage rises by the amount exceeding the voltage range, it is possible to prevent an excessive voltage from being applied to the internal circuit.

  On the other hand, when light is incident on the pad portion 1 during operation of the semiconductor optical integrated circuit and charges are generated in the P-type semiconductor substrate 10, the positive charges are reversely biased by the diode portion 3 and the P-type isolation region 11 and It moves to the ground potential GND through the electrode 11a, and the negative charge moves to the power source Vcc through the N-type island region 13 and the electrode 13a by the reverse-biased diode portion 2.

  As described above, the electric charge generated in the P-type semiconductor substrate 10 by the incident light from the pad portion 1 is absorbed by the diode portion 2 and the diode portion 3 which are electrostatic protection elements formed around the pad portion 1 and grounded. Since the voltage moves to the potential GND or the power supply Vcc, the charge does not reach the peripheral circuit elements, and the malfunction of the circuit can be prevented. In the first embodiment, the anode of the diode unit 3 is connected to the ground potential GND, but may be connected to a negative potential power source.

(Embodiment 2)
Hereinafter, Embodiment 2 of the present invention will be described in detail based on the drawings.
The semiconductor optical integrated circuit according to the second embodiment is different from the first embodiment described above in that the electrostatic protection element formed around the pad portion is composed of an NPN transistor and a diode.

  FIG. 4 is a plan view showing a pad portion of the semiconductor optical integrated circuit according to the second embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line BB shown in FIG. FIG. 6 is a schematic circuit diagram of the semiconductor optical integrated circuit according to the second embodiment of the present invention.

  As shown in FIGS. 4 and 5, an NPN transistor portion 5 and a diode portion 6, which are electrostatic protection elements, are formed around the pad portion 4. Further, as shown in FIG. 6, the pad unit 4 and the internal circuit (signal processing circuit element) are connected, and the NPN transistor unit 5 and the diode unit 6 are applied with a high voltage due to static electricity to the internal circuit. To prevent.

  As shown in FIG. 5, the pad portion 4 includes an N-type island region 22 formed on the P-type semiconductor substrate 20 and separated by the P-type isolation region 21, and an N-type island region 22. It is comprised by the electrode 22a connected to.

  The NPN transistor portion 5 formed around the pad portion 4 has an N-type island region 23 formed on the P-type semiconductor substrate 20 and separated by the P-type isolation region 21 as a collector, and an N-type transistor region 5. The P + type region 24 formed on the surface of the island region 23 is a base, and the N + type region 25 formed on the surface of the P + type region 24 is an emitter. An electrode 23a is connected to the N type island region 23. The P + region 24 is connected to an electrode 24a, and the N + region 25 is connected to an electrode 25a. The electrode 22a of the pad portion 4 is connected to the electrode 23a (collector), the ground potential GND is connected to the electrode 24a (base) via the resistor portion 8 (see FIG. 6), and the electrode 25a (emitter) is connected. Is connected to the ground potential GND.

  The diode section 6 formed around the NPN transistor section 5 has a configuration in which the N-type region 23 of the NPN transistor section 5 is a cathode, the P-type semiconductor substrate 10 and the P-type isolation region 21 are anodes, and P An electrode 21a is connected to the separation region 21 of the mold, and a ground potential GND is connected to the electrode 21a (anode). As described above, the electrode 23 a common to the collector of the NPN transistor unit 5 is used for the cathode of the diode unit 6.

  With the configuration as described above, even if an excessive voltage exceeding a predetermined voltage range is applied to the pad unit 4 from the outside due to static electricity when the semiconductor optical integrated circuit is not in operation, the collector of the NPN transistor unit 5 is in the case of a positive voltage. -A breakdown current flows between the bases, the base voltage rises due to the voltage drop of the resistance unit 8, the NPN transistor unit 5 operates, and the current flows to the ground potential GND through the collector-emitter and exceeds the predetermined voltage range. In the case of a negative voltage, the diode unit 6 is forward biased and the current flows to the ground potential GND, and the voltage increases by the amount exceeding the predetermined voltage range. It is possible to prevent an excessive voltage from being applied.

  On the other hand, when light is incident on the pad portion 4 during operation of the semiconductor optical integrated circuit and a charge is generated in the P-type semiconductor substrate 20, the positive charge is reversely biased by the diode portion 6 and the P-type isolation region 21 and It moves to the ground potential GND via the electrode 21a, and the negative charge moves to the pad portion 4 via the N-type island region 23 and the electrode 23a by the reverse-biased diode portion 6.

  As described above, the electric charge generated in the P-type semiconductor substrate 20 by the incident light from the pad portion 4 is absorbed by the diode portion 6 constituting the electrostatic protection element formed around the pad portion 4 to be ground potential GND or Since it moves to the pad portion 4, the charge does not reach the peripheral circuit elements, and malfunction of the circuit can be prevented.

  In the above configuration, the diode portion 6 is formed as a parasitic element of the NPN transistor portion 5, and can be composed of one element of the electrostatic protection element 7 as an element. Therefore, the area of the electrostatic protection element can be reduced, and an increase in the chip area can be suppressed.

  Next, the influence of the negative charge moving to the pad unit 4 on the signal output from the pad unit 4 will be described below. For example, in the case of a semiconductor optical integrated circuit used for an optical pickup device using a red laser, the power of reflected light received by a photodiode at the time of recording is about several mW, and incident light from the pad portion at that time is, for example, Assuming that it is 100 μW, since the photoelectric conversion efficiency of red light is about 0.3 A / W, the photocurrent generated by stray light from the pad portion is about 30 μA. Assuming that the output impedance of the pad portion is, for example, 100Ω, the output amplitude due to stray light is about 3 mV. Assuming that the amplitude of the original output signal is 1 V, for example, the output amplitude due to stray light is 0.3% of the output amplitude of the output signal. Therefore, even if the negative charge generated by stray light moves to the pad portion 4, the influence on the output signal of the pad portion 4 is very small and it can be said that there is no particular problem.

  The semiconductor optical integrated circuit according to the present invention absorbs the electric charge generated in the semiconductor substrate by the incident light from the pad portion by the electrostatic protection element provided around the pad portion, and can prevent malfunction of the internal circuit. This is useful for an optical integrated circuit in which an optical device such as a diode and a circuit element for signal processing are integrated.

The top view which showed the pad part of the semiconductor optical integrated circuit in Embodiment 1 of this invention AA arrow sectional view shown in FIG. 1 is a schematic circuit diagram of a semiconductor optical integrated circuit according to a first embodiment of the present invention. The top view which showed the pad part of the semiconductor optical integrated circuit in Embodiment 2 of this invention BB arrow sectional view shown in FIG. Schematic circuit diagram of a semiconductor optical integrated circuit according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 4 Pad part 2, 3, 6 Diode part 5 NPN transistor part 7 Electrostatic protection element 8 Resistor part 10, 20 P-type semiconductor substrate 11, 21 P-type isolation region 12, 13, 15, 22, 23 N-type Island region 11a to 15a, 21a to 25a Electrode 14, 24 P + type region 25 N + type region

Claims (3)

  A circuit element on a semiconductor substrate, a pad portion for performing signal input from outside or signal output to outside, and a pad portion formed around the pad portion, and a voltage exceeding a predetermined voltage range is applied to the pad portion. And an electrostatic protection element through which an electric current for dropping or increasing the voltage by an amount exceeding that is provided, wherein the electrostatic protection element is incident on the semiconductor substrate by incident light from the pad portion. A semiconductor optical integrated circuit characterized in that it is configured to absorb charges generated therein.   2. The semiconductor optical integrated circuit according to claim 1, wherein the electrostatic protection element comprises a diode. 2. The semiconductor optical integrated circuit according to claim 1, wherein the electrostatic protection element comprises an NPN transistor and a diode.

Images