JP2007329258A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a fully-silicided gate electrode that has a desired work function. <P>SOLUTION: Polysilicon is formed on a semiconductor substrate via a gate insulating film (a step S1). Impurities such as boron and arsenic are ion-implanted (a step S2). Then, the polysilicon is laser-irradiated (a step S3). The polysilicon after the laser irradiation is fully silicided (a step S4). Consequently, the fully-silicided gate electrode is formed. The laser irradiation after the ion implantation allows the impurities to be distributed in a gate electrode material without any restriction of the solid solubility limit of the gate electrode material. Accordingly, it is possible to form the fully-silicided gate electrode that has the work function corresponding to an amount of the introduced impurities. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a full silicide gate electrode.

  In a semiconductor device, a full silicide gate electrode is expected as a next-generation gate electrode structure that can suppress gate depletion, which is one of the problems of a conventional polysilicon gate electrode (see Patent Document 1).

  In addition to the general method of silicidation, a metal is deposited on the surface of polysilicon or the like and then heat treatment is performed to react the metal with silicon to form a silicide layer. Proposed. For example, a method has been proposed in which a metal deposited on a polysilicon surface is irradiated with a laser to melt the polysilicon, and the metal is diffused into the melted polysilicon to be silicided (see Patent Document 2).

  As an example of utilizing silicidation for semiconductor device manufacturing, there is a depth at which the concentration of activated impurities (carrier concentration) becomes maximum when heat treatment is performed after ion implantation of impurities into a semiconductor substrate. In view of this, a method has been proposed in which the semiconductor substrate after ion implantation and heat treatment is silicided and the interface between the silicide layer and the semiconductor substrate is retreated to a predetermined depth to increase the carrier concentration in the vicinity of the surface of the semiconductor substrate. (See Patent Document 3). In connection with the activation of such impurities, a method has also been proposed in which impurities are introduced into polysilicon, laser is irradiated to diffuse the impurities to the interface, and then the polysilicon surface is silicided. (Japanese Patent Application No. 2005-500909).

By the way, in order to apply a full silicide gate electrode to a CMOS (Complementary Metal Oxide Semiconductor) device constituting a high-speed LSI (Large Scale Integration) or the like, an n-channel is realized as realized by a conventional polysilicon gate electrode. The work function difference between a MOS (Metal Oxide Semiconductor) transistor (nMOS) and a p-channel MOS transistor (pMOS) is required to be about 1 eV. In addition, when applied to such a CMOS device, it is desirable to form the nMOS and the pMOS with the same gate electrode material in the manufacturing process.
JP 2006-1000043 A Japanese translation of PCT publication No. 2002-525868 Japanese Patent No. 3359925

  However, the full silicide gate electrode can obtain only one work function only by fully siliciding polysilicon. In order to apply the full silicide gate electrode to the CMOS device, as a method of separately forming the full silicide gate electrode of the nMOS and the pMOS, the concentration of impurities existing in the interface region with the gate insulating film is controlled, thereby There is a method for controlling the work function of the gate electrode.

  As a method for controlling the impurity concentration in the interface region with the gate insulating film, for example, after implanting a necessary amount of impurities into polysilicon, RTA (Rapid Thermal Anneal) is performed to remove impurities in the polysilicon. There is a method of thermally diffusing and then performing full silicidation from the surface side of the polysilicon and carrying (segregating) a predetermined amount of impurities to the interface region with the gate insulating film as silicidation proceeds. However, this method has the following problems.

  As an example, a case will be described in which boron (B), which is a p-type impurity, is ion-implanted into polysilicon formed on a silicon (Si) substrate via a gate insulating film, and RTA is performed to form full silicide.

First, the measurement result of the boron concentration distribution in the sample depth direction by SIMS (Secondary Ion Mass Spectroscopy) of the sample after RTA is shown.
FIG. 15 is a graph showing the relationship between the sample depth after RTA and the boron concentration.

FIG. 15 shows an acceleration energy of 5 keV, a dose of 1 × 10 ¹⁵ cm ⁻² , 5 × 10 ¹⁵ cm ⁻² , 1 × on polysilicon having a thickness of about 100 nm formed on a silicon substrate through a gate insulating film. The results of SIMS measurement are shown for a sample obtained by performing RTA at a temperature of 1000 ° C. for 10 seconds after boron is ion-implanted under each condition of 10 ¹⁶ cm ⁻² .

From FIG. 15, when the dose is increased from 1 × 10 ¹⁵ cm ⁻² to 5 × 10 ¹⁵ cm ⁻² five times, the boron concentration in the polysilicon also increases.
However, even if the dose amount is further doubled from 5 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² , the boron concentration in the polysilicon, particularly boron in the interface region between the polysilicon and the gate insulating film is increased. The concentration has hardly changed. This is because the maximum concentration of boron that can be thermally diffused in the polysilicon is limited by the solid solution limit depending on the temperature of the RTA.

FIG. 16 shows the relationship between the dose of boron and the flat band voltage.
FIG. 16 shows that when a predetermined dose of boron is ion-implanted into polysilicon and then fully silicided, the flat band voltage tends to increase with an increase in the dose of boron. However, when the boron dose exceeds a certain level, the flat band voltage tends to saturate at about 0.4 eV. In other words, even if the dose of boron to polysilicon is increased, if the dose exceeds a certain level, the impurity concentration in the interface region between the gate electrode and the gate insulating film after full silicidation is saturated. It shows that it has been. When the same measurement was performed by replacing boron with arsenic (As), which is an n-type impurity, the same result as in FIG. 16 was obtained.

FIG. 17 is a graph showing the relationship between the sample depth after full silicidation and the boron concentration.
In FIG. 17, boron is ion-implanted under conditions of an acceleration energy of 3 keV and a dose of 1 × 10 ¹⁶ cm ⁻² into polysilicon having a thickness of about 100 nm formed on a silicon substrate through a gate insulating film, and then RTA. This shows the result of SIMS measurement on a sample that has been subjected to full silicidation.

  From FIG. 17, the boron concentration obtained after full silicidation once decreases from the surface of the full silicide gate electrode of the sample toward the interface with the gate insulating film, and then decreases around the center of the full silicide gate electrode. And pile up in the interface region. From this measurement result, boron that piles up in the interface region is not all impurities introduced into the polysilicon, but mainly impurities that existed on the gate insulating film side from the middle of the polysilicon before full silicidation. Can be inferred.

  However, in order to increase the amount of impurities in the polysilicon before full silicidation, particularly the amount of impurities existing on the gate insulating film side from the middle, even if the dose amount during ion implantation is increased, FIG. As shown in FIG. 16 and FIG. 16, when the dose amount is a certain value or more, the impurity concentration in the interface region cannot be increased due to the solid solution limit in RTA, and a work function exceeding a certain value cannot be obtained. Therefore, even when a full silicide gate electrode for CMOS is formed using this method, the work function difference obtained so far between nMOS and pMOS is about 0.8 eV at the maximum.

  Thus, conventionally, a full silicide gate electrode having a desired work function cannot be formed, and therefore a large work function difference cannot be obtained between the nMOS and the pMOS. Although it can be applied to a power consumption device, it is extremely difficult to apply it to a high-speed device. However, the full silicide gate electrode is very effective for the gate depletion that can be a problem in the polysilicon gate electrode, and it is rather such a high-speed device that the gate depletion should be effectively suppressed. It is the direction.

  The present invention has been made in view of these points, and an object of the present invention is to provide a method of manufacturing a semiconductor device including a full silicide gate electrode having a desired work function.

  In the present invention, in order to solve the above problems, in a method of manufacturing a semiconductor device having a full silicide gate electrode, a step of forming a gate electrode material on a semiconductor substrate via a gate insulating film, and the formed gate electrode material There is provided a method for manufacturing a semiconductor device, comprising: introducing an impurity into the substrate; and irradiating a laser to fully silicide the gate electrode material into which the impurity has been introduced.

  According to such a method for manufacturing a semiconductor device, after introducing impurities into the gate electrode material, the gate electrode material is irradiated with a laser. Thereby, the impurities introduced into the gate electrode material are distributed in the gate electrode material without being limited by the solid solution limit due to, for example, melting or heating of the gate electrode material by laser irradiation. By performing full silicidation from such a distributed state, as the full silicidation progresses, an amount of impurities corresponding to the amount introduced into the gate electrode material is carried to the interface region with the gate insulating film.

  In the present invention, the gate electrode material into which impurities are introduced is irradiated with laser, and then the gate electrode material is fully silicided. As a result, impurities can be distributed in the gate electrode material without being limited by the solid solution limit, and a full silicide gate electrode having a work function corresponding to the amount of introduced impurities can be formed. Become. Therefore, a semiconductor device including a full silicide gate electrode having a desired work function can be realized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating the principle of a method for forming a full silicide gate electrode.
First, polysilicon, which is a gate electrode material, is formed on a semiconductor substrate with a predetermined film thickness via a gate insulating film (step S1). As will be described later, this polysilicon is finally fully silicided to form a full silicide gate electrode.

  Then, an impurity such as boron or arsenic is ion-implanted into the formed polysilicon under predetermined conditions so that a full silicide gate electrode having a target work function can be finally obtained (step S2).

  In this way, a laser having a predetermined power is irradiated to the polysilicon in which predetermined impurities are ion-implanted under a predetermined condition (step S3). By this laser irradiation, the polysilicon is melted in whole or in part. Alternatively, the polysilicon is heated at a high temperature in a short time by this laser irradiation.

  After the laser irradiation, a predetermined metal, for example, a metal such as nickel (Ni), is deposited on the polysilicon with a predetermined film thickness, and RTA is performed under a predetermined condition to cause the polysilicon and the metal to react with each other. Is fully silicided from the surface toward the inside (step S4). The impurities introduced into the polysilicon are carried to the interface region with the gate insulating film as the full silicidation proceeds. Finally, unreacted metal is removed to obtain a full silicide gate electrode having a predetermined work function.

  According to such a forming method, the polysilicon into which impurities are ion-implanted is irradiated with a laser to melt or heat the polysilicon. Then, after such laser irradiation, the polysilicon is fully silicided. If RTA is performed on polysilicon after ion implantation as in the prior art, even if a large amount of impurities are implanted into the polysilicon, the impurities are still in contact with the gate insulating film even after full silicidation due to the solid solution limit. It could not be distributed at a high concentration in the region (FIGS. 15 and 16). However, by melting or heating the polysilicon after ion implantation in this way, it becomes possible to distribute impurities in the polysilicon without being restricted by the solid solution limit.

  Here, the results of SIMS measurement of a sample in which boron, which is a p-type impurity, is ion-implanted into polysilicon formed on a silicon substrate via a gate insulating film and laser irradiation is performed are shown.

FIG. 2 is a diagram showing the relationship between the sample depth and the boron concentration after laser irradiation.
FIG. 2 shows that after ion implantation of boron under conditions of acceleration energy 5 keV, dose amount 1 × 10 ¹⁵ cm ⁻² , 5 × 10 ¹⁵ cm ⁻² , and 1 × 10 ¹⁶ cm ⁻² , 1500 mJ / cm ² . The relationship between the depth of the sample irradiated with laser with power and the boron concentration is shown.

As shown in FIG. 2, as the dose of boron into the polysilicon is increased to 1 × 10 ¹⁵ cm ⁻² , 5 × 10 ¹⁵ cm ⁻² , and 1 × 10 ¹⁶ cm ⁻² , the boron in the polysilicon is increased. The concentration tends to increase. Here, this tendency is particularly noticeable in the region on the sample surface side. The same tendency was observed for n-type impurities such as arsenic.

  Thus, by melting or heating the polysilicon after ion implantation by laser irradiation, it becomes possible to distribute impurities in the polysilicon without being limited by the solid solution limit. Therefore, if polysilicon is fully silicided from such impurity concentration distribution, the impurity concentration in the interface region with the gate insulating film is increased linearly depending on the amount of impurity introduced into the polysilicon. Is possible. In addition, it is possible to form a full silicide gate electrode in which impurities are piled up at a higher concentration than in the prior art in the interface region with the gate insulating film.

  By using such a method, the work function of the full silicide gate electrode can be controlled by the amount of impurities introduced into the polysilicon. As a result, it is possible to form full silicide gate electrodes having various work functions depending on the amount of introduced impurities, and a high-speed device using the same can be realized.

  In the above description of the formation method, the case where polysilicon is used as the gate electrode material has been described as an example. However, amorphous silicon is used instead of polysilicon, and the above-described ion implantation is performed on amorphous silicon. Laser irradiation and full silicidation may be performed. In this case, the same effect as that of the above polysilicon can be obtained.

In forming the full silicide gate electrode, the semiconductor substrate may be a silicon substrate, germanium (Ge) substrate, silicon germanium (SiGe) substrate, SOI (Silicon On Insulator) substrate, GOI (Germanium On Insulator) substrate, SGOI. A (Silicon Germanium On Insulator) substrate or the like can be used. The gate insulating film may be a silicon oxide (SiO ₂ ) film, a laminated film of an oxide film and a nitride film (ON film), a hafnium (Hf) insulating film, or the like (in this case also, Here, it is described as MOS for convenience.)

Various elements or molecules can be used as impurities introduced into polysilicon or the like. As the p-type impurity, for example, in addition to the above boron, indium (In), aluminum (Al), gallium (Ga), boron difluoride (BF ₂ ), or a combination thereof can be used. As the n-type impurity, for example, phosphorus (P), antimony (Sb), or a combination thereof can be used in addition to the above arsenic.

  In general, impurities such as indium and antimony have a low solid solution limit in polysilicon and the like, but according to the above formation method, impurities are distributed in polysilicon and the like without being limited by the solid solution limit by laser irradiation. Such impurities can be piled up at a high concentration in the interface region with the gate insulating film.

The work function can also be controlled by introducing nitrogen (N) into polysilicon or the like.
When polysilicon or the like is melted by laser irradiation, it is not always necessary to melt the whole polysilicon or the like, and may be partially melted, for example, to a certain depth from the surface.

  Moreover, even if it does not go to the point where it melts, the process of the high solid solution limit is possible by the high temperature heating by laser irradiation. Further, since the laser can perform such a high-temperature treatment in a very short time compared to the RTA, impurities inside the polysilicon or the like penetrate through the gate insulating film by the high-temperature treatment and the semiconductor substrate (or its semiconductor layer). It is possible to effectively avoid situations such as reaching the above.

  The laser irradiation conditions should be determined in consideration of the type of film to be irradiated, the film quality of the film, the type of gate insulating film that is the base of the film, the application of the device to which the full silicide gate electrode is applied, the required characteristics, etc. Optimum conditions are set such that impurities of a predetermined concentration exist in the interface region between the silicide gate electrode and the gate insulating film and the gate insulating film is not damaged.

  In addition, if necessary, after irradiating the polysilicon or the like after introducing the impurity with laser, RTA is performed to further diffuse the impurity, and then the polysilicon or the like can be fully silicided. By further performing RTA after laser irradiation in this way, it becomes possible to increase the probability of existence of impurities in the interface region between polysilicon and the like before full silicidation and the gate insulating film, and the interface region after full silicidation. It is possible to increase the concentration of the impurities in.

Hereinafter, the case where the above-described method for forming a full silicide gate electrode is applied to the formation of a MOS transistor will be described in detail.
First, a first embodiment will be described with reference to FIGS.

  3 is a schematic cross-sectional view of the main part of the polysilicon forming process, FIG. 4 is a schematic cross-sectional view of the main part of the source / drain / extension region forming process, and FIG. 5 is a schematic cross-sectional view of the main part of the side wall forming process. 6 is a schematic cross-sectional view of an essential part of an ion implantation process of polysilicon and source / drain regions, FIG. 7 is a schematic cross-sectional view of an essential part of a laser irradiation process, and FIG. 8 is a schematic cross-sectional view of an essential part of an interlayer insulating film forming process. FIG. 10 is a schematic cross-sectional view of the main part of the nickel film deposition process, FIG. 10 is a schematic cross-sectional view of the main part of the full silicidation process, and FIG. 11 is a schematic cross-sectional view of the main part of the unreacted nickel film removal process.

  First, as shown in FIG. 3, after an element isolation region 2 is formed on a silicon substrate 1 by using, for example, an STI (Shallow Trench Isolation) method, a gate insulating film 3 such as an ON film is formed on the entire surface with a predetermined film thickness. Then, polysilicon 4 is deposited to a thickness of about 100 nm using a CVD (Chemical Vapor Deposition) method or the like. Then, the polysilicon 4 and the gate insulating film 3 are patterned into a predetermined shape using lithography and RIE (Reactive Ion Etching). Note that a LOCOS (LOCal Oxidation of Silicon) method may be used to form the element isolation region 2.

  Next, as shown in FIG. 4, a predetermined impurity is ion-implanted under a predetermined condition to form a source / drain / extension region 5 in the silicon substrate 1 on both sides of the patterned polysilicon 4.

Next, an insulating film such as silicon oxide is formed on the entire surface and etched back to form sidewalls 6 on the sidewalls of the polysilicon 4 as shown in FIG.
Next, as shown in FIG. 6, impurities such as boron and arsenic are ion-implanted into the polysilicon 4 and the silicon substrate 1 to introduce impurities into the polysilicon 4 in an amount capable of obtaining a desired work function, and silicon. Source / drain regions 7 are formed on the substrate 1. For example, in the case of boron, ion implantation is performed under the conditions of an acceleration energy of 3 keV and a dose of 1 × 10 ¹⁶ cm ⁻² . In the case of arsenic, ion implantation is performed under the conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁶ cm ⁻² .

Then, after this ion implantation, as shown in FIG. 7, the polysilicon 4 is irradiated with a laser to melt the polysilicon 4. The laser power is, for example, 2500 mJ / cm ² . By this laser irradiation, the impurities introduced into the polysilicon 4 are distributed in the polysilicon 4 without being restricted by the solid solution limit.

  After the laser irradiation, as shown in FIG. 8, first, the entire surface is covered with an interlayer insulating film 8 having a film thickness of about 150 nm, and then the interlayer insulating film 8 is subjected to CMP (Chemical Mechanical Polishing) until the polysilicon 4 is exposed. Flatten. Thereafter, treatment with dilute hydrofluoric acid (HF) is performed, and an oxide film (not shown) formed on the exposed surface of the polysilicon 4 is removed.

  Thereafter, as shown in FIG. 9, a nickel film 9 is deposited on the entire surface with a film thickness of about 60 nm. Then, RTA is performed at a temperature of 400 ° C. for about 60 seconds to fully silicide the polysilicon 4 to form a full silicide gate electrode 10 as shown in FIG.

Finally, it is immersed in a sulfuric acid-based solution such as a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) to remove the unreacted nickel film 9 remaining after the formation of the full silicide gate electrode 10. Then, a MOS transistor having a full silicide gate electrode 10 as shown in FIG. 11 is formed.

Thereafter, a device including such a MOS transistor may be completed through processes such as interlayer insulating film formation, contact formation, and wiring formation according to a conventional method.
According to the method shown in the first embodiment, the ion implantation for controlling the work function for the polysilicon 4 is performed in combination with the ion implantation for forming the source / drain regions 7 (FIG. 6). ), It is possible to efficiently form a MOS transistor including the full silicide gate electrode 10 having a predetermined work function. However, in the case of this method, when setting the ion implantation conditions, the amount of impurities introduced into the polysilicon 4 by this ion implantation is substantially the same as the amount of impurities introduced into the source / drain region 7. Keep in mind.

  When a CMOS device is formed by applying the method shown in the first embodiment, first, in the step shown in FIG. 3, the polysilicon 4 is formed in the nMOS formation region and the pMOS formation region, respectively. A gate pattern is formed. In the ion implantation process shown in FIGS. 4 and 6, for example, the nMOS formation region is masked and predetermined ion implantation is performed in the pMOS formation region, and then the pMOS formation region is masked and predetermined in the nMOS formation region. Ion implantation may be performed.

  If the nickel film 9 as shown in FIG. 9 is formed without forming the interlayer insulating film 8 as shown in FIG. 8, the source / drain is formed together with the formation of the full silicide gate electrode 10. It is also possible to silicide the region 7. However, in this case, it is desirable to change the conditions appropriately such as reducing the thickness of the polysilicon 4 so that the source / drain region 7 is not silicided deeply and junction leakage occurs.

  The silicidation of the source / drain region 7 can also be performed in a separate process from the full silicide gate electrode 10. For example, an insulating film or the like is formed on the polysilicon 4 at the stage of silicidation of the source / drain region 7. If formed, the source / drain region 7 can be selectively silicided without siliciding the polysilicon 4. Thereafter, as shown in FIGS. 8 to 11, the polysilicon 4 may be fully silicided. The insulating film or the like formed on the polysilicon 4 for silicidation of the source / drain regions 7 may be removed together when the interlayer insulating film 8 shown in FIG. 8 is planarized.

Next, a second embodiment will be described with reference to FIGS. 12 to 14 and FIGS. 3 to 6 and FIGS. 8 to 11 described above.
Here, FIG. 12 is a schematic cross-sectional view of the main part of the polysilicon deposition process, FIG. 13 is a schematic cross-sectional view of the main part of the ion implantation process of polysilicon, and FIG. 14 is a schematic cross-sectional view of the main part of the laser irradiation process. 12 to 14, the same elements as those shown in FIGS. 3 to 11 are denoted by the same reference numerals, and detailed description thereof is omitted.

  First, as shown in FIG. 12, after an element isolation region 2 is formed on a silicon substrate 1, a gate insulating film 3 is formed on the entire surface with a predetermined thickness, and polysilicon 4 is deposited thereon with a thickness of about 100 nm. To do.

Next, as shown in FIG. 13, impurities such as boron and arsenic are introduced into the deposited polysilicon 4 by ion implantation so as to obtain a target work function.
Then, after this ion implantation, as shown in FIG. 14, the entire surface of the polysilicon 4 is irradiated with a laser to melt the polysilicon 4. The laser power is, for example, 2500 mJ / cm ² as in the first embodiment.

  Thereafter, as described in the first embodiment, first, as shown in FIG. 3, polysilicon 4 (impurities for work function control have already been introduced in this second embodiment). ) And the gate insulating film 3 are patterned into a predetermined shape, and then ion implantation is performed to form source / drain / extension regions 5 as shown in FIG. 4, and polysilicon is formed as shown in FIG. Side walls 6 are formed on the side walls 4. In the ion implantation of the source / drain / extension region 5, ion implantation into the polysilicon 4 is also performed together with the source / drain / extension region 5, which will be described later.

  Then, as shown in FIG. 6, ion implantation is performed to form source / drain regions 7. In this ion implantation, the ion implantation into the polysilicon 4 is performed together with the ion implantation into the source / drain region 7, which will be described later. After the formation of the source / drain region 7, the impurity is activated by RTA under a predetermined condition.

  Thereafter, as in the first embodiment, first, the interlayer insulating film 8 is formed as shown in FIG. 8, and then the nickel film 9 is formed as shown in FIG. As shown in FIG. 2, a full silicide gate electrode 10 is formed.

Thereafter, a semiconductor device including such a MOS transistor may be completed through steps such as interlayer insulation film formation, contact formation, and wiring formation according to a conventional method.
In the method as shown in the second embodiment, ion implantation for work function control and laser irradiation thereof are performed on the polysilicon 4 before gate patterning, and then the gate patterning of the polysilicon 4 is performed. (FIGS. 12 to 14 and FIG. 3). Therefore, the laser irradiation process for the polysilicon 4 can be easily performed.

  Further, in the second embodiment, unlike the first embodiment, after ion implantation and laser irradiation are performed on the polysilicon 4, the source / drain regions 7 are formed separately from the ion implantation. For ion implantation. Therefore, the amount of impurities introduced into the polysilicon 4 and the amount of impurities introduced into the source / drain regions 7 can be set independently. Also, the types of impurities to be introduced can be set independently.

  As described above, in the ion implantation for forming the source / drain region 7 and the ion implantation for forming the source / drain / extension region 5 performed before the source / drain region 7, the amount required for work function control has already been obtained. Ions are also implanted into the polysilicon 4 into which the impurities are introduced. In setting the ion implantation conditions at the time of forming the source / drain / extension region 5 and the source / drain region 7, the dose amount thereof does not greatly change the amount of impurities in the polysilicon 4 as a result of the ion implantation. For example, the work function of the full silicide gate electrode 10 is set to a value that does not greatly change. Alternatively, the amount of impurities introduced into the polysilicon 4 may be set in advance in consideration of the amount of impurities introduced by ion implantation of the source / drain / extension region 5 and the source / drain region 7. .

  When the CMOS device is formed by applying the method shown in the second embodiment, the ion implantation process for the polysilicon 4 shown in FIG. 13 and the source / drain / extension region 5 shown in FIG. In each step of the ion implantation step of FIG. 6 and the ion implantation step of the source / drain region 7 shown in FIG. The predetermined ion implantation may be performed on the region, and then the pMOS formation region may be masked to perform the predetermined ion implantation on the nMOS formation region.

  Further, when a CMOS device is formed by applying the method shown in the second embodiment, the gate patterning is performed for the nMOS formation region and the pMOS formation region in the gate patterning step of the polysilicon 4 shown in FIG. I do. This is because the etching rate of the polysilicon 4 differs depending on whether the impurity introduced into the polysilicon 4 by ion implantation is n-type or p-type. Therefore, in the case of the second embodiment, it should be noted that two masks for nMOS and pMOS are required for gate patterning.

  In the case of the second embodiment as well, as described in the first embodiment, the source and source are formed together with the formation of the full silicide gate electrode 10 or separately from the formation of the full silicide gate electrode 10. The drain region 7 can be silicided.

  In the above description, the case where a silicon material such as polysilicon or amorphous silicon is used as the gate electrode material is described. However, the above formation principle and method are based on the case where germanium or silicon germanium is used as the gate electrode material. The same applies to the above.

(Additional remark 1) In the manufacturing method of the semiconductor device which has a full silicide gate electrode,
Forming a gate electrode material on a semiconductor substrate via a gate insulating film;
Introducing impurities into the formed gate electrode material;
Irradiating a laser to fully silicide the gate electrode material into which the impurity has been introduced;
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 2) In the step of irradiating the laser to fully silicide the gate electrode material,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the laser is irradiated under a condition that the gate electrode material melts when the laser is irradiated.

(Appendix 3) When irradiating the laser under the condition that the gate electrode material melts when irradiated with the laser,
3. The method of manufacturing a semiconductor device according to claim 2, wherein the laser is irradiated under a condition that the surface layer of the gate electrode material melts when the laser is irradiated.

(Supplementary Note 4) In the step of irradiating the laser to fully silicide the gate electrode material,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the laser is irradiated under a condition that the gate electrode material is not melted when the laser is irradiated.

(Supplementary Note 5) After the step of irradiating the laser to fully silicide the gate electrode material,
The method for manufacturing a semiconductor device according to claim 1, further comprising an annealing step of annealing the gate electrode material.

(Supplementary Note 6) In the step of forming the gate electrode material,
Depositing and patterning the gate electrode material on the gate insulating film to form the gate electrode material;
In the step of introducing impurities into the gate electrode material,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is introduced into the patterned gate electrode material, and the impurity is introduced into the semiconductor substrate on both sides of the gate electrode material.

(Supplementary Note 7) After the step of irradiating the laser to fully silicide the gate electrode material,
Patterning the gate electrode material;
Introducing the same or different impurity as the impurity introduced into the gate electrode material into the semiconductor substrate on both sides of the patterned gate electrode material;
The method for manufacturing a semiconductor device according to appendix 1, wherein:

(Additional remark 8) The said gate electrode material is a polysilicon or an amorphous silicon, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Additional remark 9) The said impurity is a p-type impurity or an n-type impurity, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.

It is principle explanatory drawing of the formation method of a full silicide gate electrode. It is a figure which shows the relationship between the sample depth after a laser irradiation, and a boron density | concentration. It is a principal part cross-sectional schematic diagram of a polysilicon formation process. It is a principal part cross-sectional schematic diagram of a source-drain extension region formation process. It is a principal part cross-sectional schematic diagram of a side wall formation process. It is a principal part cross-sectional schematic diagram of the ion implantation process of polysilicon and a source / drain region. It is a principal part cross-sectional schematic diagram of the laser irradiation process (the 1). It is a principal part cross-sectional schematic diagram of an interlayer insulation film formation process. It is a principal part cross-sectional schematic diagram of a nickel film deposition process. It is a principal part cross-sectional schematic diagram of a full silicidation process. It is a principal part cross-sectional schematic diagram of an unreacted nickel film removal process. It is a principal part cross-sectional schematic diagram of a polysilicon deposition process. It is a principal part cross-sectional schematic diagram of the ion implantation process of polysilicon. It is a principal part cross-sectional schematic diagram of the laser irradiation process (the 2). It is a figure which shows the relationship between the sample depth after RTA, and a boron concentration. It is a figure which shows the relationship between the dose amount of boron, and a flat band voltage. It is a figure which shows the relationship between the sample depth after full silicidation, and a boron concentration.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation region 3 Gate insulating film 4 Polysilicon 5 Source / drain / extension region 6 Side wall 7 Source / drain region 8 Interlayer insulating film 9 Nickel film 10 Full silicide gate electrode

Claims (5)

In a method for manufacturing a semiconductor device having a full silicide gate electrode,
Forming a gate electrode material on a semiconductor substrate via a gate insulating film;
Introducing impurities into the formed gate electrode material;
Irradiating a laser to fully silicide the gate electrode material into which the impurity has been introduced;
A method for manufacturing a semiconductor device, comprising: In the step of irradiating the laser to fully silicide the gate electrode material,
The method of manufacturing a semiconductor device according to claim 1, wherein the laser is irradiated under a condition that the gate electrode material melts when the laser is irradiated. In the step of irradiating the laser to fully silicide the gate electrode material,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the laser is irradiated under a condition that the gate electrode material does not melt when the laser is irradiated. In the step of forming the gate electrode material,
Depositing and patterning the gate electrode material on the gate insulating film to form the gate electrode material;
In the step of introducing impurities into the gate electrode material,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is introduced into the patterned gate electrode material, and the impurity is introduced into the semiconductor substrate on both sides of the gate electrode material. After the step of irradiating the laser to fully silicide the gate electrode material,
Patterning the gate electrode material;
Introducing the same or different impurity as the impurity introduced into the gate electrode material into the semiconductor substrate on both sides of the patterned gate electrode material;
The method of manufacturing a semiconductor device according to claim 1, wherein:

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