JP2007325077A - Data receiver and data receiving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data receiver and data receiving method in which preferential processing data with a great limitation in a data delay amount can be preferentially repeated without being affected by a stored processing SN. <P>SOLUTION: The data receiver judges whether or not reception data are normally received (S1) in a reception timing generated by a reception timing generating means, extracts and analyzes a sequence number SN and priority flag information from header information of the reception data. Based on a judgement result of whether the reception data are normally received and the SN and priority flag information, a processing SN that is the SN of reception data to be next repeated is stored (S3-S5) and when the judgement result of whether the reception data are normally received shows that the data are normally received (S1) and the reception data are judged as preferential processing data (S2), processing is performed to preferentially repeat the reception data judged as the preferential processing data without being affected by the stored processing SN (S7) and the preferentially processed SN is stored (S8). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data receiving apparatus and a data receiving method in a network system such as a wireless or high-speed PLC (Power Line Communication), and more particularly to a data receiving apparatus and a data receiving method for performing priority processing on specific received data. It is.

  In a network system such as a wireless or high-speed PLC, the characteristics of the transmission path change from moment to moment. For this reason, generally, when an error occurs in a transmission packet on the transmission path, retransmission of the packet at the MAC (Media Access Control) layer level is performed. In addition, in a network system such as a wireless or high-speed PLC, a method of transmitting data using a TDMA (Time Division Multiple Access) method for transmitting and receiving data requiring real-time performance such as video or audio has been introduced. It's getting on. Specifically, for example, there is HiSWANA (ARIB STD-T70 1.0 version) standardized by ARIB (Association of Radio Industries and Businesses).

  Hereinafter, an outline of the TDMA system adopted in the HiSWANA standard will be briefly described. In the TDMA system adopted in the HiSWANA standard, each terminal in the network is managed by one terminal called a management terminal. The management terminal broadcasts packet data called a “Beacon signal” (hereinafter referred to as “BCH”) at a predetermined cycle (2 ms cycle in the HiSWANA standard) in order to manage time synchronization of the entire network.

  When each terminal arranged in the network receives the BCH, it resets the reference time information in the terminal and starts preparation for receiving various control packets transmitted from the management terminal. After sending the BCH, the management terminal sends packet data for network system control (hereinafter referred to as “FCH”) including the data transmission schedule of each terminal connected to the network to each terminal connected to the network. Broadcast. Data transmission and reception schedules (data transmission / reception slot information (transmission / reception start timing information, data transmission / reception time information), etc.) of each terminal connected to the network are added to the FCH and transmitted. When each terminal receives the FCH, each terminal detects the timing at which the terminal receives data and the timing at which the terminal transmits data.

  Following the FCH transmission, the management terminal transmits a transmission request reception notification (hereinafter referred to as “ACH”) to the terminal. When transmission of the BCH, FCH, and ACH packet data from the management terminal is completed, each terminal starts receiving and transmitting packet data based on the schedule notified on the FCH. Hereinafter, a period during which data is transmitted and received between the terminals is referred to as “TCH”. In the TDMA scheme, the management terminal schedules data transmission slots only for terminals having data to be transmitted. Therefore, the terminal having the data to be transmitted needs to request the management terminal to allocate a slot for transmitting the data of the own terminal. In the TDMA system adopted in the HiSWANA standard, since a transmission request is accepted from each terminal, the transmission slot request request (bandwidth allocation request) from each terminal at the end of one Beacon period (hereinafter referred to as “one frame”). CSMA (Carrier Sense Multiple Access) period (hereinafter referred to as “RCH period”) is prepared. The management terminal notifies the terminal that has received the transmission slot request request during the RCH period that the bandwidth allocation request has been received on the ACH within the next Beacon cycle.

  Hereinafter, a data retransmission control method in a conventional data receiving apparatus will be described based on an example in which the TDMA scheme adopted in the HiSWANA standard is applied to, for example, a high-speed PLC. In data communication using a power line, the characteristics of the transmission path change from moment to moment according to the operating conditions of the equipment connected to the outlet. Therefore, in the conventional high-speed PLC modem, the modulation method applied to the data sent to the transmission path is switched in accordance with the transmission path characteristics that change every moment. In the high-speed PLC modem, similar to a wireless LAN (Local Area Network), when a received packet is lost due to an error mixed in a transmission path, retransmission control is performed in the MAC layer. At this time, in consideration of transmission efficiency as a high-speed PLC system, SR (Selective Repeat) or Go-Back-N retransmission control method is used as the retransmission control method. In the retransmission control method (Stop & Wait) adopted in wireless LAN, the terminal that has received the data sends an ACK packet (a packet notifying that the data has been successfully received) to the transmitting terminal immediately after reception. To do. In the case of a wireless LAN, a maximum 64 point OFDM (Orthogonal Frequency Division Multiplex) modulation scheme is adopted as a modulation scheme in the physical layer, and the symbol length is short. On the other hand, the modulation scheme in the physical layer used for high-speed PLC or the like employs a maximum of 1024 points OFDM modulation scheme and has a long symbol length. Therefore, in the high-speed PLC, it takes time to demodulate received data in the physical layer when data is received as compared with the wireless LAN. Therefore, in a high-speed PLC adopting the TDMA system, in order to efficiently perform data communication, the management terminal determines a transmission / reception schedule in consideration of the data processing time in the physical layer. Therefore, in a high-speed PLC that employs the TDMA scheme, the receiving terminal does not always send out an ACK packet immediately after reception.

  Specifically, when data is transmitted in multiple times to the same terminal within one frame (when transmitting a plurality of MAC frame data), after a plurality of MAC frame data is input to the receiving terminal, Whether the received MAC frame data is normally received or not normally received is collectively notified from the receiving terminal to the transmitting terminal using one ACK packet. On the other hand, when the retransmission method (Stop & Wait method) employed in the wireless LAN is used in the high-speed PLC as described above, the transmission packet data and the transmission packet data are created in consideration of the demodulation time of the reception data in the physical layer. It is necessary to increase the interval between ACK packet data, and the data transmission efficiency decreases. For example, when the OFDM symbol length is 50 μs and the processing time in the physical layer requires 4 OFDM symbols, the interval between the transmission packet data and the ACK packet data needs to be 200 μs or more.

  Therefore, for example, in a high-speed PLC that employs the TDMA scheme, the SR scheme or the Go-Back-N scheme is used as the retransmission control scheme in order to increase the efficiency of transmission data. Patent Documents 1 and 2 describe the SR method and the Go-Back-N method. Further, in Patent Document 3, a terminal that has received data notifies the transmitting terminal of whether or not the data has been normally received using an ACK / NACK frame (Acknowledgement frame or Negative Acknowledgment frame), and the transmitting terminal receives the data. Describes a method of performing retransmission control using the received ACK / NACK frame.

  In addition, when data that requires real-time performance such as voice or video is transmitted and received using a network using a wireless LAN or a high-speed PLC, retransmission control in the MAC layer may not be performed. For example, in a high-speed PLC network that employs the TDMA system, as described above, a delay of one frame or more may occur until an ACK packet is received. In particular, a telephone-related application such as VoIP (Voice over IP) needs to minimize the amount of packet delay. In the MAC control method using the TDMA method adopted in the HiSWANA standard or the like, when the transmitting terminal transmits a retransmission packet after receiving a NACK frame, the transmission timing is delayed by at least about one frame from the reception of the NACK frame. Specifically, since the bandwidth allocation for the retransmission packet is after the next frame after receiving the NACK packet, the transmission timing is delayed by about one frame. In particular, as described above, in high-speed PLC, unlike OFDM, the length of 1 OFDM symbol is long. Therefore, considering the data transmission efficiency, the data length of 1 frame is very long, for example, 20 ms (HiSWANA standard). About 10 times the case). Therefore, when an error occurs in a MAC frame in which VoIP data is transmitted and retransmission control is performed, the packet is delayed by about 2 frames (about 40 ms). Therefore, even if the retransmission control in the MAC layer is used in the high-speed PLC, the retransmission packet is delayed by about 2 frames, and therefore, there is a case where the retransmission control is not performed for data such as VoIP with severe restrictions on the data delay amount. Patent Document 4 describes a control method in the case where frame data that does not perform delivery confirmation (transmission of an ACK / NACK frame) such as VoIP exists in the transmission data.

Japanese Patent Laid-Open No. 10-247901 JP 11-215192 A JP 2001-69156 A Japanese Patent Laid-Open No. 2005-64594

  However, the retransmission control method (SR method or Go-Back-N method) described in Patent Documents 1 and 2 is implemented using the delivery confirmation control method using the ACK / NACK frame disclosed in Patent Document 3 above. In this case, when a certain frame cannot be received due to an error that has occurred in the transmission path, SR receiving control or Go-Back-N retransmission control is performed at the receiving terminal. At that time, if the receiving terminal implements the SR retransmission control method after the frame that could not be received due to an error, the receiving terminal's frame is received until the error frame is normally received by the retransmission control. Stored in memory. Alternatively, when the receiving terminal implements the Go-Back-N retransmission control method, all of the error frames are discarded until they are normally received by the retransmission control. The processing delay caused by a frame in which an error has occurred in the normally received frame is a problem for data such as VoIP that has a large data delay restriction (requires real-time property).

  Accordingly, the present invention has been made to solve the above-described problems of the prior art, and the purpose of the present invention is to correct the error after the received data in which the error has occurred when an error occurs in the received data. It is an object of the present invention to provide a data receiving apparatus and a data receiving method capable of preferentially performing processing of received data with a large restriction on the amount of data delay and transferring the data to an upper layer.

  The data receiving apparatus of the present invention is connected to a network including a management terminal and needs to preferentially pass the sequence number indicating the continuity of data transmitted through the network and the data received on the receiving side to the upper layer. A data receiving apparatus that receives and relays data to which header information including priority information indicating whether or not certain priority processing data is added through the network, and is a schedule output from the management terminal Based on the reception timing generation means for generating the reception timing of the reception data, the data reception determination means for determining whether or not the reception data is normally received at the reception timing, and the header information at the reception timing. Receiving sequence analysis means for extracting and analyzing the sequence number and the priority information from The processing sequence number indicating the sequence number of the reception data to be relayed next is stored based on the determination result by the data reception determination unit and the analysis result of the sequence number and the priority information by the reception header analysis unit. Receiving data control means, wherein the received data control means determines that the received data is preferentially processed data when the judgment result by the data reception judging means is a judgment result that the received data has been normally received. The received data determined as the priority processing data without being affected by the stored processing sequence number when the received data is determined as the priority processing data. It is characterized in that processing for preferentially relaying is performed.

  In addition, the data transmission / reception method of the present invention is connected to a network including a management terminal, and the sequence number indicating the continuity of data transmitted through the network and the data received on the receiving side are preferentially sent to the upper layer. A data reception method for receiving and relaying data with header information including priority information indicating whether or not priority processing data needs to be passed through the network, and is output from the management terminal Generating a reception timing of received data based on a schedule, a step of determining whether the reception data is normally received at the reception timing, and the sequence number from the header information at the reception timing. And a step of extracting and analyzing the priority information, and whether or not the reception is normal A step of storing a processing sequence number indicating a sequence number of received data to be relayed next based on a disconnection result and an analysis result of the sequence number and the priority information; When the determination result is a result that the received data is normally received, it is determined whether the received data is priority processing data, and when the received data is determined to be priority processing data, And a step of preferentially relaying the received data determined to be the priority processing data without being influenced by the stored processing sequence number.

  If the data receiving apparatus or the data receiving method of the present invention is used, if there is data that could not be received normally and then priority processing data with a large data delay restriction is received normally, the priority processing data is processed without delay. The effect that it can be obtained.

Embodiment 1 FIG.
FIG. 1 is a diagram schematically showing a configuration of a high-speed PLC network system that implements a data reception method according to Embodiment 1 of the present invention. In FIG. 1, 1 is a management terminal for managing the entire high-speed PLC network, 2 is an outlet for connecting the management terminal 1 and the power line 9, 3 is a terminal A connected to the PLC network system, and 4 is a terminal A (that is, Outlet for connecting the power line to the terminal 3) 5 is a terminal B connected to the PLC network system, 6 is a power outlet connecting the terminal B (that is, the terminal 5) to the power line, and 7 is connected to the PLC network system Terminals C and 8 are outlets for connecting the terminal C (that is, the terminal 7) and the power line. In FIG. 1, each terminal is provided with two types of codes A, B, and C for distinguishing the terminals and codes 3, 5, and 7 as the configuration of the PLC network system. In the following description, symbols A, B, and C are used. As shown in FIG. 1, in the first embodiment, the management terminal 1, terminal A, terminal B, and terminal C constitute a high-speed PLC network system. The configuration of the high-speed PLC network system shown in FIG. 1 shows a case where a high-speed PLC is used as an example of a system configuration to which the data receiving method and data receiving apparatus of the present invention can be applied. The receiving method and the data receiving apparatus can be applied to other systems such as a high-speed PLC network system having other configurations, a network system using a wireless LAN, and a network system using Ethernet (registered trademark).

  Next, the operation of the management terminal 1 in the high-speed PLC network system will be described using FIG. In the first embodiment, the case where the TDMA method used in the HiSWANA standard described in the conventional example is adopted as the MAC control method will be described as an example. First, the management terminal 1 broadcasts a BCH (Beacon signal) at a predetermined cycle in order to manage time synchronization of the entire network system. After the BCH transmission, the management terminal 1 broadcasts data reception and data transmission timing information (FCH) of each terminal in the high-speed PLC network system. When the management terminal 1 receives a transmission slot request request (RCH) output from each terminal in the previous frame after transmitting the FCH, the management terminal 1 notifies the transmitting terminal that has transmitted the RCH that the RCH has been normally received. A request reception notification (ACH) is output.

  After the ACH transmission, the management terminal 1, the terminal A, the terminal B, and the terminal C perform data transmission / reception between the terminals based on the schedule transmitted on the FCH. Details of the FCH will be described later (described with reference to FIGS. 6 and 7). When transmission / reception of data based on the schedule in the FCH is completed, each terminal, when having transmission data, in response to the management terminal 1 during the RCH period (CSMA period for receiving a transmission slot request request from each terminal). Output a bandwidth allocation request. Details of the transmission / reception timing of the BCH, FCH, ACH, and RCH signals using the TDMA method will be described later.

  Next, the operation of each terminal will be described. Each terminal, when receiving the BCH signal output from the management terminal 1, corrects the reference time in the terminal based on the reception timing. After performing the reference time correction using the BCH, each terminal determines the data transmission timing and data reception timing of each terminal based on the FCH output from the management terminal 1, a MAC unit (not shown), and a modem unit. (Not shown). Upon receiving notification of data transmission and reception timing, the modem unit starts preparation for data transmission and reception based on the reference time information corrected by the BCH. Specifically, in the case of data reception, when the reception time based on the FCH is reached, the high-speed PLC data demodulation circuit unit (not shown) starts the data reception operation, and preamble information added in advance to the head of the data. Perform detection. When the preamble information is detected at a predetermined timing, the high-speed PLC data demodulation circuit unit detects the beginning of the received data based on the detected preamble information, demodulates the received data, and outputs the demodulated data to the MAC unit . The detailed operation of the MAC unit will be described later. On the other hand, when the preamble cannot be detected at a predetermined timing, the high-speed PLC data demodulation circuit unit notifies the MAC unit that it could not be received.

  In the case of data transmission, when the transmission time based on FCH approaches, the MAC unit starts generating transmission data. When the generation of transmission data is completed in the MAC unit, the MAC unit outputs the transmission data to a high-speed PLC data modulation circuit unit (not shown) at a predetermined timing. The high-speed PLC data modulation circuit unit modulates transmission data output from the MAC unit, adds preamble information, and transmits the transmission data to the power line 9 at a predetermined timing. The details of the transmission operation of the MAC unit will be described later (explained using FIG. 8).

  Next, the configuration of the high-speed PLC terminal will be described with reference to FIGS. FIG. 2 is a block diagram schematically showing a configuration of a data transmitting / receiving apparatus that can be used as a terminal of the high-speed PLC network system in the first embodiment of the present invention. The data receiving apparatus and data receiving method of the present invention can be applied to the data transmitting / receiving apparatus shown in FIG.

  In FIG. 2, 10 is a data transmission / reception apparatus having a relay function according to an embodiment of the present invention, 11 is a CPU, 12 is an Ethernet interface circuit, 13 is Ethernet frame data input from the Ethernet interface circuit 12, and Ethernet interface circuit. 12 is a bridge interface circuit that bridges Ethernet frame data output to 12, Ethernet frame data output to the PLC modem circuit 15, and Ethernet frame data input from the PLC modem circuit 15. In general, in the high-speed PLC network, the concept of a logical port is used for each terminal connected to the power line 9, and the bridge interface circuit 13 has destinations (the management terminal 1, terminal A, terminal B, and terminal in FIG. 1). Data is distributed every C) and queued in the bridge memory 14. Specifically, the bridge interface circuit 13 distributes and stores the Ethernet frame data input from the Ethernet interface circuit 12 in the bridge memory 14 for each destination. In FIG. 2, 14 is a bridge memory that distributes and stores Ethernet frames input to the bridge interface circuit 13 for each destination, 15 is a PLC modem circuit, and 16 is a MAC frame data that is transmitted via the power line 9. A PLC transmission memory 17 and a PLC reception memory 17 for storing MAC frame data received via the power line 9. In FIG. 2, 18 is a CPU bus, 20 is an input terminal to the Ethernet interface circuit 12, 21 is an output terminal from the Ethernet interface circuit 12, 22 is an output terminal from the PLC modem circuit 15, and 23 is a PLC modem circuit 15. Input terminal to As shown in FIG. 2, the data transmitting / receiving apparatus 10 according to an embodiment of the present invention includes a CPU 11, an Ethernet interface circuit 12, a bridge interface circuit 13, a bridge memory 14, a PLC modem circuit 15, and a PLC transmission memory 16. , And a PLC receiving memory 17.

  FIG. 3 is a block diagram schematically showing a configuration of the PLC modem circuit 15 in the data transmitting / receiving apparatus 10 that can be used as a terminal of the high-speed PLC network system shown in FIG. In FIG. 3, 30 is a PLC transmission control circuit data input terminal, 31 is a PLC reception control circuit data output terminal, and 40 is Ethernet data input from the bridge interface circuit 13 via the PLC transmission control circuit data input terminal. A PLC transmission control circuit for connecting a plurality of PLCs and generating a MAC frame for PLC. It is a reception control circuit. As shown in FIG. 3, the PLC modem circuit 15 according to an embodiment of the present invention includes a PLC transmission control circuit 40 and a PLC reception control circuit 50.

  FIG. 4 is a block diagram schematically showing the configuration of the PLC transmission control circuit 40 shown in FIG. In FIG. 4, 401 is a PLC header generation circuit that generates a MAC header to be added to a PLC frame, 402 is a packet data generation circuit that collects a plurality of Ethernet frame data input from the bridge interface circuit 13 and generates transmission data, 403 Is an encryption circuit that encrypts data output from the packet data generation circuit 402, and 404 is output from the encryption circuit 403 with Beacon frame data and schedule data output from the PLC network control data generation circuit 408 described later. 405 is a PLC header addition circuit for adding a PLC MAC header generated by the PLC header generation circuit 401 to the head of the data output from the selector 404; And data output from the dust adding circuit 405, a selector for switching the data output from the PLC transmission memory control circuit 409 to be described later. In FIG. 4, reference numeral 407 denotes a PLC transmission timing generation circuit that generates a transmission timing of data output from the data transmitting / receiving apparatus 10 to the PLC network. Reference numeral 408 denotes a sequence number added to data to be transmitted, and ACK / NACK necessity flag information. , PLC network control data generation circuit for generating and outputting ACK / NACK information indicating whether or not the previous received data has been normally received, Beacon control data to be added to the Beacon frame, schedule data in one frame, etc., and 409 for retransmission control A PLC transmission memory that generates a write control signal for storing a transmission frame used at times in the PLC transmission memory 16 and generates a read control signal for reading data stored in the PLC transmission memory 16 at the time of retransmission Control circuit 410 is a CRC code adding circuit for adding the CRC code to the PLC frame transmitted (error detection code). As shown in FIG. 4, the PLC transmission control circuit 40 includes a PLC header generation circuit 401, a packet data generation circuit 402, an encryption circuit 403, selectors 404 and 406, a PLC header addition circuit 405, and a PLC transmission timing generation circuit 407. , A PLC network control data generation circuit 408, a PLC transmission memory control circuit 409, and a CRC code addition circuit 410.

  FIG. 5 is a block diagram schematically showing the configuration of the PLC reception control circuit 50 shown in FIG. In FIG. 5, reference numeral 501 denotes a PLC header analysis circuit that separates the MAC header from the received PLC frame and analyzes the contents thereof, and 502 is a received PLC frame based on CRC information added to the received PLC frame at the time of transmission. A CRC decryption circuit 503 detects an error that has occurred, and a decryption circuit 503 decrypts the encrypted data output from the header analysis circuit 501. In FIG. 5, reference numeral 504 denotes a PLC control frame separation circuit that separates schedule information added to the PLC frame, and 505 denotes a PLC control frame that temporarily stores PLC control frame information separated by the PLC control frame separation circuit 504. A data storage circuit. In FIG. 5, 506 reconfigures Ethernet frame data from the data output from the PLC control frame separation circuit 504, generates a control signal to be temporarily stored in the PLC reception memory 17, and outputs it from the CRC decoding circuit 502. The PLC reception memory control circuit for executing the read control of the Ethernet frame data stored in the PLC reception memory 17 based on the error detection result, and 507 indicates the schedule data stored in the PLC control frame data storage circuit 505 as the CPU 11 This is a PLC reception timing generation circuit that generates data reception timing from a PLC that is read via the PLC. As shown in FIG. 5, the PLC reception control circuit 50 includes a PLC header analysis circuit 501, a CRC decryption circuit 502, an encryption / decryption circuit 503, a PLC control frame separation circuit 504, a PLC control frame data storage circuit 505, a PLC reception memory. A control circuit 506 and a PLC reception timing generation circuit 507 are provided. Further, the PLC control frame separation circuit 504, the PLC control frame data storage circuit 505, the PLC reception memory control circuit 506, and the CPU 11 determine whether or not the reception data is priority processing data, and the reception data is priority processing data. The received data control means is configured to perform the process (S7) of preferentially relaying the received data determined to be the priority processing data without being influenced by the stored processing sequence number. ing.

  Next, the operation at the time of transmission of the data transmitting / receiving apparatus 10 according to the first embodiment of the present invention will be described using FIG. 2 to FIG. 4 and FIG. 6 to FIG. FIG. 6 schematically shows the data format in one frame and the configuration of schedule data in the FCH when data transmission / reception is performed by the data transmission / reception apparatus that can be used as a terminal of the high-speed PLC network system in the first embodiment. FIG. 7 is a flowchart showing an operation when the management terminal in the first embodiment generates a data transmission / reception schedule in one frame. FIG. 8 is a flowchart showing an operation when a MAC frame for transmission is generated by the data transmission / reception apparatus as a terminal of the high-speed PLC network system in the first embodiment, and FIG. 9 is a flowchart of the high-speed PLC in the first embodiment. It is a figure which shows roughly the data format structure in 1 MAC frame at the time of transmitting / receiving data by the data transmitter / receiver as a terminal of a network system.

  As shown in FIG. 2, the Ethernet frame data input via the Ethernet interface input terminal 20 is information such as the data length based on the Ethernet MAC header information added to the data in advance by the Ethernet interface circuit 12. Are separated and analyzed and input to the bridge interface circuit 13. When Ethernet frame data is input from the Ethernet interface circuit 12, the bridge interface circuit 13 reads the input data and separates the order information from the Ethernet MAC header. Similarly, the bridge interface circuit 13 searches for the destination port address using the destination MAC address information. When the analysis of the MAC header information added to the Ethernet frame is completed, the bridge interface circuit 13 stores the received Ethernet frame data in the bridge memory 14 based on the read order information and the detection result of the destination port. Remember.

  As shown in FIGS. 2 to 4, the bridge interface circuit 13 (FIG. 2) is output from the PLC transmission control circuit 40 (FIGS. 3 and 4) in the PLC modem circuit 15 (FIGS. 2 and 3). The Ethernet frame data queued in the above manner in the bridge memory 14 (FIG. 2) based on the destination port information and the Ethernet frame data request signal are read in the order of the read order information, and the PLC transmission control circuit 40 (FIG. 3, FIG. Output to FIG.

  Next, operation | movement of the PLC transmission control circuit 40 of the management terminal 1 is demonstrated using FIG. 4 and FIG. 6 to FIG. In the first embodiment, as in the conventional example, a case where the TDMA method is adopted as the MAC control method in the PLC network system will be described.

  As described in the conventional example, the management terminal 1 periodically outputs BCH (Beacon frame) and FCH (schedule information) to manage the PLC network system. FIG. 6 shows the transmission timing of various data in one frame. In the first embodiment, it is assumed that PLC network management information such as BCH is output in a cycle of 20 ms as in the conventional example. Therefore, the PLC transmission control circuit 40 in the management terminal 1 generates a Beacon frame and schedule information once every 20 ms. In the first embodiment, the time information of the management terminal 1 when the Beacon frame is transmitted is transmitted as payload information as Beacon frame information. Specifically, the PLC network control data generation circuit 408 outputs the reference time information in the PLC network control data generation circuit 408 when Beacon frame data is transmitted to the selector 404 as a payload. When receiving the Beacon frame information, the receiving terminal adjusts the internal reception reference time to the transmission side reference time added to the Beacon frame. The management terminal 1 performs transmission of FCH (schedule information) following transmission of BCH.

  Next, a method for generating schedule information will be described with reference to FIGS. 6 and 7. FIG. 6 shows an example of schedule information in the FCH. As shown in FIG. 6, the FCH is transmitted with schedule information added to the head position of received data and preamble information for detecting a clock phase at the time of reception. In the schedule information, transmission start time, transmission time, terminal information indicating from which terminal (transmitting terminal) to which terminal (receiving terminal) data transmission and data are transmitted / received for each communication slot provided in the data transmission / reception period. Send related information. In Embodiment 1, it is assumed that MAC address information (Media Access Control Address) possessed by each device is used as transmission terminal information and reception terminal information. In addition to the MAC address information, the same effect can be obtained by using, for example, a logical port number in the PLC network or identification information that is privately defined in the network. As shown in FIG. 6, the schedule information in the FCH is transmitted with the above information added for each communication slot. As for the communication slot, each terminal having data sends a bandwidth allocation request to the MAC header of the terminal that is actually transmitting data to the management terminal 1 for RCH information or data transmission. A transmission slot is allocated by adding and transmitting.

  Next, a flow of generating schedule information in the FCH will be described with reference to FIG. When the generation of the schedule information is started (step S10), the CPU 11 in the management terminal 1 receives the ACK / NACK frame transmission band for the transmission slot assigned by the management terminal 1 last time and the previous frame from each terminal. Band allocation for ACK / NACK frame transmission for the received data is performed (step S11). When the transmission slot allocation for the ACK / NACK frame is completed, the CPU 11 in the management terminal 1 next checks whether or not there is a retransmission request from each terminal and a retransmission request to each terminal (step S12). When there is a retransmission request, the CPU 11 in the management terminal 1 assigns a retransmission time slot (step S13). When the retransmission time slot assignment is completed, the CPU 11 in the management terminal 1 checks whether or not there is a new communication requesting terminal that has made a bandwidth assignment request using the RCH (step S14). If there is a new transmission request terminal, the CPU 11 in the management terminal 1 allocates a transmission time slot for that terminal (step S15). When the assignment of the transmission time slot to the new communication request is completed, the CPU 11 in the management terminal 1 assigns the transmission time slot of the management terminal 1 (step S16).

  Finally, the CPU 11 in the management terminal 1 assigns a transmission time slot for each terminal (step S17). When the transmission time slot assignment is completed, the PLC network control data generation circuit 408 in the management terminal 1 generates an FCH frame based on the assigned transmission time slot information (step S18). The FCH frame generated in the PLC network control data generation circuit 408 is output to the selector 404 in the management terminal 1 based on the timing information output from the PLC transmission timing generation circuit 407 in the management terminal 1 (step S19). ). Further, the PLC network control data generation circuit 408 in the management terminal 1 outputs a schedule (transmission time slot information) of data to be transmitted to each terminal in this frame to the PLC transmission timing generation circuit 407 when transmitting the FCH frame. In the first embodiment, transmission / reception timings of fixed slots such as BCH and FCH are set in advance in PLC transmission timing generation circuit 407 (FIG. 4) and PLC reception timing generation circuit 507 (FIG. 5). It shall be. The data reception timing slot information is set via the CPU 11 (FIG. 2) to the PLC reception timing generation circuit 507 (FIG. 5) in the PLC reception control circuit 50 (FIG. 5).

  Next, the operation at the time of transmitting Ethernet frame information input from the bridge interface circuit 13 will be described using FIGS. 2 to 4 and the MAC frame generation flow shown in FIG. In the following operation, the management terminal 1 sets the schedule information from the PLC network control data generation circuit 408 to the PLC transmission timing generation circuit 407 at the time of FCH transmission, as described above. On the other hand, when each terminal A, B, or C participating in the PLC network system receives the FCH, the CPU 11 separates time slot information for transmitting or receiving data by itself, and regarding the transmission time slot, It is set in the PLC transmission timing generation circuit 407 via the PLC network control data generation circuit 408. Regarding the reception time slot, the CPU 11 directly sets the reception schedule in the PLC reception timing generation circuit 507. Since the transmission operation of the Ethernet frame data to the PLC network in the management terminal 1 and the normal terminal A, B, or C is the same except for the operation of setting the transmission time slot to the PLC transmission timing generation circuit 407, the management terminal Only the transmission operation 1 will be described in detail below.

  As shown in FIG. 8, the PLC transmission timing generation circuit 407 firstly transmits the destination terminal information to be transmitted next from the schedule information output from the PLC network control data generation circuit 408 and the transmittable bytes from the transmission time. The number is calculated (step S30). In the PLC network, the PHY speed (PHY modulation / demodulation parameter) of transmission data differs for each connected terminal, as in the wireless LAN. When the calculation of the number of transmission bytes is completed, the PLC transmission timing generation circuit 407 stores the Ethernet frames stored in the bridge memory 14 for the bridge interface circuit 13 in the descending order of priority. Request to be notified. The PLC transmission timing generation circuit 407 determines the number of Ethernet frames to be transmitted this time based on the byte number information of the Ethernet frame output from the bridge interface circuit 13 (step S31).

  In the first embodiment, in order to efficiently flow data on the PLC network, when generating a PLCMAC frame, a plurality of Ethernet frames are concatenated and transmitted as one PLCMAC frame as shown in FIG. Therefore, as shown in FIG. 9, the PLC MAC frame is configured by connecting N (N is an integer of 1 or more) Ethernet frames following the PLC MAC header. The number of connected Ethernet frames, the length information of each connected Ethernet frame, etc. are added to the PLCMAC header and transmitted. Also, as shown in FIG. 9, the PLC MAC header includes information such as frame control information, destination MAC address, and source MAC address, and the frame control information is preferentially relayed by a sequence number indicating the relay order. It includes priority flag information (priority information) indicating whether or not the data should be transmitted, ACK / NACK flag information indicating whether transmission of an ACK / NACK frame is necessary, header length information, and the like.

  When the determination of the number of connected Ethernet frames is completed, the PLC transmission timing generation circuit 407 instructs the PLC header generation circuit 401 to generate a PLC MAC frame. At this time, the connection information of the Ethernet frame is output. On the other hand, the PLC network control data generation circuit 408 also reads out sequence number information (step S32-1) and confirms the type of transmission data, which is the processing shown in step S32 of FIG. (Step S32-2), addition of priority flag information (Step S32-3), determination of presence / absence of retransmission request (Step S32-4), output of ACK / NACK frame transmission request information (Steps S32-5, S32-6) ) And MAC header generation (step S32-7). When the instruction to the PLC header generation circuit 401 is completed, the PLC transmission timing generation circuit 407 waits until the data transmission time comes. The PLC header generation circuit 401 generates PLC header information based on the above information, and waits until the data transmission time.

  As shown in FIG. 8, when the data transmission time comes, the PLC transmission timing generation circuit 407 instructs the PLC header generation circuit 401 and the packet data generation circuit 402 to generate PLC MAC frame data for transmission. The bridge interface circuit 13 is instructed to output Ethernet frame data based on the connection information generated earlier in descending order of priority (step S33). The bridge interface circuit 13 reads predetermined Ethernet frame data from the bridge memory 14 in accordance with the data request instruction output from the PLC transmission timing generation circuit 407, and outputs it to the packet data generation circuit 402. The packet data generation circuit 402 temporarily stores the Ethernet frame data read from the bridge memory 14 in an internal memory, converts the data into blocks of a predetermined size (for example, in units of 128 bits), and an encryption circuit Output to 403. The encryption circuit 403 encrypts the data that has been blocked into a predetermined size (step S34). Data encrypted by the encryption circuit 403 is input to the selector 404. The selector 404 switches between the encrypted Ethernet frame data output from the encryption circuit 403 and PLC network control data such as BCH and FCH generated by the PLC network control data generation circuit 408. Specifically, the output of the encryption circuit 403 is selected during the data transmission / reception period shown in FIG. 6, and the output of the PLC network control circuit 408 is selected during the BCH, FCH, ACH, and RCH periods. The management terminal 1 corresponds to the BCH, FCH, and ACH periods, and each terminal corresponds to the RCH period. Note that the select signal of the selector 404 is output from the PLC transmission timing generation circuit 407 as shown in FIG.

  The output of the selector 404 is input to the PLC header addition circuit 405. The PLC header addition circuit 405 adds the PLC MAC header information output from the PLC header generation circuit 401 to the head of payload data output from the selector 404 based on the timing signal output from the PLC transmission timing generation circuit 407 (step). S35). In the first embodiment, the Ethernet frame data blocked in a predetermined size by the packet data generation circuit 402 is temporarily stored in a memory (not shown) provided in the PLC header addition circuit 405. , It is restored to the size of the Ethernet frame data. Similarly, the PLC MAC header is added to the PLC network control data output from the PLC network control data generation circuit 408 by the PLC header addition circuit 405.

  The PLC packet data to which the PLC MAC header information is added by the PLC header addition circuit 405 is input to the selector 406 and the PLC transmission memory control circuit 409. The selector 406 switches between the output from the PLC header addition circuit 405 and the output from the PLC transmission memory control circuit 409 based on the switching signal output from the PLC transmission memory control circuit 409. Details of the control of the PLC transmission memory control circuit 409 will be described later. The output of the selector 406 is input to the CRC code adding circuit 410. The CRC code adding circuit 410 adds a CRC code for detecting an error occurring in the PLC network to the MAC frame to which the PLC MAC header is added, which is input from the selector 406, and then the PHY header in the CRC code adding circuit 410. After adding a PHY header by an additional circuit (not shown), digital modulation such as OFDM modulation is performed on transmission data including the PHY header. The transmission data digitally modulated in the CRC adding circuit 410 is sent out on the power line 9 with a preamble of a predetermined number of symbols added to the head in a preamble adding circuit (not shown) in the CRC code adding circuit 410. The When the transmission of the MAC frame data to the power line 9 is completed, the PLC network control data generation circuit 408 increments the sequence number by one (step S36), and ends the MAC frame generation operation.

  Next, the operation of the PLC transmission memory control circuit 409 in the PLC transmission control circuit 40 will be described. In Embodiment 1, the presence / absence of retransmission control is switched depending on the type of MAC frame to be transmitted. Specifically, in the case of a packet such as VoIP that requires a delay amount to be kept below a predetermined time, even if retransmission control is performed, retransmission processing is not completed within the above time, so retransmission control is not performed. . For example, when the Beacon frame interval is 20 ms and the SR retransmission control method is adopted, when retransmission control occurs, a data delay of about 60 ms occurs. Similarly, when only the protocol used for the MAC control of the PLC performed between the management terminal 1 and the terminal such as ACK / NACK is transmitted, the retransmission control is not performed. Therefore, in Embodiment 1, retransmission control is performed only for Ethernet frames other than VoIP.

  Next, retransmission control when the SR retransmission control method is adopted as the retransmission control method for the TDMA method will be described with reference to FIG. FIG. 10 is a timing chart for explaining retransmission control when the SR retransmission control method is adopted as the retransmission control method in the TDMA method. FIG. 10 shows a case where the management terminal 1 is a transmission terminal, the terminal A is a reception terminal, and data is transmitted from the management terminal 1 to the terminal A for the sake of simplicity. After transmitting the BCH, FCH, and ACH, the management terminal 1 generates a MAC frame based on the MAC frame generation flow shown in FIG. When the terminal A receives the MAC frame transmitted from the management terminal 1, the terminal A analyzes the MAC header and separates the sequence number (denoted as “SN”). In parallel with these operations, the PLC reception control circuit 50 in the terminal A performs error detection using the CRC code added to the received MAC frame. Details of the data reception operation will be described later.

  The PLC reception control circuit 50 (FIG. 3) in the terminal A confirms the SN for the MAC frame determined to have no error as a result of error detection using the CRC code, and can output it to the bridge interface circuit 13 or not. to decide. In the first embodiment, the PLC reception control circuit 50 in the terminal A stores the SN of the MAC frame transmitted last in the bridge interface circuit 13 (FIG. 2), and whether or not it can be output due to the continuity of SN. Determine whether. Specifically, the PLC reception control circuit 50 in the terminal A, when the MAC frame last output to the bridge interface circuit 13 is a MAC frame having the N-1th SN, When the frame is received, the MAC frame having the Nth SN is output to the bridge interface circuit 13.

  The PLC reception control circuit 50 in the terminal A receives the MAC frame having the (N + 1) th SN when the MAC frame finally output to the bridge interface circuit 13 is the MAC frame having the (N-1) th SN. In this case, it is determined that the MAC frame having the Nth SN has been dropped due to a reception error, and the MAC frame data having the N + 1th SN is stored in the PLC reception memory 17 (shown in FIGS. 2 and 3). Wait until the MAC frame data having the Nth SN is received.

  Furthermore, the PLC reception control circuit 50 in the terminal A, when the MAC frame last output to the bridge interface circuit 13 is a MAC frame having the N-1th SN, the MAC having the N-2th SN. When the frame is received, since the MAC frame having the N-2th SN has already been sent to the bridge interface circuit 13, the received MAC frame having the N-2th SN is discarded. Such a case occurs when the management terminal 1 cannot receive the ACK frame transmitted by the terminal A.

  Based on the above retransmission control operation, the operation based on the priority flag information of received data when the SR retransmission control method is adopted will be described based on the timing chart shown in FIG. In the SR retransmission control scheme, when an error occurs, the PLC reception control circuit 50 in the terminal A performs retransmission control only on the MAC frame in which the error is detected. Although not shown in FIG. 10, it is assumed that MAC frames having SNs up to N are normally received. As illustrated in FIG. 10, when the terminal A receives a MAC frame having an SN of N + 1 from the management terminal 1, the terminal A performs error detection in the MAC frame as described above. When the PLC reception control circuit 50 in the terminal A determines that the MAC frame has been normally received as a result of error correction, the PLC reception control circuit 50 stores the data in the PLC reception memory 17 of the terminal A and outputs the data to the bridge interface circuit 13. The sequence number of data to be output to the bridge interface circuit 13 for reception of the next data (hereinafter referred to as “processing SN”) is incremented.

  FIG. 10 shows a case where an error has occurred in the MAC frame having the SN of N + 2 and reception has not been performed normally. In this case, the terminal A performs retransmission control on the transmission source, and ends the process without incrementing the process SN stored in the terminal A (that is, maintaining the process SN as N + 2). When the terminal A normally receives the MAC frame having the SN of N + 3, the processing SN is in the state of N + 2, so the MAC frame having the SN of N + 3 is stored in the PLC reception memory 17 of the terminal A. However, the process SN stored in the terminal A is not incremented (that is, the process SN is maintained as N + 2).

  Subsequently, the terminal A normally receives data (referred to as “priority processing data” or “priority processing MAC frame”) to be preferentially processed by the MAC frame having the SN of N + 4. In this case, the terminal A stores the received data in the PLC reception memory 17 of the terminal A, and immediately receives a MAC frame having N + 4 SN without being affected by the processing SN stored in the terminal A. Output to the bridge interface circuit 13. At this time, the process SN stored in the terminal A is not incremented and is maintained as N + 2. However, in addition to the process SN, the terminal A adds the SN of the MAC frame for which priority processing has been completed (hereinafter, “priority processing”). N + 4 (denoted as “(N + 4 storage)” in the preferentially processed SN portion in FIG. 10).

  Next, the terminal A normally receives a MAC frame that has N + 5 SN and is not preferentially processed (that is, a MAC frame other than the priority processing MAC frame). At this time, in addition to the MAC frame having the N + 3 SN, the MAC frame having the N + 5 SN is stored in the PLC reception memory 17 of the terminal A. At this stage, the processing SN is the N + 2 number. Therefore, the output of the MAC frame having the SN of N + 3 and the MAC frame having the SN of N + 5 to the bridge interface circuit 13 is not started.

  Next, it is assumed that terminal A has successfully received a MAC frame having an N + 2 SN that has previously detected an error. At this time, the PLC reception memory 17 of the terminal A stores a MAC frame having an N + 2 SN in addition to a MAC frame having an N + 3 SN and a MAC frame having an N + 5 SN. Since terminal A stores N + 2 as the process SN, it starts outputting the MAC frame to the bridge interface circuit 13. The terminal A outputs the MAC frame having the N + 2 SN stored in the PLC receiving memory 17 to the bridge interface circuit 13 to set the processing SN to N + 3, and then stored in the PLC receiving memory 17. The MAC frame having the SN of N + 3 is output to the bridge interface circuit 13, and the processing SN is set to N + 4. Since the terminal A stores N + 4 as the priority processed SN when the process SN becomes N + 4, the process SN and the priority processed SN match. Therefore, the terminal A recognizes that the output of the N + 4th MAC frame, which is the processing SN, to the bridge interface circuit 13 has already been completed, and increments the processing SN to N + 5. Next, the terminal A outputs the MAC frame having the N + 5th SN stored in the PLC reception memory 17 to the bridge interface circuit 13, and increments the processing SN to the N + 6th.

  After that, the terminal A identifies each of the MAC frames having SNs from N + 6 to N + 9 according to the error correction result of the received data, and identifies the priority processing MAC frame and a MAC frame other than the priority processing MAC frame, Based on the identification result, the received MAC frame is output to the bridge interface circuit 13, and the processing SN and the priority processing SN are managed.

  Next, a case where an error has occurred in the priority processing MAC frame whose SN is N + 10 and the packet could not be received normally will be described. In this case, the terminal A performs retransmission control on the transmission source, maintains the process SN as N + 10 without incrementing the process SN, and ends the process. Subsequently, it is assumed that a MAC frame other than the priority processing MAC frame having an SN of N + 11 is normally received. At this time, the terminal A stores the MAC frame having the SN of No. 11 in the PLC reception memory 17 and confirms the presence / absence of the ACK / NACK slot for the previous MAC frame transmitted from the management terminal 1. The priority processing MAC frame, which is data that needs to be processed with priority, has a large restriction on delay, and no retransmission request is made. In this case, there is no ACK / NACK slot. Terminal A confirms that there is no ACK / NACK slot, and determines that retransmission control is unnecessary for the error that occurred in the previous MAC frame, and that the processing SN may be incremented. Terminal A cancels retransmission control for the transmission source, and stores N + 10, which is the SN of this error MAC frame, as a priority-processed SN. At this time, the processing SN is N + 10, the priority processing SN is N + 10, and the processing SN and the priority processing SN match, so the processing SN is incremented from N + 10 to N + 11.

  Next, the terminal A outputs the MAC frame having the N + 11th SN stored in the PLC reception memory 17 to the bridge interface circuit 13 and increments the processing SN to the N + 12th.

  Next, the terminal A receives the MAC frame having the SN of N + 12 and stores it in the PLC reception memory 17. At this time, since the process SN is N + 12, the terminal A outputs the MAC frame having the SN + 12 stored in the PLC reception memory 17 to the bridge interface circuit 13 and increments the process SN. N + 13. Thereafter, the received data is relayed by repeating the process according to the same procedure.

  Next, the operation flow of terminal A, B, or C of data transmitting / receiving apparatus 10 in Embodiment 1 of the present invention will be described using FIG. As described above, in the MAC control system based on TDMA, time synchronization between the management terminal 1 and each terminal is established by a Beacon frame (BCH). When time synchronization (matching the reference time) is established by the Beacon frame, transmission / reception of MAC frame data between the management terminal 1 and each terminal is performed based on the reference time. Therefore, when the data transmission / reception operation via the PLC network is started, each terminal starts detecting the Beacon frame (BCH) transmitted from the management terminal 1. Each terminal, when detecting the BCH (step S40), corrects the reference time of each terminal based on the reference time information of the management terminal 1 added in the Beacon frame (step S41).

  When the correction of the reference time is completed, each terminal starts receiving FCH (step S42). When receiving the FCH, each terminal checks whether or not its own transmission / reception time slot is scheduled (step S43). If there is a reception slot in the schedule (step S44), the terminal confirms the reception time and waits until that time (step S45). When the reception time comes, the terminal starts receiving data input via the power line 9 (step S46). When the reception of the MAC frame is started, the terminal separates and confirms the connection information of the Ethernet frame added to the MAC header part and the MAC frame length. When reception of data for one MAC frame is completed, the terminal checks whether or not the next reception slot is in the schedule (step S47). If the reception slot is in the schedule, the terminal confirms the next reception time and waits until that time. On the other hand, if the reception slot is not in the schedule, the terminal next checks whether or not a transmission slot is assigned (step S48). Even in the case where the reception slot is not assigned in step S44, as shown in FIG. 11, the terminal checks whether or not the transmission slot is assigned (step S48).

  If there is a transmission slot in the schedule, the terminal confirms the transmission time and waits until that time (step S49). When the transmission time comes, the terminal starts data transmission via the power line 9 (step S50). When the transmission of the MAC frame is completed, the terminal checks whether or not the next transmission slot is in the schedule (step S51). If there is a next transmission slot, the terminal confirms the next transmission time and waits until that time. On the other hand, if the transmission slot is not in the schedule, the terminal confirms whether or not to execute a bandwidth allocation request next. Even in the case where no transmission slot is allocated in step S48, as shown in FIG. 11, the terminal checks whether or not to execute a bandwidth allocation request (step S52). When executing the bandwidth allocation request, the terminal transmits the RCH at a predetermined time (step S53) and waits until receiving the BCH. If the terminal does not execute the bandwidth allocation request, the terminal completes the operation in this frame and waits until BCH reception.

  Next, the operation of each terminal (management terminal 1, terminal A, terminal B, and terminal C) of data transmitting / receiving apparatus 10 according to the first embodiment of the present invention will be described using FIG. 2, FIG. 3, and FIG. . The MAC frame data received via the power line 9 is input to the PLC modem circuit input terminal 23 in the data transmitter / receiver 10. The MAC frame data input to the PLC modem circuit input terminal 23 is input to the PLC reception control circuit 50 in the PLC modem circuit 15. The MAC frame data input to the PLC reception control circuit 50 detects a preamble added in advance at the time of transmission by a digital demodulation circuit unit (not shown). After the preamble detection, the received data is subjected to digital demodulation (for example, OFDM) and converted to the original MAC frame data. At that time, the digital demodulation circuit section separates the PHY header information added at the time of transmission. A parameter such as a data length is added to the PHY header, and digital demodulation is performed based on the information.

  The MAC frame data digitally demodulated by the digital demodulation circuit unit is input to the PLC header analysis circuit 501 and the CRC decoding circuit 502. The CRC decoding circuit 502 detects an error generated in the received MAC frame based on CRC information added in advance to the MAC frame data at the time of transmission. On the other hand, the PLC header analysis circuit 501 separates the MAC header portion from the input MAC frame data, and analyzes the MAC header. Specifically, the PLC header analysis circuit 501 separates the connection information of the Ethernet frame added at the time of transmission, the MAC frame length, and the like, and the PLC control frame separation circuit 504, the PLC control frame data storage circuit 505, and the PLC reception The data is output to the timing generation circuit 507. On the other hand, the error detection information detected by the CRC decoding circuit 502 is input to the PLC reception memory control circuit 506. When an error is detected, the information is also input to the PLC control frame separation circuit 504, the PLC control frame data storage circuit 505, and the PLC reception timing generation circuit 507. The received data from which the MAC header is separated by the PLC header analysis circuit 501 is input to the encryption / decryption circuit 503. If an error is detected in the CRC decoding circuit 502, the CPU 11 is notified of this via an interrupt control line (not shown). When an error is detected in the CRC decoding circuit 502, the CPU 11 notifies the PLC network control data generation circuit 408 (FIG. 4) to that effect, and outputs a NACK packet including SN information that has been lost in the next frame. (Detailed operations relating to retransmission control will be described later). Note that, when confirming the continuity of the SN of the received MAC frame, the CPU 11 controls to send out a NACK packet including the SN information even when the SN is missing (flying).

  The encryption / decryption circuit 503 decrypts the encryption applied at the time of transmission, and inputs it to the PLC control frame separation circuit 504. The PLC control frame separation circuit 504 separates PLC control frame information such as ACK / NACK from the Ethernet frame based on the connection information of the Ethernet frame and the MAC header analysis information input from the PLC header analysis circuit 501. The PLC control frame separation circuit 504 also separates PLC control frames such as schedule information output from the management terminal 1 such as FCH, or RCH information output from each terminal to the management terminal 1.

  The PLC control frame separated by the PLC control frame separation circuit 504 is temporarily stored in the PLC control frame data storage circuit 505. The PLC control frame storage circuit 505 generates an interrupt to the CPU 11 when storage of all the PLC control frames in one MAC frame is completed. When an interrupt is input from the PLC control frame data storage circuit 505, the CPU 11 once fetches the PLC control frame and issues an instruction to each circuit based on the analysis result. For example, when receiving the FCH schedule information, the CPU 11 analyzes the captured data, and then sets the data transmission / reception slot information in the PLC reception timing generation circuit 507 based on the analysis result. Similarly, in the case of ACK / NACK information, the CPU 11 issues an instruction to each circuit based on the reception result. Specifically, when the data transmitted in the previous frame is ACK, the CPU 11 issues an instruction to erase the corresponding MAC frame data stored in the PLC transmission memory 16. On the other hand, when the data transmitted in the previous frame is NACK, the CPU 11 notifies the PLC network control data generation circuit 408 that the data has not been normally transmitted, and instructs to enter preparation for retransmission control.

  On the other hand, Ethernet frame data output from the PLC control frame separation circuit 504 is input to the PLC reception memory control circuit 506. The PLC reception memory control circuit 506 separates the Ethernet frame from the input MAC frame data based on the connection information of the Ethernet frame output from the PLC header analysis circuit 501, and stores the Ethernet frame in the PLC reception memory 17 in units of Ethernet frames. Remember. When the storage of the Ethernet frame for one MAC frame in the PLC reception memory 17 is completed, the PLC reception memory control circuit 506 confirms the SN information added to the MAC frame output from the PLC header analysis circuit 501, It is confirmed whether or not the received MAC frame data can be output to the bridge interface circuit 13. Although the details of the specific confirmation operation have been described above, the PLC reception memory control circuit 506 determines the continuity of the SN information of the MAC frame already output to the bridge interface circuit 13 and the SN of the MAC frame received this time. If it is confirmed that it is continuous, the received MAC frame data is output to the bridge interface circuit 13 in units of Ethernet frames. On the other hand, if it is not continuous, it is determined that it is waiting for retransmission data, and data is not read from the PLC reception memory 17. On the other hand, the Ethernet frame data input into the bridge interface circuit 13 is temporarily stored in the bridge memory 14 after performing an FDB search or the like. The Ethernet frame data stored in the bridge memory 14 is read from the bridge memory 14 on the basis of a data transmission preparation completion signal output from the Ethernet interface circuit 12, and the Ethernet interface circuit 12 performs a predetermined Ethernet use. A MAC header and a PHY header are added and output to the Ethernet network via the output terminal 21.

  Next, the operation of the data transmitting / receiving apparatus 10 at the time of data reception will be described using the flowcharts of FIGS. 12, 13, and 14. FIG. FIG. 12 is a flowchart (part 1) showing an operation when data is received by the data transmission / reception apparatus as a terminal of the high-speed PLC network system according to the first embodiment, and FIG. 13 is a high-speed PLC network according to the first embodiment. It is a flowchart (the 2) which shows operation | movement at the time of receiving data by the data transmitter / receiver as a terminal of a system. In the description of the first embodiment, a case where the SR method is adopted as the retransmission control method will be described.

  As shown in FIG. 12, when the reception timing within one frame is set in the PLC reception timing generation circuit 507, the PLC reception control circuit 50 waits until the reception time (reception timing) is reached (step S60). When the reception time is reached and the MAC frame is input, the PLC reception control circuit 50 separates the MAC frame by the PLC header analysis circuit 501, and performs header analysis (step S61). The PLC reception control circuit 50 confirms whether or not the data is addressed to its own terminal based on the analysis result of the MAC header (step S62). If the data is not addressed to the own terminal in step S62, the PLC reception control circuit 50 notifies the CPU 11 that the data is not addressed to the own terminal, and waits until the next data is received. When the interrupt is input, the CPU 11 confirms the schedule, and if it is a time slot for the terminal itself, instructs the PLC network control data generation circuit 408 to transmit a NACK packet in the own frame.

  If the received data is the data addressed to the own terminal in step S62, the PLC reception control circuit 50 detects whether the received MAC frame has an error in the CRC decoding circuit 502 (step S63). If an error is detected in the MAC frame in step S63, the PLC reception control circuit 50 notifies the CPU 11 as described above, and each circuit starts the retransmission control process based on the instruction from the CPU 11 (step S64). Specifically, the CRC decoding circuit 502 instructs the PLC network control data generation circuit 408 to transmit a NACK packet in its own frame, and enters the retransmission control process for the PLC reception memory control circuit 506. Notify that. When the retransmission control process is activated, the data transmitting / receiving apparatus 10 enters a reception process for the next MAC frame.

  On the other hand, if no error is detected in the MAC frame in step S63, the PLC reception control circuit 50 checks whether or not the ACK / NACK flag is set (step S65). If the ACK / NACK flag is set in step S65, the PLC reception control circuit 50 causes the CPU 11 to start ACK / NACK transmission processing (step S66). If the ACK / NACK flag is not set in step S65, the PLC reception control circuit 50 performs the following processing.

  After confirming the set of the ACK / NACK flag, the PLC reception control circuit 50 acquires the priority flag information of the received MAC frame (step S67). The PLC reception control circuit 50 confirms whether or not the MAC frame is set to be preferentially processed based on the priority flag information (step S68). In step S68, if the received MAC frame is a priority processing MAC frame that is preferentially processed, the PLC reception control circuit 50 temporarily stores the received MAC frame in the PLC reception memory 17 (step S69). ). When the storage of the MAC frame in the PLC reception memory 17 is finished, the PLC reception control circuit 50 confirms whether or not the output to the bridge interface circuit 13 is possible. The PLC reception control circuit 50 waits until output becomes possible when there is no empty area in the bridge memory 14 and transmission is impossible (step S70). When the output to the bridge interface circuit 13 becomes possible, the PLC reception control circuit 50 outputs the received MAC frame to the bridge interface circuit 13 in units of Ethernet frames (step S71).

  When the PLC reception control circuit 50 finishes transmitting data for one MAC frame to the bridge interface circuit 13, the PLC reception control circuit 50 checks the continuity between the processing SN and the SN of the MAC frame output to the bridge interface circuit 13 (step S72).

  In step S72, if the SN of the received MAC frame matches the stored processing SN (that is, if the continuity of SN is confirmed), the PLC reception control circuit 50 increments the processing SN. (Step S73). In step S71, if the SN of the received MAC frame is different from the stored processing SN (that is, if the continuity of SN is not confirmed), the PLC reception control circuit 50 sets the SN of the priority processing MAC frame. It is stored as the priority processed SN (step S74) (for example, see the case of SN = N + 4 in FIG. 10). When the operation of step S73 or S74 ends, the process proceeds to a determination process (step S60) for determining whether it is a reception time.

  On the other hand, if it is determined in step S68 that the frame is a MAC frame other than the priority processing MAC frame, the PLC reception control circuit 50 checks the continuity between the processing SN and the SN of the received MAC frame (step in FIG. 13). S75). Here, “SN continuity” or “SN continuity is OK” means that the processing SN which is the SN of the MAC frame to be output to the bridge interface circuit 13 next, the SN of the received MAC frame, For example, in FIG. 10, the processing SN is N + 1, the SN of the received MAC frame is N + 1, and the two match. If a match between the processing SN and the SN of the received MAC frame is confirmed in step S75, the PLC reception control circuit 50 temporarily stores the received MAC frame in the PLC reception memory 17 (step S80 in FIG. 13). ). If there is no empty area in the bridge memory 14 (FIG. 1) and transmission is not possible, the PLC reception control circuit 50 waits until output is possible (step S81 in FIG. 13). When the output to the bridge interface circuit 13 becomes possible, the PLC reception control circuit 50 outputs the received MAC frame to the bridge interface circuit 13 in units of Ethernet frames (step S82 in FIG. 13). When the transmission of data for one MAC frame to the bridge interface circuit 13 is completed, the PLC reception control circuit 50 increments the processing SN of the MAC frame that has been transmitted to the bridge interface circuit 13 (step S83 in FIG. 13).

  Subsequently, the PLC reception control circuit 50 checks whether or not the processing SN and the priority processing SN match in order to check the continuity of the SN (step S84 in FIG. 13). When the processing SN and the priority processing completed SN match in step S84, the PLC reception control circuit 50 increments the processing SN (step S83 in FIG. 13), and again whether the processing SN matches the priority processing SN. It is confirmed whether or not (step S84 in FIG. 13). The PLC reception control circuit 50 performs the confirmation in step S84 and the increment of the process SN in step S83 until the coincidence between the process SN and the priority processed SN is not confirmed.

  When the match between the processing SN and the priority processed SN is not confirmed in step S84, or when the continuity confirmation by the increment of the processing SN is finished, the PLC reception control circuit 50 receives the received data in the PLC reception memory 17. (Step S85 in FIG. 13). If there is no reception data in the PLC reception memory 17 in step S85, the PLC reception control circuit 50 determines whether it is the reception time. On the other hand, when there is reception data in the PLC reception memory 17, the PLC reception control circuit 50 confirms whether or not the processing SN matches the SN of the MAC frame stored in the PLC reception memory 17 ( Step S86 in FIG. 13). When the processing SN and the SN of the MAC frame stored in the PLC reception memory 17 match in step S86, the PLC reception control circuit 50 again outputs to the bridge interface circuit 13 (step S81 in FIG. 13). Is determined, and the processes from step S82 to S86 are performed again. If the processing SN and the SN of the MAC frame stored in the PLC reception memory 17 do not match in step S86, the PLC reception control circuit 50 determines whether or not it is a reception time (step S60 in FIG. 12). To implement.

  Next, based on the priority flag information, whether or not the MAC frame is set to be preferentially processed (step S68 in FIG. 12), the processing SN and the SN of the received MAC frame match. A processing flow in the case of not (ie, there is no SN continuity) (step S75 in FIG. 13) will be described. The PLC reception control circuit 50 determines whether or not the SN of the received MAC frame is larger or smaller than the processing SN (step S76 in FIG. 13). If the SN of the received MAC frame is smaller than the processing SN, the received MAC frame Is discarded, and it is determined whether it is the reception time (step S60 in FIG. 12). On the other hand, when the SN of the received MAC frame is larger than the processing SN in step S76, the PLC reception control circuit 50 temporarily stores the SN of the MAC frame and the processing SN in the PLC reception memory 17 (step S78 in FIG. 13). . Thereafter, the PLC reception control circuit 50 performs a delivery confirmation determination (step S79 in FIG. 13), and then determines whether it is a reception time (step S60 in FIG. 12).

  Next, the operation of the delivery confirmation determination (step S79) in the reception processing flow shown in FIG. 13 according to the first embodiment will be described with reference to FIG. FIG. 14 is a flowchart showing an operation when determining whether or not the MAC frame data received by the data transmitting / receiving apparatus as the terminal of the high-speed PLC network system according to the first to third embodiments is delivery confirmation unnecessary data. In the first embodiment, when the reception slot for the ACK / NACK frame for delivery confirmation is not scheduled in the reception slot scheduled in the FCH, the PLC reception control circuit 50 receives the previous frame from the management terminal 1. Control is performed so as to determine that the transmitted MAC frame data is a delivery confirmation unnecessary frame. The reason for this control is as follows. For example, if an error occurs in received data when terminal A receives a MAC frame including VoIP that does not require delivery confirmation, terminal A has received the normal MAC frame received last time at the beginning of data to be transmitted in the next frame. After the fact that it could not be received is added to the payload following the MAC header, the Ethernet frame is connected and output. When the management terminal 1 receives the NACK packet from the terminal A, the management terminal 1 notifies the terminal A that the data transmitted in the previous frame is a delivery confirmation unnecessary packet in the next frame. After receiving the delivery confirmation unnecessary frame received from the management terminal 1, the terminal A reads the MAC frame data stored in the PLC reception memory 17. However, if the received MAC frame cannot be received again due to an error that has occurred in the transmission path, the terminal A cannot receive the delivery confirmation unnecessary frame even though it is a retransmission unnecessary (delivery confirmation unnecessary) frame. Thereafter, the received MAC frame data cannot be output to the bridge interface circuit 13, and an unnecessary delay occurs. The delay becomes a problem in a frame such as VoIP in which the data delay amount is largely limited. In the first embodiment, it is configured to determine that reception of retransmission unnecessary (delivery confirmation unnecessary) frames is scheduled on the FCH, thereby preventing unnecessary delay of data processing in the terminal A. . Hereinafter, details of the delivery confirmation determination will be described with reference to FIGS. 12, 13, and 14.

  As shown in FIG. 14, when the FCH is received, the CPU 11 checks whether or not an error has occurred in the MAC frame data received in the previous frame (step S90). If no error has occurred in the MAC frame data received in the previous frame, the CPU 11 ends the delivery confirmation determination (step S103). On the other hand, if an error has occurred in step S90, the CPU 11 checks whether or not a transmission confirmation transmission slot (ACK / NACK packet slot) is scheduled in the FCH (step S91). In step S91, if the transmission slot is scheduled, the CPU 11 determines that the MAC frame data in which the reception error is detected in the previous frame is a MAC frame that requires delivery confirmation, and ends the delivery confirmation judgment. (Step S103).

  If no transmission confirmation transmission slot is prepared in the FCH in step S91, the CPU 11 determines that the MAC frame in which a reception error has occurred in the previous frame is a delivery confirmation unnecessary frame. The CPU 11 determines that the MAC frame received in the previous frame is a delivery confirmation unnecessary frame and estimates the SN of the MAC frame data. Specifically, the CPU 11 estimates the SN of the MAC frame from the SN added to the MAC frame received immediately before the target MAC frame data. At that time, the CPU 11 instructs the PLC network control data generation circuit 408 to discard the transmission of the NACK packet. Then, the CPU 11 notifies the PLC reception memory control circuit 506 of the SN estimation result of the MAC frame. The PLC reception memory control circuit 506 determines whether or not the SN of the MAC frame notified from the CPU 11 matches the processing SN to the bridge interface circuit 13 managed in its own circuit (that is, continuous to the SN). It is confirmed whether or not there is a property (step S92). As a result of the confirmation in step S92, when the coincidence between the SN of the notified MAC frame and the processing SN cannot be confirmed (when there is no SN continuity), the PLC reception memory control circuit 506 determines that the delivery confirmation is unnecessary. The SN of the MAC frame is stored as a priority processed SN, and it is immediately checked whether the processing SN matches the priority processed SN (whether there is continuity) (step S93). As a result of the confirmation in step S93, if the process SN and the priority processed SN do not match, the PLC reception memory control circuit 506 ends the delivery confirmation determination (step S103), and the process SN and the priority processed SN are If they match (if there is continuity), the process proceeds to the next step S94.

  In step S92, when the SN of the MAC frame matches the processing SN (when there is continuity), the PLC reception memory control circuit 506 increments the processing SN to the bridge interface circuit 13 by one (step S92). S94). The PLC reception memory control circuit 506 continues to check whether or not the processing SN and the priority processing SN match in order to check the continuity between the processing SN and the priority processing SN (step S95). If the PLC reception memory control circuit 506 confirms that the processing SN and the priority processed SN match, the PLC receiving memory control circuit 506 again performs the processing for incrementing the processing SN (step S94), and again performs the processing SN and the priority processing SN. Is matched (step S95). The PLC reception memory control circuit 506 performs the continuity check in step S95 and the increment of the process SN in step S94 until the coincidence between the process SN and the priority processed SN is not confirmed.

  When the coincidence between the processing SN and the priority processed SN is not confirmed, or when the confirmation of continuity by the increment of the processing SN is finished, the PLC reception memory control circuit 506 stores the received data in the PLC reception memory 17. It is confirmed whether or not there is (step S96). When there is no reception data in the PLC reception memory 17, the PLC reception memory control circuit 506 ends the delivery confirmation determination (step S103). On the other hand, the PLC reception memory control circuit 506 waits until output is possible when there is reception data in the PLC reception memory 17 and there is no free space in the bridge memory 14 and transmission is not possible ( Step S97). When the output to the bridge interface circuit 13 becomes possible, the PLC reception memory control circuit 506 outputs the received MAC frame to the bridge interface circuit 13 in units of Ethernet frames (step S98). When the transmission of data for one MAC frame to the bridge interface circuit 13 is completed, the PLC reception control circuit 50 increments the process SN (step S99).

  The PLC reception control circuit 50 subsequently checks whether or not the processing SN and the priority processing SN match in order to check the continuity between the processing SN and the priority processing SN (step S100). When the PLC reception control circuit 50 confirms that the process SN matches the priority processed SN, the PLC reception control circuit 50 increments the process SN (step S99), and again checks whether the process SN and the priority processed SN match. To do. When the PLC reception control circuit 50 confirms that the process SN in step S100 matches the priority processed SN, the process SN increment in step S99 is confirmed, and the match between the process SN and the priority processed SN is confirmed. Continue until it runs out. In step S100, when the coincidence between the processing SN and the priority processed SN is not confirmed, or when the continuity confirmation by the increment of the processing SN is finished, the PLC reception memory control circuit 506 performs the PLC reception memory 17 Then, it is confirmed whether or not there is received data (step S101). If there is reception data in the PLC reception memory 17, the PLC reception memory control circuit 506 ends the delivery confirmation determination (step S103). On the other hand, when there is no reception data in the PLC reception memory 17, the PLC reception memory control circuit 506 checks the continuity of the SN between the processing SN and the MAC frame stored in the PLC reception memory 17. It is confirmed whether or not the processing SN and the SN of the MAC frame stored in the PLC reception memory 17 match (step S102). When the SN of the processing SN and the MAC frame stored in the PLC reception memory 17 is confirmed, if there is no free area in the bridge memory 14 and transmission is impossible, the process waits until output is possible. (Step S97). When the SN match between the process SN and the MAC frame stored in the PLC reception memory 17 is not confirmed (that is, there is no SN continuity), the delivery confirmation judgment is terminated (step S103).

  As described above, when the data transmission / reception apparatus (data transmission / reception method) of the first embodiment is used, when the SR method is adopted for retransmission control, when an error occurs in the MAC frame received by the receiving terminal, priority is given. Due to the priority processing operation on the receiving terminal side based on the flag information, normal reception of error data by retransmission control is awaited for data such as VoIP with a large data delay amount restriction (requires real-time property). This is unnecessary, and has the effect of suppressing the occurrence of unnecessary delay.

  In other words, the terminal that has received the priority processing MAC frame shown as the MAC frame having the SN of N + 4 in FIG. 10 has the processing SN of N + 2 different from N + 4 that is the SN of the priority processing MAC frame. Even so, the process of outputting the priority processing MAC frame to the bridge interface circuit 13 is preferentially executed. For this reason, unnecessary delay does not occur in the relay of the priority processing MAC frame requiring real-time property. Further, the terminal that has received the priority processing MAC frame shown as the MAC frame having the SN of N + 10 in FIG. 10 outputs retransmission control when an error is detected in the MAC frame having the SN of N + 10. However, since the retransmission control is canceled and the MAC frame having the SN of N + 10 is discarded and stored as the preferentially processed SN, real-time property is required, and the importance is lost when it is delayed, such as VoIP In data transmission, there is an advantage that it is not necessary to relay a priority processing MAC frame that does not need to be transmitted.

Embodiment 2. FIG.
Hereinafter, a data receiving apparatus and data receiving method according to Embodiment 2 of the present invention will be described based on a data transmitting / receiving apparatus 10 having the configuration shown in FIGS. 1 to 5. FIG. 15 is a timing chart showing an operation when the Go-Back-N retransmission control method is adopted in the data transmitting / receiving apparatus as the terminal of the high-speed PLC network system according to the second embodiment.

  In the second embodiment, a case where the Go-Back-N retransmission control method is adopted will be described. In the Go-Back-N retransmission control method, the timing of deleting (discarding) the MAC frame data stored in the PLC reception memory 17 is different from the SR retransmission control method described in the first embodiment. Based on the timing chart when the Go-Back-N retransmission control method shown in FIG. 15 is adopted, an operation for performing processing based on the priority flag information of received data will be described. Note that the circuit configuration of the data transmitting / receiving apparatus described in the second embodiment is the same as that in the first embodiment, and therefore the description will focus on the Go-Back-N retransmission control method. In the Go-Back-N retransmission control method, when an error occurs, retransmission control is performed on all frames after the MAC frame in which the error is detected. However, MAC frames that do not require retransmission control are not retransmitted. In FIG. 15, it is assumed that normal reception is performed up to the MAC frame whose SN is N.

  As shown in FIG. 15, the terminal A normally receives the MAC frame having the N + 1th SN from the management terminal 1, and the MAC frame having the N + 2th SN has an error and has not been received normally. To do. As shown in FIG. 15, when the terminal A receives the MAC frame having the SN of N + 3, since the processing SN is N + 2, the MAC frame having the SN of N + 3 is once received by the PLC. After being stored in the memory 17, the data is discarded.

  Next, the terminal A normally receives the priority processing MAC frame having the SN of N + 4. In this case, the terminal A stores the received data in the PLC reception memory 17 of the terminal A, and immediately receives a MAC frame having N + 4 SN without being affected by the processing SN stored in the terminal A. Output to the bridge interface circuit 13. At this time, the process SN stored in the terminal A is not incremented and is maintained as N + 2. However, in addition to the process SN, the terminal A adds the SN of the MAC frame for which priority processing has been completed (hereinafter, “priority processing”). N + 4 (denoted as “(N + 4 storage)” in the portion of the priority processed SN in FIG. 15).

  Next, the terminal A normally receives a MAC frame not preferentially processed (that is, a MAC frame other than the preferentially processed MAC frame) having N + 2 SN by Go-Back-N retransmission control. At this time, since the N + 2 number that is the SN of the received MAC frame matches the stored processing SN number N + 2 (that is, the SN is continuous), the terminal A changes the SN of the N + 2 number. The MAC frame is output to the bridge interface circuit 13, and the process SN is incremented to N + 3.

  Next, the terminal A normally receives the MAC frame having the N + 3 SN. At this time, since the N + 3 number which is the SN of the received MAC frame matches the stored processing SN number N + 3, the terminal A outputs the MAC frame having the N + 3 number SN to the bridge interface circuit 13. Then, the process SN is incremented to N + 4, but the SN of N + 4 is stored as the priority processed SN, so the process SN is further incremented to N + 5.

  Next, the terminal A normally receives the MAC frame having the SN of N + 5. At this time, since the N + 5 which is the SN of the received MAC frame matches the stored processing SN N + 5, the terminal A outputs the MAC frame having the N + 5 SN to the bridge interface circuit 13. Then, the process SN is incremented to N + 6.

  Next, a case will be described in which the priority processing MAC frame having the SN of N + 6 cannot be normally received in the terminal A due to the occurrence of an error, and thereafter the MAC frame having the SN of N + 7 is normally received. Terminal A performs retransmission control when the priority processing MAC frame having the SN of N + 6 cannot be normally received due to an error. Next, when the terminal A receives the MAC frame having the SN of N + 7, it stores this MAC frame in the PLC reception memory 17 and at the same time, the ACK / NACK for the previous MAC frame transmitted from the management terminal 1 Check if there is a slot. The MAC frame having the SN of N + 6 is a priority processing MAC frame, and there is no ACK / NACK slot. Therefore, retransmission control is not necessary for an error generated in the previous MAC frame. Therefore, terminal A cancels retransmission control for the transmission source, increments the processing SN to N + 7, and stores N + 6, which is the SN of the erroneous priority processing MAC frame, as the priority processing completed SN. At this time, since the processing SN and the priority processing SN match, the terminal A starts outputting the MAC frame having the SN of N + 7 to the bridge interface circuit 13 and increments the processing SN from N + 7 to N + 8. To do.

  Next, the terminal A receives the MAC frame having the SN of N + 8, outputs it to the bridge interface circuit 13, and increments the processing SN from N + 8 to N + 9. Retransmission control, priority processing operation, and SN management are also performed for MAC frames having N + 9 and subsequent SNs as described above.

  FIG. 16 is a flowchart (No. 1) showing an operation when data is received by the data transmitting / receiving apparatus as a terminal of the high-speed PLC network system according to the second embodiment, and FIG. It is a flowchart (the 2) which shows operation | movement at the time of receiving data by the data transmitter / receiver as a terminal of a system. Hereinafter, an operation flow of the data transmitting / receiving apparatus 10 at the time of data reception when the Go-Back-N retransmission control method is adopted will be described with reference to FIGS. 16 and 17. When the reception timing within one frame is set in the PLC reception timing generation circuit 507, the PLC reception control circuit 50 waits until the reception time (reception timing) is reached (step S60 in FIG. 16). When the reception time comes and the MAC frame is input, the PLC reception control circuit 50 separates the MAC frame in the PLC header analysis circuit 501 and performs header analysis (step S61 in FIG. 16). The PLC reception control circuit 50 confirms whether or not the data is addressed to the own terminal from the analysis result of the MAC header (step S62 in FIG. 16). When the data is not addressed to the own terminal, the PLC reception control circuit 50 notifies the CPU 11 that the data is not addressed to the own terminal, and waits until the next data is received. When the interrupt is input, the CPU 11 confirms the schedule, and if it is a time slot for the terminal itself, instructs the PLC network control data generation circuit 408 to transmit a NACK packet in the own frame.

  If the received MAC frame is data addressed to the own terminal, the PLC reception control circuit 50 detects whether the received MAC frame has an error by the CRC decoding circuit 502 (step S63 in FIG. 16). When an error is detected in the MAC frame in step S63, the PLC reception control circuit 50 notifies the CPU 11 as described above, and each circuit starts the retransmission control process based on the instruction from the CPU 11 (step S64 in FIG. 16). ). Specifically, the PLC reception control circuit 50 instructs the PLC network control data generation circuit 408 to transmit a NACK packet in its own frame, and enters the retransmission control process for the PLC reception memory control circuit 506. Notify that. When the retransmission control process is activated, the data transmitting / receiving apparatus 10 enters a reception process for the next MAC frame.

  On the other hand, if no error is detected in step S63, the PLC reception control circuit 50 checks whether or not the ACK / NACK flag is set (step S65 in FIG. 16). When the ACK / NACK flag is set, the PLC reception control circuit 50 causes the CPU 11 to start ACK / NACK transmission processing (step S66 in FIG. 16). When the ACK / NACK flag is not set, the PLC reception control circuit 50 performs the following process.

  After confirming the set of the ACK / NACK flag, the PLC reception control circuit 50 acquires the priority flag information of the received MAC frame (step S67 in FIG. 16). Based on the acquired priority flag information, the PLC reception control circuit 50 checks whether or not the priority processing MAC frame is set to be preferentially processed (step S68 in FIG. 16). If it is a priority processing MAC frame, the PLC reception control circuit 50 temporarily stores the priority processing MAC frame in the PLC reception memory 17 (step S69 in FIG. 16). When the storage of the priority processing MAC frame in the PLC reception memory 17 is finished, the PLC reception control circuit 50 confirms whether or not it can be output to the bridge interface circuit 13. The PLC reception control circuit 50 waits until output is possible when there is no empty area in the bridge memory 14 and transmission is impossible (step S70 in FIG. 16). When the output to the bridge interface circuit 13 becomes possible, the PLC reception control circuit 50 outputs the received MAC frame to the bridge interface circuit 13 in units of Ethernet frames (step S71 in FIG. 16). When the PLC reception control circuit 50 finishes transmitting the data for one MAC frame to the bridge interface circuit 13, it confirms the continuity between the processing SN and the SN of the MAC frame output to the bridge interface circuit 13 (step of FIG. 16). S72). In step S71, if the SN of the received MAC frame matches the stored processing SN (that is, if the continuity of SN is confirmed), the PLC reception control circuit 50 increments the processing SN. (Step S73 in FIG. 16). In step S71, if the SN of the received MAC frame is different from the stored processing SN (that is, if the continuity of SN is not confirmed), the PLC reception control circuit 50 sets the SN of the priority processing MAC frame. It is stored as the priority processed SN (step S74 in FIG. 16) (for example, see the case of SN = N + 4 in FIG. 15). When the operation of step S73 or S74 is completed, the process proceeds to a determination process for determining whether it is a reception time (step S60 in FIG. 16).

  On the other hand, as a result of the determination in step S68, if it is determined that the MAC frame is not set to be preferentially processed, the PLC reception control circuit 50 confirms continuity with the SN of the received MAC frame (step in FIG. 17). S75). In step S75, if the SN of the received MAC frame matches the stored processing SN (that is, if the continuity of the SN is confirmed), the PLC reception control circuit 50 converts the received MAC frame into Once stored in the PLC reception memory 17 (step S80 in FIG. 17). If there is no empty area in the bridge memory 14 and transmission is impossible, the PLC reception control circuit 50 waits until output is possible (step S81 in FIG. 17). When the output to the bridge interface circuit 13 becomes possible, the PLC reception control circuit 50 outputs the received MAC frame to the bridge interface circuit 13 in units of Ethernet frames (step S82 in FIG. 17). When the transmission of data for one MAC frame to the bridge interface circuit 13 is completed, the PLC reception control circuit 50 increments the processing SN of the MAC frame that has been transmitted to the bridge interface circuit 13 (step S83 in FIG. 17).

  Subsequently, the PLC reception control circuit 50 checks whether or not the processing SN matches the priority processing SN (step S84 in FIG. 17). When the matching between the processing SN and the priority processing completed SN is confirmed, the PLC reception control circuit 50 performs the processing of incrementing the processing SN (step S83 in FIG. 17), and the processing SN and the priority processing completed SN again. It is confirmed whether or not they match (step S84 in FIG. 17). The PLC reception control circuit 50 performs the processing of step S84 and step S83 until the coincidence between the processing SN and the priority processing SN is not confirmed.

  In step S84, when the match between the processing SN and the priority processed SN is not confirmed, or when the continuity confirmation by the increment of the processing SN is finished, the PLC reception control circuit 50 performs the PLC reception memory 17. It is confirmed whether or not there is received data (step S85 in FIG. 17). When there is no reception data in the PLC reception memory 17, the PLC reception control circuit 50 returns the process to step S60 and determines whether it is the reception time. On the other hand, if there is reception data in the PLC reception memory 17 in step S85, the PLC reception control circuit 50 checks the continuity of the SN between the processing SN and the MAC frame stored in the PLC reception memory 17. Therefore, it is confirmed whether or not the SN of the received MAC frame matches the processing SN (step S86 in FIG. 17). When it is confirmed that the SN of the received MAC frame matches the process SN, the PLC reception control circuit 50 returns the process to step S81 and performs the processes of steps S81 to S86 again. If it is determined in step S86 that the SN of the received MAC frame does not match the processing SN, the PLC reception control circuit 50 returns the processing to step S60 and determines whether it is a reception time. To do.

  Next, the PLC reception control circuit 50 confirms whether or not the MAC frame is set to be preferentially processed based on the priority flag information (step S68 in FIG. 16) and has received the processing SN. A processing flow when it is not confirmed that the SN of the MAC frame matches (step S75 in FIG. 17) will be described. The SN of the received MAC frame is compared with the size of the processing SN (step S76 in FIG. 17). If the SN of the received MAC frame is smaller than the processing SN, the PLC reception control circuit 50 discards the received MAC frame. Then, the process returns to step S60 to determine whether it is the reception time. On the other hand, when the SN of the received MAC frame is larger than the processing SN in step S76, the PLC reception control circuit 50 temporarily stores the received MAC frame in the PLC reception memory 17 (step S78 in FIG. 17). After that, the PLC reception control circuit 50 performs the same process as the delivery confirmation determination described in detail in the first embodiment (step S79 in FIG. 17).

  After completion of the delivery confirmation determination in step S79, the PLC reception control circuit 50 determines whether there is a MAC frame stored in the PLC reception memory 17 for a predetermined period (one frame period in the second embodiment). (Step S87 in FIG. 17). When there is a MAC frame stored in the PLC reception memory 17 for a predetermined period, the PLC reception control circuit 50 controls to delete the MAC frame (step S88 in FIG. 17). After completion of the deletion, the PLC reception control circuit 50 determines whether it is a reception time (step S60 in FIG. 16). If there is no MAC frame stored for a predetermined period, the PLC reception control circuit 50 determines whether it is the reception time (step S60 in FIG. 16).

  As described above, if the data transmission / reception apparatus (data transmission / reception method) according to the second embodiment is used, when the Go-Back-N method is adopted for retransmission control, an error occurs in the MAC frame received by the receiving terminal. On the other hand, due to the priority processing operation on the receiving terminal side based on the priority flag information, normality of this error data by retransmission control is performed for data such as VoIP that has a large data delay amount restriction (requires real-time property). Therefore, there is an effect that unnecessary delays can be suppressed without waiting for unnecessary reception.

  In other words, the terminal that has received the priority processing MAC frame shown as the MAC frame having the SN of N + 4 in FIG. 15 has the processing SN of N + 2 different from N + 4 that is the SN of the priority processing MAC frame. Even so, the process of outputting the priority processing MAC frame to the bridge interface circuit 13 is preferentially executed. For this reason, unnecessary delay does not occur in the relay of the priority processing MAC frame requiring real-time property. Further, the terminal that has received the priority processing MAC frame shown as the MAC frame having the SN of N + 6 in FIG. 15 outputs the retransmission control when an error is detected in the MAC frame having the SN of N + 6. However, since the retransmission control is canceled, the MAC frame having the SN of N + 6 is discarded and stored as the preferentially processed SN, real-time characteristics are required, and the importance is lost when it is delayed, such as VoIP In data transmission, there is an advantage that it is not necessary to relay a priority processing MAC frame that does not need to be transmitted.

  In the second embodiment, points other than those described above are the same as those in the first embodiment.

Embodiment 3 FIG.
In the first and second embodiments, the data receiving apparatus and the data receiving method of the present invention have been described in detail. However, the present invention is not limited to other data receiving apparatuses and other data receiving apparatuses that perform the processing shown in the flowchart of FIG. It is also applicable to the method.

  In the third embodiment, it is necessary to preferentially pass an SN indicating the continuity of data transmitted via this network and data received at the receiving side to a higher layer, connected to the network including the management terminal 1. A data receiving method for receiving and relaying data to which header information including priority flag information indicating whether or not it is a certain priority processing MAC frame through a network will be described. In the data receiving method of the third embodiment, terminal A performs an error determination on the MAC frame as the received data (step S1), and if it is determined that there is no error in this error determination, the received data is a priority processing MAC frame. It is determined whether or not (step S2).

  If it is determined in step S2 that the priority processing MAC frame is not a priority processing MAC frame, the terminal A determines whether or not the received MAC frame has SN continuity (step S3). Whether the received MAC frame has SN continuity is determined by the same method as in the first or second embodiment.

  When it is determined that there is continuity in the SN in step S3, the terminal A performs processing (relay) to output the received MAC frame to the bridge interface circuit 13 (step S4). The process SN is incremented (step S5) (for example, refer to SN = N + 1 in FIG. 10 or SN = N + 1 in FIG. 15), and then the process proceeds to step S1. On the other hand, if it is determined in step S3 that there is no continuity (for example, see SN = N + 3 in FIG. 10 or SN = N + 3 in FIG. 15), terminal A Saving or discarding is performed (step S6), and then the process proceeds to step S1.

  In step S6, in the case of the SR retransmission control method, when the SN of the received MAC frame indicates received data later in time than the stored processing SN (that is, the SN of the received MAC frame is stored). The received MAC frame is stored in the PLC reception memory 17 (see, for example, SN = N + 3 and N + 5 in FIG. 10), and the received MAC frame SN is stored in the process SN When the received data before the SN is indicated (that is, when the SN of the received MAC frame is smaller than the stored processing SN), the received MAC frame is discarded (or temporarily stored in the PLC reception memory 17). Discard after storage. Then, when the SN of the received MAC frame indicates received data that is temporally later than the stored processing SN, when the MAC frame having the same SN as the processing SN is stored in the PLC reception memory 17, A process of relaying the MAC frame stored in the PLC reception memory 17 is performed.

  In step S6, in the case of the Go-Back-N retransmission control method, when the SN of the received MAC frame is different from the stored processing SN, the received MAC frame is discarded (for example, FIG. 15). (See SN = N + 3).

  The processes from steps S1 to S6 are processes when the received data is a MAC frame other than the priority processing MAC frame and there is no error.

  In the determination of the priority processing data in step S2, if it is determined that the received data is a priority processing MAC frame, the terminal A preferentially processes the priority processing MAC frame (the bridge interface preferentially without being affected by the processing SN). Output to the circuit 13 (step S7), and manage (store) the SN of the priority-processed MAC frame as the priority-processed SN (step S8) (for example, SN = N + 4 in FIG. 10 or SN = N + 4 in FIG. 15). Then, the process returns to step S1.

  If it is determined that there is an error in the error determination of the MAC frame in step S1, the terminal A transmits a retransmission request for the MAC frame (step S9), and then moves the process to step S1 (for example, (See SN = N + 2 in FIG. 10 or SN = N + 2 in FIG. 15). In step S9, if the MAC frame is a priority processing MAC frame, the retransmission control is withdrawn, and the SN of the priority processing MAC frame determined to have an error is managed as the priority processing completed SN (for example, FIG. 10). (See SN = N + 10 or SN = N + 6 in FIG. 15).

  The details of the data receiving apparatus and data receiving method of the third embodiment are as described in the data receiving apparatus and data receiving method of the first or second embodiment.

  If the data receiving apparatus or the data receiving method according to the third embodiment is used and there is a MAC frame that cannot be normally received, and the priority processing MAC frame having a large data delay restriction is subsequently received normally, the priority processing MAC The effect is that the frame can be processed without delay.

Explanation of modification.
In the first to third embodiments, the case where communication between data transmitting / receiving apparatuses (terminals) is performed via a network using a high-speed PLC has been described. However, the present invention is limited to an apparatus and method applied to a high-speed PLC. However, the present invention can be applied to a network employing a wireless LAN system, a UWB (ultra-wideband wireless) system, or another transmission system that employs a TDMA system. The same effect can be achieved.

  In the first to third embodiments, the continuity of data is confirmed using the SN added to the MAC frame, and the receiving terminal uses the priority flag information added to the MAC frame. Confirmed whether or not to perform priority processing. However, in the present invention, the SN that is information indicating the continuity of data includes the reference signal that can confirm the continuity of the received MAC frame and has substantially the same function as the SN. In the present invention, priority flag information, which is information indicating whether or not priority processing data is used, is a signal that is not called priority flag information as long as it can be identified as priority processing data. For example, it also includes header information capable of recognizing MAC frame data such as VoIP that performs priority processing.

It is a figure which shows roughly the structure of the high-speed PLC network system which implements the data reception method which concerns on Embodiment 1 thru | or 3 of this invention. It is a block diagram which shows roughly the structure of the data transmitter / receiver which can be used as a terminal of the high-speed PLC network system shown by FIG. FIG. 3 is a block diagram schematically showing a configuration of a PLC modem circuit in the data transmission / reception apparatus shown in FIG. 2. FIG. 4 is a block diagram schematically showing a configuration of a PLC reception control circuit in the PLC modem circuit shown in FIG. 3. FIG. 4 is a block diagram schematically showing a configuration of a PLC reception control circuit in the PLC modem circuit shown in FIG. 3. The figure which shows schematically the structure of the data format in 1 frame at the time of performing data transmission / reception with the data transmission / reception apparatus which can be used as a terminal of the high-speed PLC network system in Embodiment 1 thru | or 3, and the schedule data in FCH It is. 6 is a flowchart showing an operation when a management terminal in Embodiments 1 to 3 generates a data transmission / reception schedule in one frame. 3 is a flowchart showing an operation when a transmission MAC frame is generated by a data transmission / reception device as a terminal of the high-speed PLC network system in the first embodiment. 6 is a diagram schematically showing a data format configuration in one MAC frame when data is transmitted / received by a data transmitting / receiving apparatus as a terminal of the high-speed PLC network system in Embodiments 1 to 3. FIG. 6 is a timing chart showing an operation when the SR retransmission control method is adopted in the data transmitting / receiving apparatus as a terminal of the high-speed PLC network system in the first embodiment. 6 is a flowchart showing an operation in each terminal of the high-speed PLC network system in the first to third embodiments. 6 is a flowchart (part 1) illustrating an operation when data is received by a data transmission / reception device as a terminal of the high-speed PLC network system according to the first embodiment. 6 is a flowchart (part 2) illustrating an operation when data is received by the data transmission / reception apparatus as a terminal of the high-speed PLC network system according to the first embodiment. 6 is a flowchart showing an operation when determining whether or not the MAC frame data received by the data transmitting / receiving apparatus as the terminal of the high-speed PLC network system according to the first to third embodiments is delivery confirmation unnecessary data. 6 is a timing chart showing an operation when a Go-Back-N retransmission control method is adopted in a data transmitting / receiving apparatus as a terminal of a high-speed PLC network system in the second embodiment. 6 is a flowchart (part 1) illustrating an operation when data is received by a data transmitting / receiving apparatus as a terminal of the high-speed PLC network system according to the second embodiment. 12 is a flowchart (part 2) illustrating an operation when data is received by a data transmission / reception device as a terminal of the high-speed PLC network system according to the second embodiment. 14 is a flowchart showing an operation of the data receiving apparatus according to the third embodiment (that is, a data receiving method according to the third embodiment).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Management terminal 2, 4, 6, 8 Outlet, 3 Terminal A, 5 Terminal B, 6 Terminal C, 9 Power line, 10 Data transmission / reception apparatus, 11 CPU, 12 Ethernet interface circuit, 13 Bridge interface circuit, 14 Bridge use Memory, 15 PLC modem circuit, 16 PLC transmission memory, 17 PLC reception memory, 18 CPU bus, 20 Ethernet interface input terminal, 21 Ethernet interface output terminal, 22 PLC modem circuit output terminal, 23 PLC modem circuit input terminal, 40 PLC transmission control circuit, 50 PLC reception control circuit, 30 PLC transmission control circuit data input terminal, 31 PLC reception control circuit data output terminal, 401 PLC header generation circuit, 402 packet data generation circuit, 4 3 encryption circuit, 404, 406 selector, 405 PLC header addition circuit, 407 PLC transmission timing generation circuit, 408 PLC network control data generation circuit, 409 PLC transmission memory control circuit, 410 CRC encoding circuit, 501 PLC header analysis circuit, 502 CRC decoding circuit, 503 encryption / decryption circuit, 504 PLC control frame separation circuit, 505 PLC control frame storage circuit, 506 PLC reception memory control circuit, 507 PLC reception timing generation circuit.

Claims (18)

Is it priority processing data that is connected to the network including the management terminal and needs to preferentially pass the sequence number indicating the continuity of data transmitted through the network and the data received on the receiving side to the upper layer A data receiving device that receives and relays data with header information including priority information indicating whether or not through the network,
A reception timing generation means for generating a reception timing of the reception data based on a schedule output from the management terminal;
Data reception determination means for determining whether or not the reception data is normally received at the reception timing;
Receiving header analysis means for extracting and analyzing the sequence number and the priority information from the header information at the reception timing;
Based on the determination result by the data reception determination means and the analysis result of the sequence number and the priority information by the reception header analysis means, a processing sequence number indicating the sequence number of received data to be relayed next is stored. Receiving data control means,
The reception data control means determines whether the reception data is priority processing data when the determination result by the data reception determination means is a determination result that the reception data has been normally received, When it is determined that the received data is priority processing data, the received data determined to be the priority processing data is preferentially relayed without being affected by the stored processing sequence number. A data receiving device.   2. The data receiving apparatus according to claim 1, wherein the reception data control means increments the processing sequence number when a process of relaying the reception data is performed.   The reception data control means stores a priority processed sequence number indicating a sequence number of the priority processing data when performing processing for preferentially relaying the reception data determined to be the priority processing data. The data receiving device according to claim 1 or 2.   The received data control means performs control for retransmitting data determined not to be normally received when the received data is determined not to be normally received data. The data receiving device according to claim 1.   The received data control means determines that the received data is not normally received data, and if the received data is priority processing data, the priority is determined not to be normally received data. 5. The priority processing sequence number indicating the sequence number of the priority processing data determined not to be normally received data is stored by canceling control for retransmitting the processing data. Data receiving device. Receiving means for storing the received data,
The received data control means determines that the received data is normally received data and the received data is data other than the priority processing data.
When the sequence number of the received data indicates received data that is temporally later than the stored processing sequence number, the received data is stored in the receiving storage means,
6. The received data is discarded when the sequence number of the received data indicates received data temporally prior to the stored processing sequence number. Data receiver.   The received data control means stores the sequence number of the received data when the received data is determined to be normally received data and the received data is data other than the priority processing data. When data having the same sequence number as the processing sequence number is stored in the receiving storage means when the received data after the processing sequence number is temporally indicated, the data is stored in the receiving storage means. The data receiving device according to claim 6, wherein the data relaying process is performed.   The received data control means stores the sequence number of the received data when the received data is determined to be normally received data and the received data is data other than the priority processing data. 6. The data receiving device according to claim 1, wherein the received data is discarded when the processing sequence number is different from the received processing sequence number. The received data control means stores the sequence number of the received data when the received data is determined to be normally received data and the received data is data other than the priority processing data. If the processing sequence number stored in the reception data control means is the same as the priority processed sequence number when the received data after the processing sequence number is temporally indicated, the processing sequence number The data receiving apparatus according to claim 6, wherein the data receiving apparatus is incremented. Is it priority processing data that is connected to the network including the management terminal and needs to preferentially pass the sequence number indicating the continuity of data transmitted through the network and the data received on the receiving side to the upper layer A data reception method for receiving and relaying data with header information including priority information indicating whether or not through the network,
Generating reception timing of received data based on a schedule output from the management terminal;
Determining whether or not the received data has been normally received at the reception timing;
Extracting and analyzing the sequence number and the priority information from the header information at the reception timing; and
A step of storing a processing sequence number indicating a sequence number of received data to be relayed next based on a determination result of whether or not the reception is normal, and an analysis result of the sequence number and the priority information;
When the determination result of whether or not the reception is normal is a result that the reception data is normally received, it is determined whether or not the reception data is priority processing data, and the reception data is priority processing data. And a step of preferentially relaying the received data determined to be the priority processing data without being influenced by the stored processing sequence number. Data receiving method.   11. The data receiving method according to claim 10, wherein the processing sequence number is incremented when processing for relaying the received data is performed.   11. A priority-processed sequence number indicating a sequence number of the priority processing data is stored when a process of preferentially relaying the received data determined to be the priority processing data is performed. The data receiving method according to any one of 11.   13. When it is determined that the received data is not normally received data, control is performed to retransmit the data determined not to be normally received. The data receiving method according to any one of the above.   When it is determined that the received data is not normally received data and the received data is priority processing data, control for retransmitting the priority processing data determined not to be normally received data 14. The data receiving method according to claim 13, further comprising storing a priority processed sequence number indicating a sequence number of priority processing data determined not to be normally received data. When it is determined that the received data is normally received data and the received data is data other than the priority processing data,
When the sequence number of the received data indicates received data that is temporally later than the stored processing sequence number, the received data is stored in the receiving storage means,
The received data is discarded when the sequence number of the received data indicates received data temporally prior to the stored processing sequence number. Data receiving method.   When the received data is determined to be normally received data and the received data is data other than the priority processing data, the received data control means stores the sequence number of the received data. When the received data that is later in time than the processing sequence number is stored and the data having the same sequence number as the processing sequence number is stored in the receiving storage means, the data is stored in the receiving storage means. The data receiving method according to claim 15, wherein the data relaying process is performed.   When the received data is determined to be normally received data and the received data is data other than the priority processing data, the received data control means stores the sequence number of the received data. 15. The data receiving method according to claim 10, wherein the received data is discarded when the processing sequence number is different from the received processing sequence number.   When it is determined that the received data is normally received data, and the received data is data other than the priority processing data, the sequence number of the received data is greater than the stored processing sequence number. 18. The processing sequence number is incremented when the received processing sequence number is the same as the priority processing sequence number when the received data is shown later in time. The data receiving method according to any one of the above.

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