JP2007324225A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of controlling a breakdown voltage to be the desired breakdown voltage by changing a design rule concerning the semiconductor device composed of a transistor with a MOS structure, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device having the MOS structure includes: a channel dope layer, and an impurity layer which is arranged adjacent to the channel dope layer so as to form a drain. The breakdown voltage is set to the prescribed breakdown voltage by controlling the superimposition of the impurity layer on the channel dope layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a MOS structure transistor and a manufacturing method thereof.

  Semiconductor devices such as MOSFETs are used as control transistors for power supply devices and the like. Such a semiconductor device is required to have a high breakdown voltage.

The breakdown voltage between the drain and source of the MOSFET is affected by the concentration of the drain low concentration impurity layer and the back gate impurity layer. For this reason, in order to obtain a desired breakdown voltage in the MOSFET, the impurity concentration of the drain layer and the back gate layer is changed (see Patent Document 1).
JP-A-5-160400

  However, in order to obtain a desired breakdown voltage in the conventional semiconductor device, the impurity concentration of the drain layer and the back gate layer is changed. For this reason, since it is necessary to change the conditions of a manufacturing process, the manufacturing process increased or the operation | work which adjusts a manufacturing apparatus was needed and manufacturing efficiency was bad.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of controlling a breakdown voltage to a desired breakdown voltage by changing a design rule, and a method for manufacturing the same.

  In a semiconductor device having a MOS structure, the present invention includes a channel dope layer and an impurity layer that is disposed adjacent to the channel dope layer and forms a drain or source region, and the impurity layer and the channel dope layer overlap. Alternatively, a predetermined breakdown voltage is set by controlling the distance.

  The overlap or distance between the impurity layer and the channel dope layer is controlled by the shape of the impurity layer.

  The shape of the impurity layer is controlled based on the design rule of the impurity layer.

  In a method of manufacturing a semiconductor device having a MOS structure having a channel dope layer and a diffusion layer disposed adjacent to the channel dope layer and forming a drain, the impurity layer and the impurity layer The overlap with the channel dope layer is controlled, and the withstand voltage is set to a predetermined withstand voltage.

  The overlap between the diffusion layer and the channel dope layer is set by controlling the shape of the impurity layer.

  According to the present invention, a predetermined breakdown voltage is changed to a desired breakdown voltage by changing the design rule according to the breakdown voltage and controlling the overlap or distance between the impurity layer formed close to the channel dope layer and the channel dope layer. By setting, it is possible to set the breakdown voltage to a desired breakdown voltage without changing the process.

  FIG. 1 shows a block diagram of an embodiment of the present invention. 1A is a plan view and FIG. 1B is a cross-sectional view.

  The semiconductor device 100 of this embodiment is an n-channel MOS field effect transistor mounted on a low-concentration p-type well layer 112 formed on a p-type semiconductor substrate 111, and includes a low-concentration n-type impurity layer 113, a channel dope layer. 114, a high-concentration n-type impurity layer 115, a gate oxide film 116, a LOCOS (local oxidation of silicon) oxide film 117, and a gate electrode 118.

  The low-concentration n-type impurity layer 113 is an impurity diffusion layer that constitutes a drain and a source region, and is formed on both sides of the channel region A1 with the channel region A1 interposed therebetween.

  The channel dope layer 114 is a thin low-concentration n-type impurity layer formed immediately below the gate oxide film 116 in the channel region A1, and stabilizes the characteristics of the transistor.

  The high-concentration n-type impurity layer 115 is formed with the drain and source openings 121 of the low-concentration n-type impurity layer 113 and stabilizes the connection between the electrode and the drain and source regions.

  The gate oxide film 116 is formed on the channel region A1.

The LOCOS oxide film 117 is made of SiO ₂ , isolates and protects the element, and stabilizes the characteristics of the element. The gate electrode 118 is made of polysilicon or the like and is wired on the gate oxide film 116 to control the gate potential.

  This embodiment controls the distance between the low-concentration n-type impurity layer 113 and the channel dope layer 114 by controlling the lateral direction of the low-concentration n-type impurity layer 113 and the spread in the directions of the arrows X1 and X2. The withstand voltage is controlled to a desired withstand voltage.

  At this time, the lateral direction of the low-concentration n-type impurity layer 113 and the spread in the directions of the arrows X1 and X2 are controlled by, for example, the shape of the opening 211 of the resist 201 used when the low-concentration n-type impurity layer 113 is formed. .

  Therefore, the distance between the low-concentration n-type impurity layer 113 and the channel dope layer 114 can be controlled by arbitrarily setting the design rule of the opening 211 of the resist 201 used when forming the low-concentration n-type impurity layer 113. . By controlling the distance between the low-concentration n-type impurity layer 113 and the channel dope layer 114, the breakdown voltage changes.

  FIG. 2 is a diagram showing the characteristics of the withstand voltage BV with respect to the distance between the impurity layer 113 constituting the drain and source regions and the channel dope layer 114.

  As shown in FIG. 2, when the distance L between the impurity layer 113 and the channel dope layer 114 is increased, generation of hot carriers can be suppressed, so that the breakdown voltage BV can be increased.

  Next, a method for manufacturing the semiconductor device 100 will be described.

  3 and 4 are views for explaining a manufacturing process of the semiconductor device 100. FIG.

  First, as shown in FIG. 3A, a low concentration p-type well layer 112 is formed on a p-type semiconductor substrate 111, and a LOCOS oxide film 117 having an opening 121 is formed.

  Next, as shown in FIG. 3B, a resist 201 having an opening 211 is formed, and impurities are ion-implanted to form a low-concentration n-type diffusion layer 113. At this time, the position of the end of the low-concentration n-type impurity layer 113 on the channel region A 1 direction side can be changed by changing the shape of the opening 211 of the resist 201. Thereby, the overlap or the distance between the low-concentration n-type impurity layer 113 and the channel dope layer 114 can be changed. It is possible to set the breakdown voltage to a desired breakdown voltage by overlapping the low-concentration n-type impurity layer 113 and the channel dope layer 114 or changing the distance.

  Next, as shown in FIG. 4A, a gate oxide film 116 and a channel dope layer 114 are formed in the channel region A1.

  Next, as shown in FIG. 4B, a gate electrode 118 is formed on the channel region A1.

  Further, as shown in FIG. 4C, a high concentration n-type impurity layer 115 is formed in the region of the opening 121.

  The semiconductor device 100 is manufactured as described above.

  According to the present embodiment, the predetermined breakdown voltage is set to a desired breakdown voltage by changing the design rule according to the breakdown voltage and controlling the overlap between the impurity layer formed adjacent to the channel dope layer and the channel dope layer. By doing so, it is possible to set the withstand voltage to a desired withstand voltage without changing the process.

  In this embodiment, the example in which the breakdown voltage is set by controlling the distance between the low-concentration n-type impurity layer 113 and the channel dope layer 114 is described. However, the low-concentration n-type impurity layer 113, the channel dope layer 114, The withstand voltage may be set by controlling the overlap between the two.

  Here, for example, in a semiconductor device in which a low-concentration n-type impurity layer 113 having a depth of about 2 μm and a channel dope layer 114 overlap each other by about 0.4 μm, the breakdown voltage BV is 32 [V]. The low concentration n-type impurity layer 113 and the channel dope layer 116 can be raised to about 42 [V] by separating the distance L by about 0.4 μm.

  In addition, this invention is not limited to the said Example, A various modification can be considered in the range which does not deviate from the summary of this invention.

It is a block diagram of one Example of this invention. The figure which shows the characteristic of the proof pressure BV with respect to the distance of the impurity layer 113 which comprises a drain and a source region, and the channel dope layer 114 6 is a diagram for explaining a manufacturing process of the semiconductor device 100. FIG. 6 is a diagram for explaining a manufacturing process of the semiconductor device 100. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 111 P type semiconductor substrate, 112 Low concentration p-type well layer, 113 Low concentration n type impurity layer 114 Channel dope layer, 115 High concentration n type impurity layer, 116 Gate oxide film 117 LOCOS oxide film, 118 Gate electrode, 201 resist 211 opening

Claims (5)

In a semiconductor device having a MOS structure,
A channel doped layer;
An impurity layer disposed adjacent to the channel doped layer and forming a drain or source region;
A semiconductor device, wherein a predetermined breakdown voltage is set by controlling an overlap or distance between the impurity layer and the channel dope layer. The semiconductor device according to claim 1, wherein an overlap or distance between the impurity layer and the channel dope layer is controlled by a shape of the impurity layer. The semiconductor device according to claim 2, wherein the shape of the impurity layer is controlled based on a design rule of the impurity layer. In a method of manufacturing a semiconductor device having a MOS structure having a channel dope layer and an impurity layer disposed adjacent to the channel dope layer and forming a drain or source region,
A method of manufacturing a semiconductor device, wherein a design rule is changed according to a breakdown voltage to control an overlap or distance between the impurity layer and the channel dope layer and set a breakdown voltage to a predetermined breakdown voltage. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the overlap between the impurity layer and the channel dope layer is set by controlling a shape of the impurity layer.

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