JP2007317935A - Semiconductor substrate, substrate-dividing method, and element chip manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the accuracy, stability and reliability of division of a semiconductor substrate into a plurality of semiconductor chips. <P>SOLUTION: A test pattern 21 for inspecting the characteristics of a wiring 3 involved in an element chip 10a, and an alignment 20 which is capable of detection of a position of a semiconductor substrate, are formed on the semiconductor substrate. They are formed only on a first division predetermined line C1 for first division, among division predetermined lines for dividing the element chip 10a disposed on the semiconductor substrate. In division, a grooved surface processing mark is formed in a substrate surface along division predetermined lines C1, C2, and a group of inner cracks are formed by condensing laser light to the inside of the substrate. Thereafter, cracks connecting a linear processor and inner cracks are generated in a substrate rear, by applying a force directed toward a substrate surface side, thus separating each element chip 10a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate in which a plurality of wiring parts including a semiconductor element and the like are arranged and separated into individual element chips each including each wiring part, a substrate cleaving method for separating the semiconductor substrate into individual element chips, and a substrate cleaving The present invention relates to an element chip manufacturing method including a process.

  As a method of precisely cutting a semiconductor substrate such as a silicon wafer into individual element chips, particularly when the element chip includes a fine structure such as an ink jet nozzle, it is possible to prevent fine particles from being mixed as dust inside the nozzle. Is required. Therefore, especially in a semiconductor substrate having a wiring portion including a fine structure portion, cutting is performed by mixing semiconductor substrate and abrasive fine particles, adhesive particles of an adhesive tape for fixing the semiconductor substrate and the processing table, etc. mixed with cooling water. It is desirable to carry out in a dry environment that does not scatter.

As such a substrate cutting method, Patent Document 1 discloses a method in which a workpiece is split after being processed by laser light. That is, in this method, a laser beam having a specific wavelength that is highly transmissive to the workpiece is focused on a predetermined portion inside the workpiece to form a modified region. Thereafter, by applying stress to the workpiece, the crack is expanded starting from the modified region, and the workpiece is separated along a desired scribe line.
JP 2003-334675 A

  In many semiconductor exposure apparatuses used in the cleaving method as described above, alignment marks for alignment are provided on the mask and the substrate surface, and position information obtained from them is used to align the mask and the substrate. It is carried out. This alignment mark is provided on the scribe line in the substrate. Furthermore, in addition to the alignment marks, a test pattern called a TEG (Test Element Group) for confirming basic characteristics of a semiconductor element is generally arranged on the scribe line.

  Such alignment marks and test patterns are generally formed from metal deposits. For this reason, as described above, when a modified region is formed by exposing a portion corresponding to a scribe line inside a semiconductor element, the metal deposits constituting the alignment mark and the test pattern on the scribe line affect the exposure. give. That is, the optical path of the laser beam is partially blocked by the metal deposit, and a portion where the modified region is to be formed is not sufficiently modified, or a portion where the modified region is not formed occurs. Thus, when the part in which the modified region is not formed satisfactorily occurs, there is a possibility that good cleaving may be inhibited.

  Further, in the method disclosed in Patent Document 1, as described above, only the modified region inside the substrate becomes the base point of the crack, so that the position where the crack reaches the substrate surface tends to be unstable. On the other hand, it may be required to be able to set the separation position on the substrate surface more precisely.

  The present invention has been made in view of the prior art as described above, and after performing a process of condensing the laser beam inside the substrate, in the substrate cleaving method for breaking the substrate and separating it, The purpose is to improve stability and reliability.

  In order to achieve the above object, the element chip manufacturing method of the present invention includes a step of forming a plurality of wiring portions on the surface of the semiconductor substrate and a test for inspecting the characteristics of the wiring portions on the surface of the semiconductor substrate. A step of forming at least one of the pattern and an alignment pattern for enabling detection of the position of the semiconductor substrate, and then separating the semiconductor substrate into a plurality of element chips each including a wiring portion. In the chip manufacturing method, the step of separating into a plurality of element chips intersects at least one first cutting planned line for separating into element chips on the surface of the semiconductor substrate, and the first cutting planned line. A step of forming a groove-shaped linearly processed portion along at least one second planned cutting line, and a laser at a condensing point at a predetermined depth along the planned cutting line inside the semiconductor substrate. The process of forming an internal crack extending in the depth direction by concentrating and forming a group of cracks along the planned cutting line by repeatedly forming the internal crack, and applying a force toward the front side on the back surface of the semiconductor substrate And forming a crack connecting the linear processed portion and the internal crack, and cleaving the semiconductor substrate along the first planned cutting line, and cleaving along the first planned cutting line, and then on the back surface of the semiconductor substrate. Applying a force toward the surface side to generate a crack that connects the linearly processed portion and the internal crack, and cleaving the semiconductor substrate along the second planned cutting line, and having a test pattern and an alignment pattern The step of forming at least one of the above is performed only on the first planned cutting line.

  According to the present invention, it is possible to improve cleaving accuracy, stability, and reliability. Moreover, the cleaving position on the substrate surface can be set to the position of the linearly processed portion.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 and 2 are schematic views showing a silicon substrate 10 which is a semiconductor substrate to be divided into a plurality of element chips 10a in the present embodiment. 1A is a perspective view of the entire silicon substrate 10, FIG. 1B is an enlarged perspective view of the element chip 10a portion, and FIG. 1B is a cross-sectional view. These drawings also schematically show a planned cutting line C for separation into individual element chips 10a. FIG. 2 is a plan view showing the parting line C portion in more detail.

  The silicon substrate 10 is based on a silicon wafer 1 having a surface of (100) orientation and a thickness of 625 μm. As shown in FIG. 1C, an oxide film 2 having a thickness of about 1 μm is formed on the surface of the silicon wafer 1. The element chip 10a manufactured in the present embodiment constitutes a discharge mechanism for a liquid such as ink, which is mounted on the inkjet head. On the substrate surface 11, a plurality of nozzle layers, which are epoxy resin structures containing liquid discharge elements, logic elements for driving them, wiring, and the like, are arranged to form each wiring portion 3. ing.

  In this manner, a liquid supply port (ink supply port) 4 is formed as a through hole of the silicon wafer 1 by anisotropic etching of the silicon wafer 1 immediately below the wiring portion 3 incorporating the liquid discharge mechanism and the like. Yes. The wiring part 3 is disposed with a planned cutting line C interposed therebetween so that the silicon wafer 1 can be cut into the element chips 10a at the final stage of the manufacturing process.

  As shown in FIG. 2, the element chip 10a in the present embodiment has a rectangular shape, and the cleaving line C has a plurality of first cleaving lines C1 extending along the short side of each element chip 10a and the long side. A plurality of second cutting lines C2 extending along the intersection intersect with each other and are set in a lattice shape. These planned cutting lines C1 and C2 extend in directions orthogonal to each other with reference to the orientation flat 10b of the silicon wafer 1.

  On the planned cutting line C, an alignment pattern 20 that can detect the position of the silicon substrate 10 and is used for alignment of the silicon substrate 10 with a mask for the exposure is formed. A test pattern (TEG) 21 for confirming the characteristics of the wiring part 3 is also formed on the planned cutting line C. The alignment pattern 20 and the test pattern 21 are made of a metal deposit, and are formed only on the first cutting planned line C1 while avoiding the second cutting planned line C2.

  Next, a cleaving procedure for separating the silicon substrate 10 into individual element chips 10a including the respective wiring portions 3 will be described. As shown in FIG. 3, this cleaving procedure is composed of seven steps: a tape mounting step, a wafer correction step, a surface linear processing step, an internal crack formation step, a cleaving step, a repair step, and a pick-up step. Hereinafter, each process is demonstrated in order.

"Tape mounting process" (Step 1)
First, tape mounting is performed in order to prevent the element chip 10a from being separated from the silicon substrate 10 until the cleaving step. As shown in FIG. 4, the tape mount is performed by attaching an adhesive dicing tape T with a dicing frame M attached to the back surface of the silicon substrate 10 (opposite to the surface on which the wiring portion 3 is formed). . As the dicing tape T, an adhesive tape coated with an ultraviolet curable or pressure sensitive adhesive, or an adhesive tape having a self-adhesive layer can be used.

"Wafer correction (warp correction) process" (Step 2)
As described above, the wiring layer 3 in the present embodiment has a structure made of a resin layer formed on the substrate surface 11 of the silicon substrate 10, and causes thermal contraction when cured. Is entirely deformed as shown in FIG. When laser irradiation described later is performed in such a deformed state, the incident angle changes for each incident position on the substrate surface 11 and it becomes difficult to process with high accuracy. Therefore, it is preferable to correct this deformation in advance. Therefore, as shown in FIG. 5B, the silicon substrate 10 is sucked onto the flat suction stage D from the dicing tape T side to flatten the silicon substrate 10 and correct the deformation.

"Surface linear processing process" (Step 3)
Subsequently, a groove-shaped surface processing mark (linear processing portion) 11 a is formed on the substrate surface 11 along the planned cutting line C. As will be described later, the surface processing mark 11a serves to cause a crack separating the element chips 10a of the silicon substrate 10 to be located on the planned cutting line C on the substrate surface 11 when cleaving.

  As shown in FIG. 6, the surface processing mark 11 a can be formed by marking the surface with a scriber using a tool 40 such as cemented carbide or diamond along the cutting line C. The surface processing mark 11a preferably has a width of 2 μm or more and a depth of 1 μm or more. However, it is necessary to have a size that does not hinder the optical path of the laser beam L for processing the internal crack 12 described later. The processing depth is preferably set so that stress concentration occurs between the surface processing mark 11a and the internal crack 12 during cleaving. The depth of the surface processing mark 11a may be smaller than the thickness of the oxide film 2 which is the surface layer of the silicon substrate 10 as shown in FIG. 6A, or the oxidation depth as shown in FIG. There is no problem even if the thickness is equal to or larger than the thickness of the film 2.

  The surface processing mark 11a is essential for at least the substrate surface 11 having the wiring portion 10a, but may be formed on both the front surface side and the back surface side of the silicon substrate 10.

  Moreover, when forming the surface processing mark 11a by scribing using the tool 30, by forming the surface processing mark 11a before forming an internal crack, which will be described later, as in this embodiment, it is unnecessary due to the processing load. Cracks can be avoided. Further, by forming the surface processing mark 11a first, the surface processing mark 11a itself can be used as a reference (line) indicating a processing position at the time of laser irradiation in a subsequent process, and the work efficiency of laser irradiation is improved. be able to. However, the surface processing mark 11a may be formed after the internal crack formation step by the laser beam L. In this case, since there is no influence of the vignetting of the laser beam when the internal crack is formed (the phenomenon that the concave slope of the surface of the surface processing mark 11a reflects the irradiated laser beam and the amount of the laser beam reaching the inside of the substrate decreases) Internal crack formation can be performed more efficiently.

"Internal crack formation process" (Step 4)
Next, the internal crack 12 is formed using the processing apparatus 50 shown to Fig.7 (a). This processing apparatus 50 includes an X stage 53a, a Y stage 53b, and a fine movement adjustment stage 53c, and an automatic stage 53 that adjusts the position of the mounted workpiece W in the XY direction (direction parallel to the surface on which the workpiece W is placed). It has. A condensing optical system 52 having a microscope objective lens 52a, a mirror 52b and the like is disposed above the automatic stage 53. A light source optical system having a light source 51, a beam expanding system 51 a, a mirror 51 b, and the like is optically connected to the condensing optical system 52, so that irradiation light from the light source 51 passes through the condensing optical system 52. Is irradiated onto the workpiece W. The condensing optical system 52 is mounted on the Z stage 52c and is movable in the Z direction (a direction perpendicular to the surface of the automatic stage 53 on which the workpiece W is placed).

  In the present embodiment, the silicon substrate 10 is mounted on the automatic stage 53 as the workpiece W. The processing apparatus 50 also includes an alignment optical system (not shown) that performs alignment using the orientation flat 10b (see FIG. 1) of the mounted silicon substrate 10.

  The condensing optical system 52 has an observation camera 52d so as to be conjugate with the workpiece irradiation point. At this time, since the reflectance of the silicon substrate 10 is about 30% as will be described later, a filter corresponding to the output of the laser is arranged, although not shown. Thereby, it is possible to suppress the observation camera 52d from being damaged by the influence of the reflected light. As the illumination for observation, a relay lens is used, and a light source is formed at the position of the entrance pupil of the microscope objective lens 52a used for condensing to perform Koehler illumination. In addition, this illumination is also performed through a filter to eliminate damage to the illumination optical element as much as possible.

  In addition to the above observation optical system, an AF optical system 54 is also provided. The AF optical system 54 obtains the contrast of the image obtained by the observation camera 52d, and determines the focus and inclination from the value. By using this AF optical system 54, it is possible to perform an AF operation of measuring the contrast while finely feeding the distance to the workpiece W and determining the best position. Regarding this AF operation, it is determined whether or not to use it by looking at the parallelism of the workpiece W or the like.

  As the light source 51, a fundamental wave (1064 nm) of a pulse YAG laser is used. The pulse width is around 15 to 700 ns, and the pulse frequency is 10 to 100 KHz. The excitation source of this laser is a semiconductor laser, and the power of this excitation laser can be changed by the injection current to the semiconductor laser. The pulse width can be changed by changing the amount and frequency of the injected current.

  The laser beam is selected according to the spectral transmittance of the silicon substrate 10. That is, light having a wavelength range that is transmissive to the silicon substrate 10 and capable of forming a strong electric field at the condensing point may be selected, and any wavelength range that satisfies this condition may be selected. It doesn't matter. For example, a laser beam having a wavelength of 1.3 to 1.5 μm, which is generated by combining an ultrashort pulse and a wavelength conversion unit, can be used.

  The laser light L emitted from the light source 51 enters the condensing optical system 52 through the beam expanding system 51a and the like. As the microscope objective lens 52a of the condensing optical system 52, for example, a lens having a magnification of 20NA0.42 or a magnification of 50NA0.55 is used. In addition, in consideration of the refractive index of the silicon substrate 10, a condensing lens that is applicable to microscopic observation and is optimal for silicon internal processing can also be used.

  The laser light L condensed by the condensing optical system 52 is incident from the substrate surface 11 of the silicon substrate 10 which is the work W on the automatic stage 53 as shown in FIG. The optical conditions at this time are set so that no problem occurs even if the surface processing mark 11 a exists on the substrate surface 11. That is, measures are taken such as increasing the power in consideration of energy loss due to the surface processing mark 11a, or selecting a light beam that is incident while avoiding the surface processing mark 11a.

  The light beam incident from the substrate surface 11 is refracted in the silicon substrate 10 and is condensed at a condensing point A at a predetermined depth position a inside. The depth position a of the condensing point A can be controlled by moving either the silicon substrate 10 or the condensing optical system 52 in the optical axis direction and shifting the condensing position.

  When the refractive index of the silicon substrate 10 with respect to the laser beam L is n and the relative movement amount of the silicon substrate 10 and the condensing optical system 52 in the optical axis direction is d, the optical movement amount of the condensing point A. The theoretical value of nd is nd. The refractive index of the silicon substrate 10 is in the vicinity of 3.5 with respect to a laser beam having a wavelength of 1.1 to 1.5 μm, and the value actually estimated by experiment is also close to 3.5. Therefore, by changing mechanically the relative position between the silicon substrate 10 and the condensing optical system 52 from the position where the light is focused on the surface of the silicon substrate 10 by 100 μm, the condensing point A of the laser beam is 350 μm from the surface. Can be in the position.

At this time, the fact that the refractive index is in the vicinity of 3.5 indicates that the reflectance is quite large. That is, in general, the reflectance at normal incidence is ((n−1) / (n + 1)) ² , so that it is about 30% in the silicon substrate. Although the remaining energy reaches the inside, since the silicon substrate also absorbs light, the final energy reaching the condensing point A is further reduced. When measured on a 625 μm thick silicon substrate, the transmittance was about 20%.

  When the laser beam L is condensed at the condensing point A, the crystalline state of silicon partially changes, and as a result, the internal crack 12 is formed. In the experimental results, it was confirmed that the internal crack 12 ran below the condensing point A, that is, farther from the incident side of the laser beam L, and the crack length b was about 50 to 100 μm.

  In this way, the internal crack 12 is formed from one point inside the silicon substrate 10, and the condensing point A is moved in the depth direction and along each planned cutting line C, so Internal processing is performed to form internal cracks 12 in a predetermined pattern. The condensing point A can be moved in the XY direction (direction parallel to the substrate surface 11) by moving the silicon substrate 10 by the automatic stage 53. Further, the condensing point A can be moved in the Z direction (depth direction, thickness direction of the silicon substrate 10) by moving the condensing optical system 52 by the Z stage 52c. Alternatively, a mechanism for moving the silicon substrate 10 side in the Z direction or a mechanism for moving the condensing optical system 52 side in the XY direction may be provided.

  In this internal processing, as shown in FIG. 8, in the vicinity of the end point of the silicon substrate 10 as the workpiece W, the incident path of the laser light L is partially different from the central portion, and is harder to process than the central portion. For this reason, when processing the vicinity of the end point, it is preferable to adjust processing conditions such as increasing the laser energy at the center of the silicon substrate 10.

  Moreover, as shown in FIG. 9, the cutting planned lines C1 and C2 extending in the two cutting directions respectively intersect at an intersection C12. In the vicinity of the intersection C12, the laser beam is disturbed by the internal crack 12 formed by the internal processing first, when the internal processing is performed later on the planned cutting lines C1 and C2. This is a phenomenon that occurs locally instead of the entire planned cutting line C on the side where internal machining is performed later. Therefore, considering the energy loss due to this phenomenon, the machining conditions are changed in the vicinity of the intersection C12, or the machining conditions for the planned cutting line C on the side where the internal machining is performed first and the side where the internal machining is performed later. It is desirable to change

  In the present embodiment, the cleaving on the first cleaving planned line C1 side is performed first in the cleaving step described later. In this case, it is preferable to perform the internal processing on the second cutting planned line C2 side first. Thereby, it is possible to suppress the internal crack 12 from becoming smaller or not being sufficiently formed in the vicinity of the intersection C12 in the second planned cutting line C2. Further, as described above, the metal deposition film constituting the alignment pattern 20 and the test pattern 21 is formed on the first planned cutting line C1. As a result, in the first cleaving line C1, there is a portion where the formation of the internal crack 12 is locally insufficient compared to other portions.

  As described above, the length of the internal crack 12 formed by condensing at one condensing point A is 50 to 100 μm, whereas the thickness of the silicon substrate 10 is 625 μm. Therefore, in order to cut the silicon substrate 10 satisfactorily, it is preferable to perform internal processing using a plurality of positions different in the depth direction as light condensing points. It is preferable that the internal processing at the condensing point A different in the depth direction is made closer to the substrate surface 11 only after processing on the far side (back side) from the substrate surface 11. In the internal processing at the condensing points A that differ in the depth direction, the internal cracks 12 formed by processing at the respective condensing points A may be connected in the depth direction, or the internal cracks 12 may be deep. It may be formed intermittently in the vertical direction.

  At this time, in the internal processing at least at the position closest to the substrate surface 11, the upper end of the formed internal crack 12 is not connected to the surface processing mark 11 a in order to prevent splitting before the cleaving step described later. To. According to the experiment, the processing conditions such as the position of the focal point A, the film configuration of the oxide film 2 and the laser wavelength to be used are set so that the upper end of the formed internal crack 12 is separated from the substrate surface 11 by 10 μm or more. Desirably, it can be set to a depth position of 20 to 100 μm. In addition, a processing condition in which the internal crack 12 formed by the previous internal processing near the condensing point A grows due to the influence of heat or the like by laser irradiation and reaches the substrate surface 11 is not selected. . Accordingly, it is possible to prevent the internal crack 12 and the substrate surface 11 from being inadvertently connected during processing or the substrate surface 11 from being damaged.

  For the back surface of the silicon substrate 10, the internal crack 12 may reach the back surface. When the internal crack 12 does not reach the back surface, the lower end of the internal crack 12 (the end near the back surface side) is inferred from the slip direction of the crystal. Set to be inside.

  In FIG. 10, the example of the processing pattern with respect to the thickness direction of the silicon substrate 10 of the internal crack 12 is shown.

  The processed pattern shown in FIG. 10A is a pattern in which the internal crack 12 is formed by laser irradiation once in the depth direction. The upper end position of the internal crack 12 is set to a position of 25 μm from the substrate surface 11 and is not connected to the surface processing mark 11a. Moreover, about the lower end of the internal crack 12, the gap of 20 micrometers is provided with respect to the back surface. The position of the lower end is set as a position where the outer dimension of the element chip 10a falls within an allowable range even when a crack spreads along the crystal orientation during cleaving.

  The processed pattern shown in FIG. 10B is a pattern in which the internal crack 12 is formed in a plurality of times. The forming cracks formed by a plurality of internal processes are connected to each other without creating a gap therebetween, so that the internal crack 12 has an end portion substantially only at one upper and lower positions. ing. In this case, the position at which the internal machining is performed a plurality of times may be set so that the formed cracks are connected to each other, but is preferably set so that the formed cracks overlap each other. That is, by setting the overlap amount in consideration of manufacturing tolerances such as variations in the length of formed cracks and variations in position in the depth direction, the formed cracks can be reliably continued.

  The processing patterns shown in FIGS. 10A and 10B are preferable from the viewpoint of cleaving stability because the internal crack 12 is formed in the entire region in the depth direction of the cross section of the substrate. However, even if the internal cracks are not completely connected in the depth direction as described above, if the internal cracks 12 are formed intermittently at a predetermined interval, sufficiently good cleaving can be performed.

  As such a processing pattern, FIG. 10C is a pattern in which processing is performed by reducing the amount of energy to be irradiated only when a crack is formed at a position closest to the substrate surface 11 as compared with other cracks. . As a result, a crack having a gap from a crack on the back surface side is formed at a position close to the substrate surface 11. When the crack closest to the substrate surface 11 is formed, the laser light is condensed at a position close to the substrate surface 11, so that the density of energy applied to the surface is closer to the back side. Higher than time. Therefore, damage to the wiring part 3 can be suppressed by reducing the irradiation energy at the time of formation of a crack at the position closest to the substrate surface 11.

  In the processing pattern shown in FIG. 10D, the internal crack 12 is composed of a plurality of cracks provided with gaps in the depth direction. In this case, compared with the case where the internal crack 12 is connected, the strength after the internal processing can be maintained, so that inadvertent cracking such as separation of chips during conveyance from the internal processing step to the cleaving step is suppressed. be able to.

  The processing pattern shown in FIG. 10E forms a plurality of cracks with gaps in the depth direction, and the amount of energy to be irradiated is different only when a crack is formed closest to the substrate surface 11. It was dropped from the time of crack formation.

  In the processing pattern shown in FIG. 10 (f), in the vicinity of the substrate surface 11, a crack in which a plurality of formation cracks are connected without forming a gap between them is arranged, and at a position away from the substrate surface 11, between the formation cracks. This is a pattern in which a gap is provided. Since this processing pattern can make the cleaving accuracy near the substrate surface 11 relatively high, it is an effective pattern when high cleaving accuracy is required on the substrate surface 11 side.

  The processed pattern shown in FIG. 10G is a pattern in which cracks are formed in the vicinity of the back surface of the silicon substrate 10 and a plurality of formed cracks are connected without forming a gap therebetween. As in the present embodiment, the processed pattern is formed along the internal crack 12 by suppressing breakage at the ink supply port 4 portion even when the ink supply port 4 is open on the back side and the strength on the back side is low. It is effective for cleaving.

  The processed pattern shown in FIG. 10H is a pattern in which the gap between the lower end of the internal crack 12 and the back surface of the silicon substrate 10 is adjusted in accordance with the arrangement of the structure on the surface. That is, when NA is 0.55, the refractive index of silicon is 3.5, and the distance between the surface structures is 100 μm, the gap between the lower end of the internal crack 12 and the back surface of the silicon substrate 10 is 300 μm as shown in the figure. . As a result, energy loss due to vignetting on the laser irradiation surface can be suppressed and efficient processing can be performed.

  The internal cracks 12 may be formed continuously or intermittently in the direction along each cutting line C.

  FIG. 11 shows various examples of the processing order of the crack group.

  In the example shown in FIGS. 11A and 11B, a group of internal cracks 12a having the same depth position is formed for each planned cutting line C, and then a group of internal cracks having a depth position different from the internal crack 12a is formed. This is an example of forming a crack 12b. This is repeated sequentially to form internal cracks 12 composed of cracks along each planned cutting line C.

  At this time, the crack group at the same depth position can be formed by moving the silicon substrate 10 at a predetermined speed in the XY direction by the automatic stage 53 while operating the light source 51 at a predetermined pulse interval. This moving speed is set in consideration of the pulse frequency of the light source 51 and the shape of the crack formed. As described above, when the pulse frequency is 10 to 100 KHz, the moving speed is 10 to 100 mm / sec as a guide. When the moving speed exceeds 100 mm / sec, the subsequent cleaving process tends to be difficult, for example, the interval along the planned cleaving line C of the formed crack becomes too wide.

  FIG. 11A shows an example in which internal cracks 12a and 12b at respective depth positions are formed while moving the silicon substrate 10 in the same direction. FIG. 11B shows a case where the silicon substrate 10 is moved back and forth. This is an example in which internal cracks 12a and 12b having different depth positions are formed during operation and return operation. The latter has an advantage that the machining time can be shortened because the total operating distance is shortened, and this method is adopted in this embodiment. However, these may be determined by comprehensively judging from the state of the object (parallelism or swell of the silicon substrate).

  Further, as shown in FIG. 11 (c), a group of internal cracks 12a having the same depth position is formed for all planned cutting lines C, and then a group of internal cracks 12b having other depth positions is formed. May be. This method has an advantage that the number of times of changing the setting of the depth position can be reduced. Further, after forming the deepest crack group at the depth position for all the planned cutting lines C, by sequentially forming the shallowest depth positions, the crossing at the intersection C12 of the planned cutting line C is performed. The influence by the internal crack 12 previously formed on the planned line C can be reduced.

  Alternatively, as shown in FIG. 11 (d), internal cracks 12a, 12b, and 12c having different depth positions may be formed at a certain point, and the crack formation point may be changed along the planned cutting line C. Good. This method has an advantage that the number of correction operations can be reduced because the correction operation at each processing point only needs to be performed at the start of processing when the correction of the focal position with respect to the flatness of the silicon substrate 10 is necessary.

"Cleaving process" (Step 5)
As described above, the silicon substrate 10 in which the surface processing marks 11a and the internal cracks 12 are formed along each planned cutting line C has a gap at least between the surface processing marks 11a and the internal cracks 12. Therefore, the silicon substrate 10 is not separated into the individual element chips 10a even after the laser processing, that is, the internal crack formation process. In the cleaving step, the silicon substrate 10 in this state is separated into individual element chips 10a.

  In this cleaving step, as shown in FIG. 12, the silicon substrate 10 is placed on the rubber sheet 60 of the cleaving apparatus so that the back surface of the silicon substrate 10 faces up while being mounted on the dicing tape T. The rubber sheet 60 is preferably sufficiently elastic, and may be formed from silicone rubber or fluorine rubber. In order to prevent the substrate surface 11 of the silicon substrate 10 from coming into contact with the rubber sheet 60, a commercially available protective tape R used for back grinding or the like is applied to the substrate surface 11 after the formation of internal cracks. May be.

  Then, the silicon substrate 10 placed on the rubber sheet 60 in this way is pressed by the roller 61 via the dicing tape T from the back surface side, so that the silicon substrate 10 is cleaved. The roller 61 is made of a hard material, such as stainless steel, and has a sufficient length in the direction of the rotation axis thereof, and can press a linear region extending from end to end of the silicon substrate 10 at a time. .

  The compression is first performed by arranging the silicon substrate 10 so that the first cleaving line C <b> 1 is substantially parallel to the rotation axis of the roller 61. When the silicon substrate 10 is pressed while rolling the roller 61, the silicon substrate 10 is deformed so as to sink into the rubber sheet 60 immediately below the roller 61.

  When the roller 60 comes directly above the first cleaving line C1, as shown in FIG. 12 (b), a force is applied to spread the surface processing mark 11a. As a result, a crack occurs starting from the surface processing mark 11a. That is, since the surface processing mark 11a and the internal crack 12 are formed along the planned cutting line C, when an external force is applied, stress concentration occurs in the planned cutting line C, and along the planned cutting line C. Cracking occurs.

  The crack generated from the surface processing mark 11a is connected to the internal crack 12 formed by laser irradiation. Thereby, the crack spreads to the back surface of the silicon substrate 10 along the first cleaving line C1. In addition, the generated crack spreads in the direction parallel to the substrate surface 11 along the first cleaving line C1. That is, because of the in-plane distribution of the strength of the silicon substrate 10 and variations in the formation of the surface processing marks 11a and the internal cracks 12, cracks are first broken into several pieces as shown in FIG. Usually formed at the starting point S. When a crack is formed at the cleaving start point S, stress is easily applied to a portion around the crack, and as a result, as indicated by an arrow E, the crack spreads along the first cleaving line C1. . And as shown in FIG.13 (b), the cracks extended from each cutting start point S are connected by the point M, and a crack spreads in the whole part along the 1st cutting planned line C1 in this way. In this manner, the silicon substrate 10 is separated along the first planned cutting line C1, that is, is cut.

  At this time, the spread of cracks tends to occur along the crystal orientation of the silicon substrate 10 in detail. However, when the formation crack is connected to the internal crack 12 or the surface processing mark 11a, the cleaving is performed substantially along the first cleaving line C1.

  Moreover, since the surface processing trace 11a is formed, it can suppress that a crack generate | occur | produces in places other than the formation part of the surface processing trace 11a of the board | substrate surface 11. FIG. Therefore, it is possible to prevent the logic circuit or the like of the wiring unit 3 from being adversely affected by the crack.

  As the roller 61 advances, the cleaving along each first cleaving line C1 is sequentially performed. The roller 61 may be advanced from one end of the silicon substrate 10 toward the other end, or the progress toward each end of the silicon substrate 10 is started in the vicinity of the center of the silicon substrate 10 in order. You may go.

  Next, the silicon substrate 10 is rotated by 90 ° so that the second cleaving line C2 and the rotation axis of the roller 61 are substantially parallel. Then, as in the case of the first cleaving line C1, the silicon substrate 10 is pressed by the roller 61 to cause a crack starting from the surface processing mark 11a to reach the back surface. Cleaving along the planned cutting line C2.

  Through the above steps, the silicon substrate 10 is divided along the first planned cutting lines C1 and the second planned cutting lines C2 in the entire region, and is separated into individual element chips 10a.

  In the cleaving step described above, as described above, an effect is obtained in which the induced crack spreads in a direction parallel to the substrate surface 11 along the cleaving line C. Thereby, even if there is a portion where the formation of the internal crack 12 is non-uniform, it is possible to prevent the separation from being performed at that portion or the separation position from being shifted.

  This action is interrupted at the cleaved portion when the intersecting direction is cut first. However, if the intersecting direction is not cut, this effect is obtained over the entire length of the planned cutting line C. It is done. Therefore, this effect can be obtained more effectively on the side where the cutting is to be performed first among the planned cutting lines C1 and C2.

  That is, as shown in FIG. 14, a case is considered in which, after cleaving along the cleaved line G extending in the vertical direction in the figure is completed, cleaving is performed along the planned cleaving line C extending in the horizontal direction in the figure. In FIG. 14A, the cleaving start point S is generated between the left and right element chips 21 and 24 and 23 and 26, while the cleaving start point S is formed between the element chips 22 and 25 in the center of the figure. The case where the starting point S did not arise is shown. For example, when there is a portion where the internal crack 12 is not sufficiently formed between the element chips 22 and 25 and the distance between the cleaved lines G along the planned cleave line C is relatively short, the element chip is thus formed. There is a high possibility that the cleaving start point S does not occur between 22 and 25.

  In the subsequent process, cracks spread from the left and right cleavage start points S, respectively, but the spread of these cracks is interrupted by the cleaved line G as shown in FIG. There may be a case where it is left uncut for 25. On the other hand, if the cleaving is not performed on the cleaved line G, the crack extending from the cleaving start point S on the left and right also extends between the element chips 22 and 25, and the element chips 22 and 25 are cleaved well. can do.

  Therefore, in the present embodiment, as described above, there is a portion where the formation of the internal crack 12 is locally insufficient compared to other portions due to the metal deposited film constituting the test pattern 21 and the like. The cleaving along the existing 1st cutting plan line C1 is performed previously. Thereby, even in a portion where the formation of the internal crack 12 is insufficient, it is possible to perform good cleaving. On the other hand, the second cleaved planned line C2 side has no factor that the formation of the internal crack 12 is insufficient. Therefore, even if the action of the crack spreading in the direction parallel to the substrate surface 11 is relatively weak, good cleaving Is possible.

  Further, when the element chip 10a has a rectangular shape having an aspect ratio, if the cleaving along the short side is performed first, then the cleaving along the long side is positioned along the planned cutting line. The number of parts that have already been cleaved can be kept relatively small. Therefore, by performing the cleaving along the short side first, it is possible to reduce the number of portions where the action of the crack spreading in the direction parallel to the substrate surface 11 is interrupted, and this action can be obtained effectively. In the present embodiment, in consideration of this, as described above, the side along the short side of the element chip 10a is set to the first cleaving line C1 for cleaving first.

  In the cleaving process in the present embodiment, stress is applied to the entire silicon substrate 10 as the rubber sheet 60 is deformed by the hard roller 61, and the logic elements and nozzle layers of the wiring portion 3 are adversely affected. It is necessary to prevent it from occurring. That is, by appropriately setting the pressing load of the silicon substrate 10 by the roller 61, the thickness of the rubber sheet 60, the rubber hardness, etc., the cutting along the planned cutting line C is performed while suppressing adverse effects on the wiring portion 3. be able to. The material and thickness of the dicing tape T and the protective tape R on the substrate surface 11 are selected so that the force by the roller 61 is not excessively buffered. As the protective tape R, it is desirable to select a material that is equal to or softer than the dicing tape T so as not to prevent the deformation of the silicon substrate 10 at the time of cleaving. For example, when polyolefin is used for the base material of the dicing tape T, the protective tape R is preferably made of polyolefin or vinyl chloride.

"Repair process" (Step 6)
As described above, in the cleaving step, the surface processing mark 11a and the internal crack 12 are connected to each other by the crack generated with the stress, and the crack reaches the back surface of the silicon substrate 10, and the silicon substrate 10 It is separated into element chips 10a. However, if there is no accidental complete separation, it is necessary to re-cleave. The re-cleaving can be performed using, for example, a mechanism for a pickup process described later shown in FIG.

  The mechanism shown in FIG. 15 includes a pickup pin 66 disposed on the dicing tape T side, that is, the back surface side of the silicon substrate 10, and a suction collet 65 disposed on the substrate surface 11 side. The suction collet 65 and the pickup pin 66 have a size corresponding to each element chip 10a, and can be moved up and down by a mechanism (not shown). In addition, this mechanism has a mechanism for moving the suction collet 65 and the pickup pin 66 or the silicon substrate 10 in a direction parallel to the substrate surface 11. Thereby, the suction collet 65 and the pickup pin 66 can be aligned at a position corresponding to the desired element chip 10a.

  If not completely separated, the suction collet 65 and the pickup pin 66 are aligned with the position corresponding to the element chip 10a. Then, the element chip 10a is pushed up by the pick-up pin 66, and the element chip 10a is captured by bringing the suction collet 65 close to the pushed-up element chip 10a. In this way, by slightly lifting the element chip 10a portion, stress can be applied to the parting line C, and the element chip 10a can be completely separated.

"Pickup process" (Step 7)
As shown in FIG. 15, the element chips 10a separated in the cleaving process and the repair process are carried out by the suction collet 65 and stored individually. At this time, the pick-up may be performed after widening the gaps between the element chips 10a by applying a force to spread the dicing tape T with an expander or the like. Further, fine dust generated at the time of pickup may be removed by suction.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 16, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The present embodiment is different from the first embodiment in the cleaving process. Other steps and the like may be the same as those in the first embodiment unless specifically described, and a detailed description thereof will be omitted.

  In the present embodiment, as shown in FIG. 16, cleaving is performed by pressing a portion along the planned cutting line C of the silicon substrate 10 with a blade-like pressing tool (hereinafter referred to as a blade 30). The blade 30 is made of a hard material and has a sufficient length in the longitudinal direction, and can simultaneously press a linear region extending from end to end of the silicon substrate 10. The blade 30 is made of, for example, stainless steel and has a length of 160 mm and a cutting edge width of 0.2 mm.

  In the cleaving step, first, as shown in FIG. 16A, the silicon substrate 10 is placed on the rubber sheet 60 so that one of the planned cutting lines C of the silicon substrate 10 is substantially parallel to the blade 30. When the blade 30 is brought into contact with a portion along the planned cutting line C on the back surface of the silicon substrate 10 and pressed, the rubber sheet 60 is deformed so as to sink immediately below the blade 30. As a result, as in the first embodiment, the silicon substrate 10 is subjected to a force to spread the surface processing mark 11a on the rubber sheet 60 side, that is, the substrate surface 11 side, and the surface processing mark 11a is the starting point. As a crack occurs. The generated crack is induced by the surface processing mark 11a and the internal crack 12, spreads along the planned cutting line C, and is cut along the planned cutting line C.

  At this time, a tensile force may be applied to the protective tape R during compression. Thereby, since the stress to the surface processing mark 11a in the cleaving is enhanced, the amount of pushing of the blade 30 necessary for the cleaving can be further reduced. Furthermore, since a gap is formed between the element chips 10a after the cleaving, it is possible to suppress rubbing between the element chips 10a after the cleaving and suppress the occurrence of chipping.

  In the present embodiment, stress can be applied to the portion along the planned cutting line C by the blade 30, and stress can be suppressed from being applied to the wiring portion 3. That is, it is easy to apply a sufficient stress to a portion along the planned cutting line C while suppressing adverse effects on the wiring portion 3, thereby enabling effective cutting. In particular, even when the wiring portion 3 includes a nozzle layer and the ink supply port 4 (see FIG. 1 or the like) is formed, the cleaving step is performed on a portion where the strength is weakened because the ink supply port 4 is formed. Can be prevented from being damaged.

  Note that, as described above, the spread of cracks is likely to occur in the cleavage direction along the crystal orientation of the silicon substrate 10 as described in detail. In the present embodiment, the position where the stress is applied by the blade 30 can be easily fine-tuned. Therefore, the cleavage position on the back surface of the silicon substrate 10 can be controlled to adjust the crack arrival position.

  For example, as shown in FIG. 17, consider manufacturing an element chip 10a including a nozzle layer in which an ink supply port 14 is formed. In this case, as shown in FIG. 17B, when viewed in a cross section, there are two cleavage directions, CLa and CLb, from the end of the internal crack 12 toward the back surface of the silicon substrate 10. Therefore, by setting the compression position P by the blade 30 to a position closer to the one cleavage direction CLa side from the cleaving planned line C as shown in FIG. 17B, the crack is along the cleavage direction CLa. Can be spread.

  FIG. 17 shows an example in which cleaving is performed between the element chip 10a and the spare part. In this case, it is preferable to set the portion slightly closer to the element chip 10a than the planned cutting line C as the compression position P. As a result, it is possible to prevent cracks from spreading toward the element chip 10a side on the back surface side of the silicon substrate 10 and to prevent the element chip 10a from protruding.

  Moreover, in this embodiment, the order of the cutting planned line C which stresses with the braid | blade 30, and therefore the order of the cutting planned line C which performs cutting can be adjusted easily. Hereinafter, a preferable order of the cleaving planned line C for cleaving will be described.

  First, as shown in FIG. 18, it is first considered to perform cutting along a planned cutting line C close to the end of the silicon substrate 10. In this case, as shown in FIG. 18 (b), one of the divided pieces formed by cleaving of the silicon substrate 10 is much smaller than the other. Larger displacement as 30 is pushed. When the cleaving is completed, the small divided piece may jump up. When the split pieces bounce up in this way, it causes rubbing and chipping. Also, when the blade 30 is pressed, the stress applied to the parting line C is likely to become unstable, and the cleaving accuracy is lowered.

  Therefore, as shown in FIG. 19A, the compression is first performed at a position along the planned cutting line C1 near the center of the silicon substrate 10 as the compression position P1. In this case, since the two divided pieces formed by the cleaving of the silicon substrate 10 have substantially the same size, the displacement is generated symmetrically with respect to the planned cutting line C1, and is stably performed in a portion along the planned cutting line C1. Stress can be applied. Moreover, it can suppress that a division | segmentation piece jumps up.

  Subsequently, as shown in FIG. 19B, a position along the planned cutting line C1 near the center of the divided piece separated by the cut line G in the process shown in FIG. Make pressure. At this time, since the entire divided piece is likely to be depressed by the compression on the divided piece that has become smaller, it is difficult to apply stress to the planned cutting line C1 immediately below the compression position P2 with the same pushing amount. Therefore, the pushing amount of the blade 30 at the time of dividing the divided piece shown in FIG. 19 (e) is larger than the pushing amount Q1 of the blade 30 at the time of breaking the unbroken silicon substrate 10 shown in FIG. 19 (d). It is preferable to increase the amount Q2.

  After that, as shown in FIG. 19 (c), in the further smaller divided piece, the portion along the cutting planned line C1 near the center is divided as the compression position P3, and this is repeated to repeat all the cutting planned lines. Cleaving along C1. At this time, in the cleaving shown in FIG. 19 (c), the pushing amount Q3 shown in FIG. 19 (f) is made larger than that in the cleaving shown in FIG. 19 (b). Therefore, it is preferable to increase the pushing amount.

  Thereafter, the silicon substrate 10 is rotated by 90 °, and cutting along the second planned cutting line C2 is performed. The cleaving along the second planned cutting line C2 is also preferably performed in order from the vicinity of the center in each divided piece, as in the case of the first planned cutting line C1.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram of the silicon substrate in the 1st Embodiment of this invention, (a) is a perspective view, (b) is a partial expansion perspective view which expands and shows a part of (a), (c) is (b). The fragmentary sectional view which shows the cross section. The top view which shows in more detail the part which follows the cutting planned line of the silicon substrate of FIG. The flowchart of the cleaving process by the 1st Embodiment of this invention. The figure explaining a tape mounting process. The figure explaining a wafer correction process. The figure explaining the surface linear processing process which forms a surface processing trace. It is a figure explaining an internal crack formation process, (a) is a schematic diagram which shows the processing apparatus which irradiates a laser beam, (b) is a figure which shows the mechanism in which an internal crack generate | occur | produces. The figure explaining the internal crack formation process in the edge part of a silicon substrate. The figure explaining the formation order of an internal crack. The figure which illustrates the formation pattern of the depth direction of an internal crack. Diagram illustrating the internal crack formation sequence The figure explaining the cleaving process using the roller by the 1st Embodiment of this invention. The figure explaining that a crack spreads in the direction parallel to the substrate surface. The figure explaining that a crack spreads in the direction parallel to the substrate surface when there is a cleaved line. The figure explaining a pick-up process. The figure explaining the cleaving process using the braid | blade by the 2nd Embodiment of this invention. It is a figure explaining the compression position by a braid | blade, (b) is a figure which expands and shows B part of (a). It is a figure explaining the case where the part along the cutting planned line near the edge part of a silicon substrate is pressed with the braid | blade, (a) is a top view, (b) is the cross section along the FF line of (a). Figure. (A) to (b) is a diagram showing a preferred cleaving order by blades, and (d) to (f) are cross-sections of the planned cutting line portion to be cleaved at each cleaving from (a) to (b) Figure.

Explanation of symbols

3 Wiring part 10 Silicon substrate (semiconductor substrate)
10a element chip 11a linear processing part 12 internal crack 20 alignment pattern 21 test pattern C1 first cleaved line C2 second cleaved line

Claims (8)

Forming a plurality of wiring portions on the surface of the semiconductor substrate;
Forming on the surface of the semiconductor substrate at least one of a test pattern for inspecting the characteristics of the wiring portion and an alignment pattern for enabling detection of the position of the semiconductor substrate;
Thereafter, separating the semiconductor substrate into a plurality of element chips each including the wiring portion;
A device chip manufacturing method comprising:
The step of separating into a plurality of the element chips,
Grooves are formed on the surface of the semiconductor substrate along at least one first cutting line for separation into the element chip and at least one second cutting line that intersects the first cutting line. Forming a linear processed portion of
An internal crack extending in the depth direction is formed by condensing laser light at a condensing point at a predetermined depth position along the planned cutting line inside the semiconductor substrate, and the formation of the internal crack is repeated. Forming a group of cracks along the planned cutting line;
Applying a force toward the front surface side of the back surface of the semiconductor substrate to generate a crack that connects the linear processed portion and the internal crack, and cleaving the semiconductor substrate along the first planned cutting line;
After cleaving along the first planned cutting line, a force is applied to the back surface of the semiconductor substrate toward the front surface side to generate a crack that connects the linearly processed portion and the internal crack, and the semiconductor substrate is Cleaving along the second cleaving line,
Have
The step of forming at least one of the test pattern and the alignment pattern is performed only on the first planned cutting line,
Element chip manufacturing method. The element chip has a rectangular shape having a short side and a long side, the first cutting planned line extends along the short side of the element chip, and the second cutting planned line is the element chip. Extending along the long side of the
The element chip manufacturing method according to claim 1. When cleaving the semiconductor substrate, a protective tape is applied to the surface of the semiconductor substrate, and a tensile force is applied to expand the protective tape.
The element chip manufacturing method according to claim 1 or 2. In the cleaving step, a force is applied by bringing a blade into contact with the back surface of the semiconductor substrate in parallel to the planned cutting line.
The element chip manufacturing method according to any one of claims 1 to 3. At least one of the first planned cutting line and the second planned cutting line is plural, and the cutting along the plurality of first planned cutting lines and the cutting along the plurality of second planned cutting lines are performed. First, perform the cutting along the planned cutting line in the center of the semiconductor substrate, and then perform in order so as to perform the cutting along the planned cutting line in the center of the divided pieces.
The element chip manufacturing method according to claim 4. The cleaving step includes cleaving along the cleaving line extending between the part serving as the element chip and the spare part, and the cleaving schedule extending between the part serving as the element chip and the spare part. The cutting along the line is performed by bringing the blade into contact with the position closer to the element chip than the planned cutting line.
The element chip manufacturing method according to claim 4 or 5. A wiring portion constituting a plurality of rectangular element chips having a short side and a long side;
At least one of a test pattern for inspecting the characteristics of the wiring portion and an alignment pattern for enabling position detection;
Is a semiconductor substrate formed on the surface and separated into a plurality of the element chips,
The test pattern and the alignment pattern are formed only on a boundary line extending along the short side among the boundary lines between the element chips.
Semiconductor substrate. A substrate cleaving method for separating a semiconductor substrate into a plurality of element chips,
Forming a groove-like linearly processed portion on the surface of the semiconductor substrate along a planned cutting line for separation into the element chips;
An internal crack extending in the depth direction is formed by condensing laser light at a condensing point at a predetermined depth position along the planned cutting line inside the semiconductor substrate, and the formation of the internal crack is repeated. Forming a group of cracks along the planned cutting line;
A blade is brought into contact with the back surface of the semiconductor substrate in parallel with the planned cutting line, and a force is applied toward the front surface side of the semiconductor substrate to generate a crack that connects the linearly processed portion and the internal crack. Cleaving the substrate along the planned cutting line;
A substrate cleaving method comprising:

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