JP2007317096A - Verification scenario producing program, recording medium, verification scenario producing system, and verification scenario producing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute highly accurate logical verification and improve efficiency of verification operation. <P>SOLUTION: The verification scenario producing system produces an outline scenario as an intermediate file which becomes a framework of a verification scenario based on a result of path analysis of a verification target. The verification producing system produces a table of verification items based on a user's operation input by use of a GUI. The verification scenario producing system produces the verification scenario based on the outline scenario and the table of verification items. Besides, a designer can monitor each time when the outline scenario and table of verification items are produced. Herewith, validity of the content of verification can be recognized during the verification by the designer, thereby improving the accuracy of the logical verification. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a verification scenario creation program, a recording medium, a verification scenario creation device, and a verification scenario creation method for creating a verification scenario for performing LSI logic verification.

  In LSI design, it is indispensable to check the operation by a logic verification operation such as a logic simulation for verifying whether the LSI operates normally. Especially for LSIs that require large scale, high functionality, high speed and low power consumption, this logic verification work is important to maintain high quality, while the design period has been shortened from the past. The work efficiency improvement by is required.

  Extraction of verification items is important for improving the efficiency of verification work. For example, if there are too few verification items extracted, the yield will decrease, and rework such as LSI rework will occur, resulting in a great deal of work. Increases man-hours. If too many verification items are extracted, verification becomes redundant and the number of work steps increases. As described above, when an appropriate verification item cannot be extracted, an increase in design period and an increase in manufacturing cost in LSI design are caused.

  Furthermore, after extracting the verification items, it is necessary to create a verification scenario to be actually used for logic simulation or the like. At this time, for example, when the number of verification items extracted is large, it is difficult to create a verification scenario that covers all the verification items. In addition, when a logic simulation using an incorrect verification scenario is performed, the logic simulation is re-executed, which causes a prolonged logic verification operation.

  For this reason, in order to reduce the burden of verification work by the user when performing logical verification work, it has been possible to automatically perform all of verification items extraction, verification scenario creation, and logical verification based on the verification scenario. A verification scenario creation device that can be used is provided (see, for example, Patent Document 1 below).

JP 2006-85319 A

  However, in the conventional verification scenario creation apparatus described above, a series of processes such as extraction of verification items, creation of a verification scenario, and logical verification based on the verification scenario are automatically performed. There has been a problem that it is not possible to visually check whether or not logic verification has been performed on such verification items during the verification scenario creation.

  For this reason, it is difficult for an unskilled designer or the like to determine whether the verification scenario is correct or not only by looking at the verification scenario. As a result, logic verification may be performed using an incorrect verification scenario, and it is difficult to improve the accuracy of verification work.

  In addition, a highly skilled designer may decide whether the verification result is correct or not based on experience or can, but if there is an error in the verification result, add or delete verification items to be extracted, etc. It is necessary to create a verification scenario based on the corrected verification items. In this case, it is necessary to perform logic verification again from the beginning based on the newly created verification scenario, which still increases the design period and the manufacturing cost in LSI design.

  Furthermore, the verification scenario created by the above-described conventional verification scenario creation device depends on the architecture to be verified for logical verification, and cannot be used for an architecture exceeding a specific design range. There was a problem of poor versatility.

  In addition, it is possible to reconstruct the configuration such as the verification scenario creation program according to the verification target architecture to perform the logic verification, but it may take a lot of time and effort to reconstruct the program. There was a problem that it would lead to an increase in period and production cost.

  The present invention eliminates the problems caused by the prior art described above, and performs a highly accurate logic verification and a verification scenario creating program, a recording medium, a verification scenario creating apparatus, and a verification scenario capable of improving the efficiency of verification work The purpose is to provide a creation method.

  In order to solve the above-described problems and achieve the object, a verification scenario creation program, a recording medium, a verification scenario creation device, and a verification scenario creation method according to the present invention receive and input an input of a path analysis result related to a verification target Based on the path analysis result, outline scenario data related to the verification target logical verification is generated, and a combination of verification items necessary for the logical verification related to the verification target selected from the set of verification items related to the logical verification is represented. A list is displayed on the display screen for each path analysis result. From the displayed list, a selection of verification item combinations related to arbitrary path analysis results is accepted by user operation input, and the selected verification item Using the combination and the general scenario data, the verification scenario data regarding the logical verification is used. And generating a.

  According to the present invention, by presenting a list to the user in the middle of verification, the validity of verification items when performing logical verification can be confirmed, and appropriate verification scenario data can be generated. . In addition, since schematic scenario data corresponding to each verification target can be generated based on the path analysis result created for each verification target, logical verification independent of the verification target architecture can be performed.

  In the above invention, the generated general scenario data is displayed on a display screen, and it is determined whether or not the general scenario data displayed on the display screen has been corrected by the user's operation input. Based on the result, verification scenario data related to the logic verification may be generated.

  According to the present invention, it is possible to correct the general scenario data by the user's operation input before creating the verification scenario, and when it is corrected, the verification scenario can be generated using the corrected general scenario data.

  Further, in the above invention, by selecting a combination of verification items required for logical verification related to the verification target from a set of verification items related to the logical verification displayed on the display screen by the user's operation input, A list may be displayed for each path analysis result.

  According to the present invention, it is possible to create a list representing combinations of verification items necessary for logical verification related to a verification target by user operation input.

  In the above invention, it is determined whether the verification items of the list displayed on the display screen match the description contents of the general scenario data, and the description of the general scenario data is determined based on the determination result. The verification items in the list that do not match the contents may be highlighted.

  According to the present invention, the verification items of the list that are not compatible with the description content of the general scenario data can be displayed in a display format that can be intuitively recognized by the user.

  According to the verification scenario creation program, the recording medium, the verification scenario creation device, and the verification scenario creation method according to the present invention, it is possible to perform highly accurate logic verification and to improve the efficiency of verification work. .

  Exemplary embodiments of a verification scenario creation program, a recording medium, a verification scenario creation device, and a verification scenario creation method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment)
<Hardware configuration of verification scenario creation device>
First, the hardware configuration of the verification scenario creating apparatus according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing a hardware configuration of a verification scenario creating apparatus according to an embodiment of the present invention.

  In FIG. 1, the verification scenario creation device is an example of a CPU 101, ROM 102, RAM 103, HDD (hard disk drive) 104, HD (hard disk) 105, FDD (flexible disk drive) 106, and a removable recording medium. FD (flexible disk) 107, display 108, I / F (interface) 109, keyboard 110, mouse 111, scanner 112, and printer 113. Each component is connected by a bus 100.

  Here, the CPU 101 controls the entire verification scenario creation apparatus. The ROM 102 records a program such as a boot program. The RAM 103 is used as workware for the CPU 101. The HDD 104 controls reading / writing of data with respect to the HD 105 according to the control of the CPU 101. The HD 105 stores data written under the control of the HDD 104.

  The FDD 106 controls reading / writing of data with respect to the FD 107 according to the control of the CPU 101. The FD 107 stores data written under the control of the FDD 106, or causes the verification scenario creation apparatus to read data stored in the FD 107.

  In addition to the FD 107, the removable recording medium may be a CD-ROM (CD-R, CD-RW), MO, DVD (Digital Versatile Disk), memory card, or the like. The display 108 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As the display 108, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 109 is connected to a network 114 such as the Internet through a communication line, and is connected to other devices via the network 114. The I / F 109 controls an internal interface with the network 114 and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 109.

  The keyboard 110 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 111 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 112 optically reads an image and reads image data into the verification scenario creating apparatus. The scanner 112 may have an OCR function. The printer 113 prints image data and document data. As the printer 113, for example, a laser printer or an ink jet printer can be employed.

<Functional configuration of verification scenario creation device>
Next, a functional configuration of the verification scenario creating apparatus according to the embodiment of the present invention will be described. FIG. 2-1 is a block diagram showing a functional configuration of the verification scenario creating apparatus according to the embodiment of the present invention. 2A, the verification scenario creation apparatus includes an input unit 201, a schematic scenario data generation unit 202, a display unit 203, a display control unit 204, a selection unit 205, a verification scenario data generation unit 206, and a determination. Part 207.

  The input unit 201 receives an input of a path analysis result related to the verification target. The verification target is, for example, an LSI having a specific function, and is a target for performing logical verification. The path analysis result is descriptive data indicating an object necessary for realizing the function of the verification target, an operation flow of the object, and the like. This path analysis result is created for each verification target by a user operation input or the like.

  Based on the path analysis result input by the input unit 201, the general scenario data generation unit 202 generates general scenario data related to the logical verification to be verified. The outline scenario data is intermediate data that forms a framework of verification scenario data described later, and is description data that indicates definitions and the like regarding the operation of the object. The general scenario data generation unit 202 generates general scenario data for each path analysis result input by the input unit 201.

  The display unit 203 has a display screen. The display control unit 204 controls the display screen to display, for each path analysis result, a list representing a combination of verification items necessary for logical verification related to the verification target selected from the set of verification items related to logical verification. To display. A set of verification items related to logical verification is a set of verification items arbitrarily set by the user. A set of verification items arbitrarily set by the user will be described later with reference to FIGS.

  Further, the display control unit 204 displays the general scenario data generated by the general scenario data generation unit 202 on the display screen. Further, the display control unit 204 selects a list of verification items necessary for the logical verification related to the verification target from the set of verification items related to the logical verification displayed on the display screen by the user's operation input. Display for each path analysis result.

  The selection unit 205 receives selection of a combination of verification items related to an arbitrary path analysis result from a list displayed by the display control unit 204 by a user operation input. A detailed description of the user operation input will be described later.

  The verification scenario data generation unit 206 generates verification scenario data related to logic verification using the combination of verification items selected by the selection unit 205 and the general scenario data generated by the general scenario data generation unit 202. The verification scenario data is descriptive data indicating a flow (scenario) of the function used when verifying a function to be verified. For example, when verifying the function of the arithmetic unit of the CPU, the pattern data is input to the arithmetic unit in order to verify whether or not the operation “A + B = C” is performed.

  The determination unit 207 determines whether or not the general scenario data displayed on the display screen by the display control unit 204 has been corrected by a user operation input. Then, the verification scenario data generation unit 206 generates verification scenario data related to logic verification based on the determination result determined by the determination unit 207.

  Specifically, the user can arbitrarily correct the outline scenario data when there is an error in the description content of the outline scenario data displayed on the display screen. Then, when the general scenario data is corrected by the user, the verification scenario data generation unit 206 generates verification scenario data using the corrected general scenario data.

  In addition, the determination unit 207 determines whether the verification items of the list displayed on the display screen by the display control unit 204 match the description contents of the general scenario data. Based on the determination result determined by the determination unit 207, the display control unit 204 highlights the verification items in the list that do not match the description content of the general scenario data. Specifically, for example, the display control unit 204 highlights the cell by changing the color of the cell in which the verification item that does not match the description content of the outline scenario data in the list is displayed.

  Note that the input unit 201, the schematic scenario data generation unit 202, the display control unit 204, the selection unit 205, and the verification scenario data generation unit 206 are specifically recorded in the ROM 102, the RAM 103, the HD 105, etc. shown in FIG. The function is realized by causing the CPU 101 to execute the program recorded on the medium or by the I / F 109.

<Verification scenario creation processing procedure of verification scenario creation device>
FIG. 2-2 is a flowchart showing a verification scenario creation processing procedure in the verification scenario creation device according to the embodiment of the present invention. 2-2, first, the input unit 201 waits for input of a path analysis result related to the verification target (step S201: No).

  When the path analysis result is input (step S201: Yes), the general scenario data generation unit 202 generates general scenario data related to the verification target logical verification based on the path analysis result input by the input unit 201. (Step S202). Next, the display control unit 204 displays, on the display screen, a list representing a combination of verification items necessary for the logical verification related to the verification target selected from the set of verification items related to the logical verification for each path analysis result. (Step S203).

  Here, the selection unit 205 waits for selection of a combination of verification items related to an arbitrary path analysis result from the list displayed by the display control unit 204 by a user operation input (step S204: No). When selected (step S204: Yes), the verification scenario data generation unit 206 uses the combination of verification items selected by the selection unit 205 and the general scenario data generated by the general scenario data generation unit 202. Thus, verification scenario data relating to logic verification is generated (step S205).

  According to this verification scenario creation device, the validity of verification items when performing logical verification can be confirmed by presenting a list to the user during verification, and appropriate verification scenario data is generated. be able to. For this reason, the user can perform highly accurate logic verification using appropriate verification scenario data.

  In addition, according to the verification scenario creation device, it is possible to correct the rough scenario data by user operation input before creating the verification scenario, and when it is corrected, the verification scenario is created using the corrected rough scenario data. can do. For this reason, the user can correct the contents of the outline scenario data during the verification, and can obtain an appropriate verification scenario.

  Furthermore, according to the verification scenario creation device, it is possible to create a list representing combinations of verification items necessary for the logical verification related to the verification target by a user operation input. As a result, it is possible to improve the convenience of the user when creating a combination of verification items necessary for the logical verification related to the verification target.

  In addition, according to the verification scenario creation device, the verification items in the list that do not match the description contents of the outline scenario data can be displayed in a display format that allows the user to intuitively recognize. As a result, it is possible to improve the convenience of the user when correcting the combination of verification items necessary for the logical verification related to the verification target.

<Specific example>
<Outline of processing of verification scenario creation device>
Next, an outline of processing of the verification scenario creating apparatus according to the embodiment of the present invention will be described. FIG. 3 is an explanatory diagram showing an outline of the processing of the verification scenario creating apparatus according to the embodiment of the present invention. As shown in FIG. 3, the verification scenario creation device can output a predetermined intermediate file (schematic scenario, verification item table) before finally outputting a verification scenario to be used when performing logical verification. .

  First, the verification scenario creation device outputs a schematic scenario as an intermediate file that is a framework of the verification scenario. Here, the general scenario is an intermediate file that does not depend much on a parameter (for example, a register value for designating a verification item) set when performing logical verification. By presenting this general scenario to the user, it is possible to check whether there is an error in the description contents of the general scenario in the middle of verification.

  Specifically, the verification scenario creation device generates outline scenario data based on the path analysis result, outline scenario command group, outline scenario template, and path analysis definition file input by the input unit 201 (see FIG. 2-1). The unit 202 (see FIG. 2A) automatically generates and outputs a schematic scenario. A detailed description of the path analysis result, the general scenario template, the general scenario command group, and the path analysis definition file input to the verification scenario creation apparatus will be described later.

  Next, the verification scenario creating apparatus creates a verification item table based on a user operation input using a GUI (Graphical User Interface). The verification item table is necessary for the logical verification related to the verification target selected from the set of verification items related to the logical verification displayed on the display 108 by the display control unit 204 (see FIG. 2-1) of the verification scenario creating apparatus. It is a list showing the combination of verification items.

  Further, the verification scenario creation device can create a verification item table by reading a combination definition file that can automatically create a combination of parameters. Detailed description of the combination definition file will be described later. Then, the created verification item table is displayed on the display 108 by the display control unit 204 (see FIG. 2A) of the verification scenario creation device. The user can confirm the validity of the verification item when performing logical verification by visually recognizing the verification item table displayed on the display 108.

  Finally, the verification scenario creation device creates a verification scenario based on the general scenario, the verification item table, and the input register definition. Specifically, the verification scenario data generation unit 206 (see FIG. 2-1) of the verification scenario creation device is configured to display a summary scenario, a combination of verification items selected by the selection unit 205 (see FIG. 2-1) in the verification item table, and A verification scenario is generated and output based on the input register definition. Here, the verification scenario is, for example, a simulation parameter or a simulation scenario, and is used when a logic verification simulation is executed.

  Further, when the contents of the verification item table are corrected (for example, addition or deletion of verification items) by the user, the verification scenario creating apparatus creates a verification scenario using the corrected verification item table. Specifically, the determination unit 207 (see FIG. 2-1) of the verification scenario creation device determines whether or not the verification item table has been corrected by a user operation input, and generates verification scenario data based on the determination result. The unit 206 generates verification scenario data.

  In this way, when creating a verification scenario to be used when performing logical verification, the accuracy of an appropriate verification scenario can be confirmed by allowing the user to check the contents of intermediate files such as outline scenarios and verification item tables step by step. High logic verification can be performed.

<Summary scenario creation process>
Next, a process for creating the above-described general scenario by the verification scenario creation apparatus will be described. Here, processing when performing logic verification with an LSI related to the image transfer function as a verification target will be described. FIG. 4 is a use case diagram showing an outline of the image data transfer function.

  FIG. 4 shows an image processing apparatus 404 on which a CPU 401, an external block 402, a memory 403, and an LSI having an image data transfer function are mounted as objects for realizing the image data transfer function. Here, a function of transferring image data from the external block 402 to the memory 403 is realized by the CPU 401, the external block 402, and the memory 403 acting on the image processing apparatus 404.

  Specifically, based on the control of the CPU 401, the image processing apparatus 404 takes in the image data output from the external block 402 and transfers the fetched image data to the memory 403. Hereinafter, the logic verification for verifying whether or not the use case shown in FIG. 4 functions without malfunction will be described.

  In order to create an outline scenario necessary for performing logic verification, first, a path analysis result that creates a scenario for the operation of the CPU model when performing image data transfer processing is created. The CPU model is an object necessary for realizing the image data transfer processing, and shows the CPU 401, the external block 402, the memory 403, and the image processing device 404 here.

  Specifically, for example, the user creates a path analysis result by operating the keyboard 110 and inputting data into an analysis result template prepared in advance. When there is a tool that can automatically create a path analysis result, the user can automatically create a path analysis result using this tool.

  FIG. 5 is an explanatory diagram illustrating an example of a path analysis result. The path analysis result shown in FIG. 5 describes a path number, an outline of image data transfer processing, conditions, objects, and an event flow indicating the outline flow. The path number is a number for distinguishing each of the path analysis results when there are a plurality of path analysis results. The condition is a condition for executing the image data transfer process. Here, the condition is that no error occurs during the process. Specifically, for example, when an error occurs during execution of the image data transfer process, the series of processes may be forcibly terminated.

  Here, the event flow will be described along the outline of the image data transfer process shown in the path analysis result. First, when the verification scenario creation device sets the register of the CPU 401 to “CE = 1”, the internal operation of the image processing device 404 starts. At this time, the external block 402 outputs image data to the image processing device 404.

  Next, when the register of the CPU 401 is initialized (soft reset), the internal state of the image processing apparatus 404 is initialized (specifically, the counter inside the image processing apparatus 404 is initialized) and starts to operate. It will be in a state that can be. Next, the CPU 401 waits for “one frame” in order to synchronize the operation timing between the external block 402 and the image processing apparatus 404 and synchronizes. Specifically, for example, the CPU 401 determines that “one frame” is completed when the count value in the internal counter of the image processing apparatus 404 becomes the value of the process.

  After waiting for “1 frame” for synchronization, if the register of the CPU 401 is set to “OE = 1”, the image processing apparatus 404 starts to take in the image data output from the external block 402. The image data captured by the image processing apparatus 404 is transferred to the memory 403 and written.

  When the processing for “one frame” is completed, the image processing apparatus 404 generates an interrupt and notifies the CPU 401 of it. Next, when receiving an interrupt from the image processing apparatus 404, the CPU 401 confirms the status of the image processing apparatus 404 and clears the internal state. Finally, the CPU 401 register is set to “OE = 0, CE = 0”, and a series of processing is stopped.

  Next, a summary scenario command group input to the verification scenario creation apparatus will be described. The general scenario command is defined by replacing the operation appearing in the event flow described above with a specific command. FIG. 6 is an explanatory diagram showing an example of a schematic scenario command group. FIG. 6 shows schematic scenario commands corresponding to various operations appearing in the event flow described above.

  First, a general scenario command related to the register setting operation will be described (see (1) in the figure). When setting a register, there is one register to be set (single shot), and when a register name is specified, a description in which the register name and the set value in the event flow are described in turn is used as a general scenario command. Specifically, for example, when the register name is “CE” and the set value is “1”, the general scenario command is “WRITE, CE, 1”.

  When initializing the registers of the CPU 401, the registers to be initialized are collectively defined, and each of the register names and the setting values in the event flow are sequentially described as a general scenario command. Note that when defining a register to be initialized, if a set value of the register is undecided, a specific set value may not be described here. For example, when the set value of the register is a variable parameter, the set value is not described here.

  Next, an outline scenario command for the operation of waiting for “one frame” for synchronization will be described (see (2) in the figure). Here, a series of operations for synchronization is defined by a general scenario command. Specifically, when waiting for “1 frame” for synchronization, the CPU 401 monitors the register value of the register at the address 601, and when the register value is counted up to “525” by the internal counter of the image processing apparatus 404. Therefore, it is determined that “one frame” is completed, and the process proceeds to the next process.

  Next, an outline scenario command for the interrupt reception operation will be described (see (3) in the figure). Here, a mechanism is set in advance so that the flag is set to “1” when an interrupt occurs. The CPU 401 monitors this flag, and determines that an interrupt has been received when the flag becomes “1”.

  Here, an outline scenario template and a path analysis definition file input to the verification scenario creation apparatus will be described. FIG. 7 is an explanatory diagram illustrating an example of a schematic scenario template and a path analysis definition file. The outline scenario template is a framework of the outline scenario, and is defined as a base to which the above outline scenario command group is applied. In the outline scenario template shown here, outline scenario command groups are listed in order from “scenario () {” to the next “}”.

  In the path analysis definition file, a definition for acquiring information from the above path analysis results is described. In the path analysis definition file, first, in the “INIT” part, it is defined which item corresponds to the CPU model for the object. Specifically, a character string that is internally recognized by the verification scenario creation device is defined on the left side of the equation in the “INIT” portion, and a specific object name is defined on the right side.

  Further, in the path analysis definition file, commands corresponding to operations (events) appearing in the event flow shown in the path analysis result are defined in the “COMMAND” portion. Specifically, a keyword corresponding to a specific action is defined on the right side of the equation in the “COMMAND” part, and a character string (command) for causing the verification scenario creation apparatus to recognize it internally on the left side Is defined.

  Note that the notation “&” in the path analysis definition file indicates that the equation is satisfied when both of the items described on both sides exist, and the notation “|” is described on both sides. It is shown that the equation holds when one of the two is present.

  The definitions described in the path analysis definition file have a higher priority in order from the top. That is, in the outline scenario output process to be described later, it is evaluated whether or not they are matched or matched in order from those described above in the path analysis definition file. When there are a plurality of path analysis results, object names and commands corresponding to all objects and operations described in the plurality of path analysis results can be defined in the path analysis definition file.

<Outline of scenario output process>
Next, the procedure of the schematic scenario output process in the verification scenario creating apparatus according to the embodiment of the present invention will be described. FIG. 8 is a flowchart showing a procedure of a schematic scenario output process in the verification scenario creating apparatus according to the embodiment of the present invention.

  In the flowchart of FIG. 8, first, the verification scenario creating apparatus determines whether or not input data has been input (step S801). Specifically, the input unit 201 illustrated in FIG. 2A receives input of input data. The input data input to the verification scenario creation device is, for example, the above-described path analysis result, general scenario command group, general scenario template, and path analysis definition file.

  Here, after receiving input data input, if input is received (step S801: Yes), the input path analysis result is read (step S802). When input of a plurality of path analysis results is received in step S801, for example, the path analysis results are read one by one in the order in which the inputs are received.

  Next, CPU model recognition processing is executed based on the read path analysis result (step S803). Specific processing of the CPU model recognition processing will be described later. In step S802, command registration processing is executed based on the read path analysis result (step S804). Specific processing of command registration processing will be described later. Next, an outline scenario output process is executed based on the command registered in the command registration process (step S805). Specific processing of the outline scenario output processing will be described later.

  Then, it is determined whether or not the processing for all the path analysis results received in step S801 has been completed (step S806). Here, when the processing for all the path analysis results has not been completed (step S806: No), the processing returns to step S802 and the series of processing is repeated. Further, when the processes for all the path analysis results are completed (step S806: Yes), the series of processes according to this flowchart is terminated.

  Note that the processes executed in steps S803, S804, and S805 are executed by the general scenario data generation unit 202 shown in FIG.

  Next, the CPU model recognition process shown in step S803 will be specifically described. FIG. 9 is a flowchart showing the CPU model recognition processing procedure shown in step S803. In the flowchart of FIG. 9, the verification scenario creation apparatus matches the object described in the path analysis result read in step S802 of FIG. 8 with the object defined in the “INIT” portion of the path analysis definition file. Whether or not (step S901).

  As described above, since the objects defined in the path analysis definition file have a higher priority in order from the top, it is determined here whether or not they match in order from the top item. Specifically, first, does the object described in the path analysis result match the object name on the right side of the equation described in the top item of the “INIT” part of the path analysis definition file? Judge whether or not.

  If they match in step S901 (step S901: Yes), the matched object is recognized as a CPU model (step S902). Specifically, the matched object is recognized as a character string on the left side of the equation described in the “INIT” portion in the path analysis definition file.

  Next, it is determined whether or not the determination for all items defined in the path analysis definition file has been completed (step S903). Here, when the determination for all items has not been completed (step S903: No), the target for determining whether or not they match is shifted to the next item (step S904), and the process returns to step S901. Repeat a series of processes.

  Further, when the determination for all items is completed (step S903: Yes), the series of processes according to this flowchart is ended. In this way, it is determined whether or not all items defined in the path analysis definition file match, and all objects described in the path analysis result are recognized.

  For example, if an object that matches the object described in the path analysis result is not defined in the path analysis definition file, error processing that notifies the user is executed, and a series of processing according to this flowchart is performed. You may comprise so that it may complete | finish. In this case, for example, the user may re-create a new path analysis definition file or modify the contents of the path analysis definition file and redo the series of processes shown in FIG.

  Next, the command registration process shown in step S804 will be specifically described. FIG. 10 is a flowchart showing the command registration processing procedure shown in step S804. In the flowchart of FIG. 10, the verification scenario creation device converts the event flow character string described in the path analysis result read in step S <b> 802 of FIG. 8 to the keyword defined in the “COMMAND” portion of the path analysis definition file. It is determined whether or not they match (step S1001).

  As described above, since the keywords defined in the path analysis definition file have a higher priority in order from the top, it is determined here whether or not the keywords are matched in order from the top item. Specifically, first, a character string corresponding to the first event described in the path analysis result (e.g., corresponding to the number “1” portion of the event flow in the path analysis result shown in FIG. 5), and the path It is determined whether or not the keyword on the right side of the equation described in the top item of the “COMMAND” portion of the analysis definition file matches.

  If it is matched in step S1001 (step S1001: Yes), a command corresponding to the matched keyword is registered (step S1002). Next, it is determined whether or not the determination for all events described in the path analysis result has been completed (step S1003).

  Here, if the determination for all events has not been completed (step S1003: No), the event for determining whether or not the event matches is transferred to the next event (step S1004), and the sequence returns to step S1001. Repeat the process. Further, when the determination for all the events is completed (step S1003: Yes), the series of processes according to this flowchart is ended.

  If no match is found in step S1001 (step S1001: No), it is next determined whether or not all items defined in the path analysis definition file have been determined (step S1005). Here, when the determination for all items is not completed (step S1005: No), the item for determining whether or not it matches is shifted to the next item (step S1006), and the process returns to step S1001. Repeat a series of processes.

  In step S1005, when the determination for all items is completed (step S1005: Yes), a series of processes according to this flowchart may be ended. In this case, since there is no item that matches the character string of the event flow, for example, notify the user to that effect and perform error processing such as re-creating the path analysis definition file or prompting correction. It may be configured to execute.

  In this way, it is determined whether or not all items defined in the path analysis definition file match, and commands corresponding to all events described in the path analysis result are registered.

  Next, the outline scenario output process shown in step S805 will be specifically described. FIG. 11 is a flowchart showing a schematic scenario output processing procedure shown in step S805. In the flowchart of FIG. 11, the verification scenario creation device replaces the command registered in step S1002 of FIG. 10 with a general scenario command (step S1101). At this time, the commands registered in step S1002 are replaced with general scenario commands in the registered order.

  Then, the replaced general scenario command is output to the general scenario template (step S1102). Specifically, the general scenario commands replaced in step S1101 are listed in order in the part from “scenario () {” to the next “}” of the general scenario template shown in FIG.

  Next, it is determined whether all commands registered in step S1002 have been replaced with general scenario commands (step S1103). If not all commands have been replaced (step S1103: No), the process returns to step S1101 and a series of processes are repeated.

  When all the commands are replaced (step S1103: Yes), the created schematic scenario is output (step S1104), and the series of processes according to this flowchart is terminated. FIG. 12 is an explanatory diagram illustrating an example of a schematic scenario output by the verification scenario creation device.

  The outline scenario is a framework for the verification scenario. The user can confirm the outline of the verification item by the outline scenario output intermediately. If the user notices an error in the contents defined in the general scenario, the general scenario can be corrected at this stage. For this reason, after a verification scenario is finally created, rework can be reduced and the verification work can be made more efficient as compared with a case where a correction portion is searched for and corrected.

  Here, a scenario number is assigned to the output schematic scenario in the format of “path number of path analysis result (convert UC to UCV) −P (number indicating output order)”. Specifically, for example, when the path number is “UC01-B01”, the scenario number is “UCV01-B01-P01”.

  As described above, the user can automatically create a summary scenario by inputting a path analysis result, a summary scenario command group, a summary scenario template, and a path analysis definition file to the verification scenario creation device. In this way, by creating a schematic scenario that does not depend on setting parameters when performing logical verification in advance according to the verification target, logical verification independent of the verification target architecture can be performed.

  Furthermore, the user can correct the wrong part in the middle of the logic verification work by confirming the contents of the output outline scenario. At this time, since the user only has to correct the fragmented portion of the general scenario, rework due to the correction work can be reduced. In addition, since a verification scenario can be created using a corrected appropriate general scenario, highly accurate logic verification can be realized.

<Verification scenario creation process>
Next, verification scenario creation processing in the verification scenario creation device according to the embodiment of the present invention will be described. The verification scenario creation device creates a verification scenario based on the input general scenario, register definition file, and verification item table.

  The verification scenario is used for logic simulation when performing logic verification. If the contents of this verification scenario are incorrect, highly accurate logic verification cannot be performed. For this reason, in the verification scenario creating apparatus according to the embodiment of the present invention, an appropriate verification scenario can be created by using the general scenario confirmed by the user.

<Register definition file>
First, the register definition required when creating a verification scenario will be described. FIG. 13 is an explanatory diagram showing an example of a register definition file. Here, the register definition file indicates definitions related to registers in the CPU 401. Specifically, for example, in the register definition file, the module name, the start address of the function indicated by the module name, the register name, the bit width of the register, the module to which it belongs, the bit description (start bit position, end bit position, initial Value, typical value, maximum value, minimum value) and the like are defined. In the register definition file, these definitions are described for each register.

<Verification item list>
Next, a verification item table necessary for creating a verification scenario will be described. FIG. 14 is a chart (part 1) illustrating an example of a verification item table showing verification items when performing logic verification. FIG. 15 is a diagram (part 2) illustrating an example of a verification item table showing verification items when performing logical verification.

  FIG. 14 shows an overall parameter table 1400 as a verification item table and a parameter definition table 1410 regarding control system register values. The overall parameter table 1400 shows verification items for each scenario number when the logical verification is actually performed. The user can examine the validity of the verification item when performing the logic verification by checking the contents of the overall parameter table 1400.

  The overall parameter table 1400 is created based on the contents of a parameter definition table 1410 and parameter definition tables 1510 and 1520 described later. Specifically, for example, when the user operates the keyboard 110, a value is input to the template of the overall parameter table 1400, and the overall parameter table 1400 is completed. In addition, the user can automatically create the entire parameter table 1400 by inputting a combination definition file to the verification scenario creating apparatus.

  The parameter definition table 1410 defines parameters related to the control system registers that must be set. For example, when there is a register (“ModeRegister” shown in FIG. 14) having a function capable of changing the control of the operation, the operation mode (synchronization method, vertical magnification, horizontal magnification) is considered in consideration of the combination of the functions. A parameter corresponding to (magnification) is defined in the parameter definition table 1410. Here, a synchronization method, a vertical magnification and a horizontal magnification are set as verification items of the control system.

  “ModeRegister” shown in the parameter definition table 1410 is a register having a storage capacity of 5 bits, and each bit is given a name. Specifically, the fourth bit of “ModeRegister” is named “SYNC”, the second bit and the third bit are “VMR”, and the 0th bit and the first bit are named “HMR”. .

  Then, each bit in “ModeRegister” can be used to represent the contents shown in the parameter definition table 1410. Specifically, for example, when “0” is inserted in the fourth bit (“SYNC”) of “ModeRegister”, the content “synchronize with an external signal” is indicated, and the fourth bit (“SYNC”) of “ModeRegister” is displayed. When “1” is entered in “)”, the content “not synchronized with external signal” can be represented.

  Next, FIG. 15 shows a parameter definition table 1510 regarding the data system register value (part 1) and a parameter definition table 1520 regarding the data system register value (part 2). Here, the data system has no dependency on the control system registers. For all combinations of the control system register setting values described above, the logic verification is performed by combining the data system register setting values. Here, conversion coefficients (parameter definition table 1510) and interrupt timing (parameter definition table 1520) are set as data system verification items.

  In the parameter definition table 1510, conversion coefficient parameters are defined by three registers “MINMAX”, “K0”, and “K1”. Specifically, the contents shown in the parameter definition table 1510 can be expressed using the bits in “MINMAX”, “K0”, and “K1”.

  Also, in the parameter definition table 1520, the interrupt timing is defined by the registers “ActiveStartLine1” and “ActiveStartLine2”. Specifically, the contents of the parameter definition table 1520 can be expressed using the bits in “ActiveStartLine1” and “ActiveStartLine2”.

  The parameter definition table 1410, the parameter definition table 1510, and the parameter definition table 1520 are created manually by the user. Specifically, for example, the user arbitrarily sets verification items corresponding to verification targets to be logically verified in the parameter definition table template, and inputs values corresponding to the verification items by operating the keyboard 110 or the like. A definition table 1410, a parameter definition table 1510, and a parameter definition table 1520 are created. In addition, a chart showing definitions regarding parameters is created according to the verification target.

  Then, the user creates an overall parameter table 1400 based on the contents of the parameter definition table 1410, the parameter definition table 1510, and the parameter definition table 1520. Finally, the verification scenario creation device extracts parameters from the overall parameter table 1400 and creates a verification scenario from the above-described general scenario and register definition file.

  By creating a plurality of tables corresponding to the entire parameter table 1400 as know-how of an expert designer, even a beginner can perform logic verification with the same accuracy as an expert.

<Create verification item table using GUI>
Next, processing when the user creates a verification item table corresponding to the overall parameter table 1400 using the GUI will be described. When creating the verification item table on the GUI, the user can create the verification item table by a simple operation input while confirming the contents displayed on the display 108.

  FIG. 16 is an explanatory diagram showing an overview when a verification item table is created using a GUI. Even when the verification item table is created using the GUI, the parameter definition table 1410, the parameter definition table 1510, and the parameter definition table 1520 are first created by the user's manual work.

  Then, the user creates a combination on the GUI according to the parameter type (control system / data system), importance, item, etc. defined in the parameter definition table 1410, parameter definition table 1510, and parameter definition table 1520. Create a verification item table. In addition, the user can automatically create a verification scenario based on input data by inputting the created verification item table, outline scenario, and register definition to the verification scenario creation device.

  Here, a specific process when the verification item table is created using the GUI will be described. FIG. 17 is an explanatory diagram showing the display contents (part 1) when the verification item table is created. As shown in FIG. 17, when creating the verification item table using the GUI, first, a combination assist screen 1700 is displayed on the display 108.

  The combination assist screen 1700 shows the order of combinations when a combination is automatically created. Here, the order of combination is set in advance, but the order and contents of the combination may be arbitrarily changed by the user.

  The user can confirm the order of combination by visually recognizing the contents of the combination assist screen 1700. Next, when the user operates the cursor displayed on the display 108 with the mouse 111 or the like and clicks the “next button”, the display content on the display 108 is switched.

  FIG. 18 is an explanatory diagram showing the display contents (part 2) when the verification item table is created. FIG. 18 shows selectable setting methods when creating a combination. Specifically, for example, the combination assist screen 1800 shows setting methods such as “create all combinations”, “create combinations while specifying conditions”, and “read combination definition file”.

  Here, the user can select a setting method when creating a combination. The combination definition file defines a conditional expression created by an external editor or the like. A combination can be automatically created by inputting the combination definition file to the verification scenario creation device. Hereinafter, a case where “Create all combinations” is selected will be described.

  When the user selects a setting method and clicks the “Next button”, the display content on the display 108 is switched. FIG. 19 is an explanatory diagram showing the display contents (part 3) when the verification item table is created. A combination assist screen 1900 shown in FIG. 19 displays a combination for the importance specified by the user as a condition for creating a combination. Here, nothing has been specified by the user yet, so nothing is displayed on the combination assist screen 1900.

  Here, when the user clicks the “edit button” on the combination assist screen 1900, the display content of the display 108 is switched. FIG. 20 is an explanatory diagram showing the display contents (part 4) when the verification item table is created. FIG. 20 shows a combination editing screen 2000 displayed on the display 108 when a combination for importance is designated.

  Here, the user can edit combinations for importance. First, the user selects a control system item as a “condition”. Specifically, for example, the user operates the mouse 111 to select an item to be designated as “condition” from the list 2001 by drag and drop.

  Next, the user selects an item of the data system as “target”. Specifically, for example, the user operates the mouse 111 to select an item to be designated as “target” from the list 2001 by drag and drop. Here, the list 2001 is a list of control system items shown in the parameter definition table 1410 (see FIG. 14) and data system items shown in the parameter definition tables 1510 and 1520 (see FIG. 15).

  FIG. 21 is an explanatory diagram showing the display contents (No. 5) when the verification item table is created. FIG. 21 shows a combination editing screen 2100 after editing combinations for importance. Here, “synchronization method” is selected as “condition”, and importance is set to “A”. Further, “horizontal magnification” is selected as the “condition”, and the importance is set to “C”.

  In addition, “conversion coefficient” is selected as “target”, and importance is set to “A”. Furthermore, “ALL” is selected as the “target”, and the importance is set to “A” and “B”. Here, “ALL” indicates that all items are selected. It should be noted that all values can be taken for items not selected here. Specifically, for example, when “synchronization method: A” is set as “condition” and “conversion coefficient: A” is set as “target”, other “vertical magnification” and “horizontal magnification” are set. As for “interrupt timing”, all values can be taken.

  In the combination editing screen 2100, a combination of the selected “condition” and “target” is set as a verification item when performing logical verification. When “condition” and “target” shown in the combination edit screen 2100 are combined, the “condition” and “target” shown in the same row on the combination edit screen 2100 are combined.

  On the combination editing screen 2100, when “condition” is not designated as in the blank 2101, a combination is created according to the “condition” designated above the blank 2101. As described above, a plurality of “targets” can be designated for one “condition”.

  When the editing of the combination with respect to the importance is completed and the user clicks the “save button” on the combination editing screen 2100, the edited content is stored in a recording medium such as the HD 105, and the display content on the display 108 is switched. FIG. 22 is an explanatory diagram showing the display contents (No. 6) when the verification item table is created. The combination assist screen 2200 shown in FIG. 22 displays combinations for the importance specified by the user.

  Here, the user can confirm the combination with respect to the designated importance by visually recognizing the combination assist screen 2200. At this time, if the specified combination is incorrect, the user can return to the combination editing screen 2100 by clicking the “return button”. When the user clicks the “next button” on the combination assist screen 2200, the display content on the display 108 is switched. FIG. 23 is an explanatory diagram showing the display contents (part 7) when the verification item table is created.

  In the combination assist screen 2300 shown in FIG. 23, individual combinations designated by the user are displayed as conditions for creating a combination. An individual combination is a combination created by combining specific “conditions” and “targets” individually. Here, since nothing has been designated by the user, nothing is displayed on the combination assist screen 2300. Here, when the user clicks the “edit button” on the combination assist screen 2300, the display content of the display 108 is switched.

  FIG. 24 is an explanatory diagram showing the display contents (No. 8) when the verification item table is created. In the combination editing screen 2400 shown in FIG. 24, “condition” and “target” are specifically designated. Note that the method for specifying “condition” and “target” is the same as that for specifying a combination for importance, and a description thereof will be omitted.

  Further, when the user clicks a “group button” on the combination edit screen 2400, a plurality of conditions can be represented as one group. A dotted frame 2401 shown on the combination editing screen 2400 represents one group. In this case, the first row and the second row designated as “target” for this group are combined.

  Here, when the editing of the individual combination is completed and the user clicks the “save button” on the combination editing screen 2400, the edited content is stored in a recording medium such as the HD 105, and the display content on the display 108 is switched. . FIG. 25 is an explanatory diagram showing the display contents (No. 9) when the verification item table is created.

  In the combination assist screen 2500 shown in FIG. 25, individual combinations designated by the user are displayed. Here, the user can confirm the designated individual combination by visually recognizing the combination assist screen 2500. At this time, if the designated combination is incorrect, the user can return to the combination editing screen 2400 by clicking the “return button”.

  When the user clicks the “next button” on the combination assist screen 2500, the display content of the display 108 is switched. FIG. 26 is an explanatory diagram showing display contents (No. 10) when the verification item table is created. In the combination assist screen 2600 shown in FIG. 26, combinations and individual combinations for the importance specified by the user are collectively displayed.

  Here, the user can confirm all combinations designated by the user by visually recognizing the combination assist screen 2600. The combination displayed on the combination assist screen 2600 is divided into an importance condition and an individual condition. The control system is represented on the left side and the data system is represented on the right side. Under what conditions the user performs the combination, It can be judged intuitively.

  When the user clicks “Next” on the combination assist screen 2600, a verification item table corresponding to the designated combination is automatically created. When the “combination number calculation button” on the combination assist screen 2600 is clicked, the number of combinations when a combination is created is calculated.

<Verification item table creation process>
Here, processing when creating the verification item table using the GUI will be described. First, the verification scenario creation apparatus, based on the parameter definition table 1410, the parameter definition table 1510, and the parameter definition table 1520, shows specific contents (hereinafter referred to as “content levels”) in which the importance conditions specified by the user are represented in each table. "). For example, the importance level condition “synchronization method: A” is converted into a content level “synchronization method: synchronize” based on the parameter definition table 1410.

  In this way, all importance conditions are converted into content levels, and then a list of “conditions” and “controls” is created by user operation input. Hereinafter, a list created using the importance condition and the individual condition shown in the combination assist screen 2600 (see FIG. 26) as examples will be described. FIG. 27 is an explanatory diagram showing a list (part 1) of “conditions” and “controls”.

  First, a condition list regarding the importance condition shown in the combination assist screen 2600 (“condition” shown in FIG. 27) will be described. The condition list is for each item of “synchronization method”, “horizontal magnification”, “conversion coefficient” and “interrupt timing” shown in the parameter definition table 1410, the parameter definition table 1510 and the parameter definition table 1520. It is the table | surface which showed what kind of content can be taken.

  Next, a control list (“control” shown in FIG. 27) related to the importance condition shown in the combination assist screen 2600 will be described. The control list is a list of controls specified by the condition specification. As an initial setting, a list 2720 representing all possible contents of each item shown in the parameter definition table 1410, the parameter definition table 1510, and the parameter definition table 1520 is set for each item. Each list 2720 is assigned a subscript number “0”. This subscript number is used in the condition list.

  Here, the importance condition is “synchronization method: A” and “conversion coefficient: A”, and the content level of the importance condition is “synchronization method: synchronized” and “conversion coefficient: initial value, typical value”. It is. The user creates a list corresponding to the importance condition and adds it to the control list. Specifically, since there is a condition of “conversion coefficient: initial value, typical value” as the importance condition, the user creates a list 2721 that can only take “initial value” or “typical value” as the “conversion coefficient”. And add it to the control list. The list 2721 is assigned a subscript number “1”.

  Furthermore, “horizontal magnification: C” and “all items in the data system: A”, “horizontal magnification: C”, and “all items in the data system: B” are designated as the importance conditions. Here, since there are conditions of importance “A” and “B” for “all items in the data system”, “NTSC typical value”, “PAL typical value”, and “minimum value” are set as “interrupt timing”. A list 2722 (that is, a list that does not include content related to the importance “C”) that can be taken by any one of the lists is created and added to the control list. Further, the index number “1” is attached to the list 2722.

  Then, the condition list is completed using the subscript number attached to each list in the control list. Specifically, for example, in the “Synchronization method” list 2701 in the condition list, the subscript number “0” is added to the “control (vertical magnification)” portion, and the subscript number “0” is added to the “control (horizontal magnification)” portion. ”And“ control (conversion coefficient) ”are subscript numbers“ 1 ”and“ control (interrupt timing) ”are subscript numbers“ 0 ”to complete the table. Since the item is the same as the item shown in the list 2701, the subscript number “-” is entered in the “control (synchronization method)” part. The table is also completed in the same manner for the “horizontal magnification” list 2702 in the condition list.

  Regarding the individual conditions, a condition list and a control list are created in the same manner as the importance condition. FIG. 28 is an explanatory diagram showing a list (part 2) of “conditions” and “controls”. First, based on the parameter definition table 1410, the parameter definition table 1510, and the parameter definition table 1520, the individual conditions specified by the user are converted to the content level.

  Next, a control list corresponding to the individual conditions is created. In the control list (“control” shown in FIG. 28), a list 2720 which is an initial setting and lists 2721 and 2722 created in accordance with the importance condition are set. Here, since the “vertical magnification: 8/9 times”, “horizontal magnification: 8/9 times”, and “conversion coefficient: typical value, initial value” are designated as individual conditions, the user corresponds to these. Create a list.

  Specifically, the user creates a list 2821 corresponding to the individual condition “vertical magnification: 8/9 times” and a list table 2822 corresponding to the individual condition “horizontal magnification: 8/9 times”. Further, the index number “1” is assigned to the list table 2821, and the index number “1” is assigned to the list table 2822. In addition, regarding the list corresponding to the individual condition “conversion coefficient: typical value, initial value”, a list 2722 showing the same contents is created in advance, and this is used.

  Then, the condition list is completed using the subscript number attached to each list in the control list. The contents of the condition list have priority over the contents specified as the individual conditions over the contents specified as the importance condition. Specifically, regarding “control (vertical magnification)” of “horizontal magnification” in the condition list, “control (vertical magnification): 0” in the list 2702 shown in FIG. In 2801, “control (vertical magnification): 1”. In this way, the content designated as the individual condition is prioritized and the corresponding subscript number is entered in the condition list.

  Then, the verification scenario creating apparatus creates a combination based on the condition list and the control list created in consideration of the importance condition and the individual condition. FIG. 29 is an explanatory diagram of an example of a combination definition file. In the combination definition file shown in FIG. 29, a definition relating to the created combination is described based on the condition list and the control list. Further, the number of combinations shown in the combination definition file is the number of items shown in the parameter definition table 1410, the parameter definition table 1510, and the parameter definition table 1520.

  In the combination definition file, the number of combinations related to the specified item is defined. Specifically, for example, in the syntax related to “synchronization method” in the combination definition file, “[subscript]” after “control element” is subscript number “0” corresponding to “synchronization method” in the control list. Enters. In addition, “i” after “[subscript]” contains the number of contents shown in the list with the subscript number “0”. Here, since the contents that can be taken as the synchronization method are “synchronize” or “not synchronize”, “0, 1” is entered in “i”.

  Further, in the syntax related to “vertical magnification” in the combination definition file, the subscript number “0, 1” corresponding to “vertical magnification” in the control list is entered in “subscript” after “control element”. In addition, “i” after “subscript” contains the number of contents shown in each list attached with the subscript number “0, 1”. Here, as the contents that can be taken as the vertical magnification, “same size”, “2 times”, “4 times”, and “8/9 times” are displayed in the list with the subscript number “0”. In the table with the subscript number “1”, “8/9 times” is shown. For this reason, “0” to “3” are entered in “j”.

  In this way, numbers are entered for all items, and values are entered in “k” and “l”. The number of combinations can be calculated by multiplying the numbers in “i”, “j”, “k”, and “l”. Also, if a combination with the same content occurs when creating a combination, only one is left and the rest is deleted. When creating combinations for all the contents, all the values to be put in the “subscript” after the “control element” are set to “0”.

  The combination definition file once created is recorded on a recording medium such as the HD 105 or the FD 107 and can be used in subsequent logic verification. Specifically, on the assist screen 1800 (see FIG. 18), when the setting method for creating a combination is “read combination definition file”, the combination definition file recorded in the HD 105 or the like is displayed. Any combination definition file can be selected.

  30, 31 and 32 are explanatory diagrams showing the contents that can be taken for the item for which the condition is specified. 30 to 32, the contents that can be taken for the items for which conditions are specified are highlighted (gray portions in the figure). Then, the number of combinations corresponding to each item can be calculated by multiplying each item by the number of possible contents. Specifically, for example, the number of combinations corresponding to the “synchronization method” is “1 × 4 × 4 × 2 × 5”. Thus, the total number of combinations can be obtained by calculating the number of combinations corresponding to each item and finally adding the calculation results.

  FIG. 33-1 is an explanatory diagram of an example of the verification item table. In the verification item table 3300, combinations created based on the above-described condition list and control list are displayed from the beginning in a portion 3301 surrounded by a dotted line. Here, when the user clicks the scenario number button 3302, the scenario number is displayed in the scenario list 3303. While confirming the contents displayed in the verification item table 3300, the user selects a scenario number corresponding to each content by dragging and dropping from the scenario list 3303 to complete the verification item table.

  Further, the verification scenario creation device may have a function of determining whether or not the scenario number selected by the user matches the content displayed in the verification item table 3300. Specifically, for example, it may be determined whether the verification item displayed in the verification item table 3300 matches the description content of the general scenario. Furthermore, when it is not suitable, for example, by changing the background color of the cell in which the non-conforming item is displayed in the verification item table 3300 and highlighting it, the user is notified of the non-conforming item. Also good.

  FIG. 33-2 is an explanatory diagram of an example when the verification items in the verification item table do not match the description contents of the general scenario. FIG. 33B shows a schematic scenario portion 3310 and a verification item table portion 3320 corresponding to the same pass number. Here, a part 3310 of the general scenario is defined as “WRITE, SYNC, 0”. For this reason, the only content that can be taken as a verification item is “synchronization method: synchronize”.

  However, the contents of “synchronization method: not synchronized” are shown in the cell 3321 of the part 3320 of the verification item table. In this case, the verification scenario creation device determines that the verification item displayed in the verification item table does not match the description contents of the general scenario, and highlights the cell 3321 by changing the background color.

  Returning to the description of FIG. 33-1, when the user selects a scenario number, a pass number corresponding to the scenario number is automatically displayed. Then, when the user selects one that actually creates a verification scenario from the scenario numbers displayed in the verification item table 3300, the display content of the display 108 is switched to the scenario output screen. Furthermore, when the user clicks a scenario output button on the scenario output screen, a verification scenario corresponding to the selected scenario number is automatically created and output.

<Verification scenario output processing procedure>
Next, the procedure of the verification scenario output process in the verification scenario creation device according to the embodiment of the present invention will be described. 34 and 35 are flowcharts showing the procedure of the verification scenario output process in the verification scenario creating device according to the embodiment of the present invention. In the flowchart shown in FIG. 34, the verification scenario creating apparatus determines whether or not an input of a scenario number has been accepted (step S3401).

  The scenario number is input, for example, when the user selects from the scenario numbers displayed in the verification item table 3300 shown in FIG. Next, the parameter definition table to be referenced is read (step S3402). The parameter definition table is, for example, the above-described parameter definition table 1410, parameter definition table 1510, parameter definition table 1520, or the like. Here, the input parameter definition table 1410, parameter definition table 1510, and parameter definition table 1520 are read in order.

  Next, a register to be used is set based on the read parameter definition table (step S3403). Specifically, for example, when the parameter definition table 1410 is read, the register to be used is set to “ModeRegister”. Based on the read parameter definition table, an item to be referred to is set (step S3404). Specifically, for example, “synchronization method”, “vertical magnification”, and “horizontal magnification” shown in the parameter definition table 1410 are sequentially set as items to be referred to.

  Next, based on the read parameter definition table, a register value related to the item set in step S3404 is set (step S3405). Specifically, register values corresponding to the contents are set in the order defined in the parameter definition table. Then, an address corresponding to the register set in step S3403 is acquired from the register definition file (step S3406), and the process proceeds to step S3501 shown in the flowchart of FIG.

  In step S3501 of the flowchart of FIG. 35, the verification scenario creating apparatus determines whether or not the set register is defined in the general scenario. If it is defined (step S3501: Yes), it is determined whether a register value is set in the general scenario (step S3502).

  If the register value is set in step S3502 (step S3502: Yes), whether or not the register value set in step S3405 shown in the flowchart of FIG. 34 is the same as the register value set in the general scenario. Is determined (step S3503).

  If they are the same (step S3503: YES), the command described in the general scenario is converted (step S3504). Specifically, the command described in the general scenario is converted from “WRITE: cpu_write (address, value)” to “READ: cpu_read (address)”. If no register value is set in step S3502 (step S3502: NO), the process proceeds to step S3504.

  In step S3503, when the register values are not the same (step S3503: No), the user is notified that the register values are different (step S3505). Specifically, for example, the display 108 shows “Register values are different. Or a comment such as “” may be displayed as a warning and notified to the user. Further, when a warning is displayed, the user can make a correction corresponding to the content displayed in the warning in the middle of the verification scenario output process.

  In step S3501, if the set register is not defined in the general scenario (step S3501: No), the user is notified that the corresponding register is not defined in the general scenario (step S3506). Specifically, for example, “ModeRegister” is not defined in the summary scenario. Or a comment such as “” may be displayed as a warning and notified to the user. In this case as well, the correction corresponding to the warning-displayed content can be performed in the middle of the verification scenario output process, as described above.

  Next, it is determined whether or not register values have been set for all the contents defined in the parameter definition table (step S3507). Here, when it has not set (step S3507: No), it returns to step S3405 and repeats a series of processings. Note that when returning to step S3405, a register value is set for the content immediately below in the parameter definition table.

  If it is set in step S3507 (step S3507: Yes), it is determined whether all items defined in the parameter definition table have been set (step S3508). Here, when it has not set (step S3508: No), it returns to step S3404 and repeats a series of processings. Note that when returning to step S3404, the next lower item in the parameter definition table is set.

  If it is set in step S3508 (step S3508: Yes), it is determined whether all input parameter definition tables have been read (step S3509). Here, when not reading (step S3509: No), it returns to step S3402 and repeats a series of processing. Note that when returning to step S3402, the next parameter definition table is read in the order of input.

  If it is read in step S3509 (step S3509: Yes), it is determined whether there is a register value that has not been replaced in the verification scenario (step S3510). If there is a register value that has not been replaced (step S3510: YES), the value defined in the register definition file is set (step S3511). Specifically, register values that are not replaced are set to “initial value, maximum value, typical value” defined in the register definition file.

  In step S3510, if there is no register value that has not been replaced (step S3510: No), a simulation scenario and a parameter file are output as a verification scenario (step S3512), and a series of processes according to the flowcharts shown in FIGS. FIG. 36 is an explanatory diagram showing an example of a simulation scenario. FIG. 37 is an explanatory diagram showing an example of a parameter file.

  The simulation scenario shown in FIG. 36 includes “synchronization method: synchronize”, “vertical magnification: equal magnification”, “horizontal magnification: equal magnification”, “conversion coefficient: initial value”, and “interrupt timing: NTSC typical value” as verification items. "Is specified. By using this simulation scenario for logic simulation, logic verification of an LSI or the like can be performed.

  Also, the parameter file shown in FIG. 37 shows combinations when performing logic verification, and is used, for example, when a numerical value such as an expected value is obtained using another tool or the like.

  According to the verification scenario creation device, the user can output a verification scenario corresponding to the selected scenario number by selecting a desired scenario number from the scenario numbers displayed in the verification item table 3300. In this way, the verification scenario creation device can output a verification scenario that covers the contents described in the general scenario and the verification item table 3300. And the user can implement | achieve highly accurate logic verification by performing logic verification using this verification scenario.

  As described above, according to the verification scenario creation program, the recording medium, the verification scenario creation device, and the verification scenario creation method, by presenting the verification item table 3300 to the user during the verification, the logic verification is performed. The validity of the verification item can be confirmed, and an appropriate verification scenario can be created. Therefore, the user can perform highly accurate logic verification using an appropriate verification scenario.

  Further, the user can create the verification item table 3300 by performing a simple operation input on the GUI. When the verification item table 3300 is created on the GUI and there is an error in the verification item shown in the verification item table 3300, the verification item is displayed in a display format that can be intuitively recognized by the user. Can be highlighted. Thereby, it is possible to improve the convenience of the user when the verification item table 3300 is corrected.

  If there is an error in the contents of the verification item table 3300, it is possible to make corrections such as adding or deleting verification items before creating the verification scenario, and create an appropriate verification scenario based on the corrected verification items. can do. For this reason, it is possible to reduce rework due to re-execution of logic verification, and it is possible to improve the efficiency of verification work.

  The verification scenario creation method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

(Supplementary note 1) An input process for receiving an input of a path analysis result related to a verification target;
A general scenario data generation step for generating general scenario data related to the verification target logical verification based on the path analysis result input in the input step;
A list display step for displaying a list representing a combination of verification items necessary for logical verification related to the verification target selected from a set of verification items related to the logical verification on a display screen for each path analysis result;
From the list displayed by the list display step, a selection step for accepting selection of a combination of verification items regarding an arbitrary path analysis result by a user operation input,
A verification scenario data generation step for generating verification scenario data related to the logical verification using the combination of verification items selected in the selection step and the general scenario data generated by the general scenario data generation step;
A verification scenario creation program characterized by causing a computer to execute.

(Additional remark 2) The outline scenario data display process which displays the outline scenario data on the display screen,
Causing the computer to execute a determination step of determining whether or not the general scenario data displayed on the display screen by the general scenario data display step has been corrected by the user's operation input;
The verification scenario data generation step includes:
The verification scenario creation program according to appendix 1, wherein verification scenario data related to the logic verification is generated based on a determination result determined by the determination step.

(Appendix 3) The list display step
The path analysis is performed by selecting a combination of verification items necessary for logical verification related to the verification target from the set of verification items related to the logical verification displayed on the display screen by the user's operation input. The verification scenario creation program according to appendix 1 or 2, wherein the verification scenario creation program is displayed for each result.

(Additional remark 4) Let the said computer perform the 2nd determination process made to determine whether the verification item of the list displayed on the said display screen and the description content of the said outline scenario data are suitable,
The list display step includes
Any one of appendices 1 to 3, wherein the verification items of the list that do not match the description content of the general scenario data are highlighted based on the determination result determined by the second determination step. The verification scenario creation program described in one.

(Additional remark 5) The said computer-readable recording medium which recorded the verification scenario creation program as described in any one of Additional remark 1-4.

(Appendix 6) An input means for receiving an input of a path analysis result related to a verification target;
Based on the path analysis result input by the input means, schematic scenario data generating means for generating schematic scenario data related to the verification target logical verification;
Display means having a display screen;
A list representing a combination of verification items necessary for logical verification related to the verification target selected from the set of verification items related to the logical verification by controlling the display screen is displayed on the display screen for each path analysis result. Display control means for
A selection unit that receives selection of a combination of verification items related to an arbitrary path analysis result from a list displayed by the display control unit;
Verification scenario data generating means for generating verification scenario data related to the logical verification using the combination of verification items selected by the selection means and the schematic scenario data generated by the schematic scenario data generating means;
A verification scenario creating device comprising:

(Appendix 7) The display control means displays the summary scenario data generated by the summary scenario data generation means on the display screen,
Determination means for determining whether or not the general scenario data displayed on the display screen by the display control means has been corrected by the user's operation input;
The verification scenario data generation means includes:
The verification scenario creating apparatus according to appendix 6, wherein verification scenario data relating to the logical verification is generated based on a determination result determined by the determination unit.

(Appendix 8) The display control means includes:
The path analysis is performed by selecting a combination of verification items necessary for logical verification related to the verification target from the set of verification items related to the logical verification displayed on the display screen by the user's operation input. 8. The verification scenario creation device according to appendix 6 or 7, wherein the verification scenario creation device displays each result.

(Supplementary note 9)
Determining whether the verification items of the list displayed on the display screen and the description contents of the summary scenario data are compatible,
The display control means includes
The verification item of the list that does not match the description content of the general scenario data is highlighted based on the determination result determined by the determination means. The verification scenario creation device described.

(Additional remark 10) The input process which receives the input of the path | pass analysis result regarding a verification object,
Based on the path analysis result input in the input step, a schematic scenario data generating step for generating schematic scenario data related to the verification target logical verification;
A list display step for displaying, on the display screen for each path analysis result, a list representing a combination of verification items necessary for the logical verification related to the verification target selected from the set of verification items related to the logical verification;
A selection step for accepting selection of a combination of verification items related to an arbitrary path analysis result by a user operation input from the list displayed by the list display step;
A verification scenario data generation step for generating verification scenario data related to the logical verification using the combination of verification items selected in the selection step and the general scenario data generated by the general scenario data generation step;
A verification scenario creation method characterized by including

  As described above, the verification scenario creation program, the recording medium, the verification scenario creation device, and the verification scenario creation method according to the present invention are useful for LSI logic verification.

It is a block diagram which shows the hardware constitutions of the verification scenario creation apparatus concerning embodiment of this invention. It is a block diagram which shows the functional structure of the verification scenario creation apparatus concerning embodiment of this invention. It is a flowchart which shows the verification scenario creation processing procedure in the verification scenario creation apparatus concerning embodiment of this invention. It is explanatory drawing which shows the outline | summary of a process of the verification scenario creation apparatus concerning embodiment of this invention. It is a use case figure which shows the outline of an image data transfer function. It is explanatory drawing which shows an example of a path | pass analysis result. It is explanatory drawing which shows an example of a general scenario command group. It is explanatory drawing which shows an example of an outline scenario template and a path analysis definition file. It is a flowchart which shows the procedure of the general | schematic scenario output process in the verification scenario creation apparatus concerning embodiment of this invention. It is a flowchart which shows the CPU model recognition process procedure shown by step S803. It is a flowchart which shows the command registration processing procedure shown by step S804. It is a flowchart which shows the general | schematic scenario output process procedure shown by step S805. It is explanatory drawing which shows an example of the general | schematic scenario output by the verification scenario creation apparatus. It is explanatory drawing which shows an example of a register definition file. It is a chart (the 1) which shows an example of the verification item table showing the verification item at the time of performing logic verification. It is a chart (the 2) which shows an example of the verification item table | surface showing the verification item at the time of performing logic verification. It is explanatory drawing which shows the outline | summary at the time of producing a verification item table | surface using GUI. It is explanatory drawing which shows the display content (the 1) on a display in producing a verification item table | surface. It is explanatory drawing which shows the display content (the 2) of a display in producing a verification item table | surface. It is explanatory drawing which shows the display content (the 3) on the display in producing a verification item table | surface. It is explanatory drawing which shows the display content (the 4) on producing a verification item table | surface. It is explanatory drawing which shows the display content (the 5) on the display at the time of producing a verification item table | surface. It is explanatory drawing which shows the display content (the 6) on the display in producing a verification item table | surface. It is explanatory drawing which shows the display content (the 7) at the time of producing a verification item table | surface. It is explanatory drawing which shows the display content (the 8) at the time of producing a verification item table | surface. It is explanatory drawing which shows the display content (the 9) on the display at the time of creating a verification item table | surface. It is explanatory drawing which shows the display content (the 10) on a display in producing a verification item table | surface. It is explanatory drawing which shows the list (the 1) of "condition" and "control". It is explanatory drawing which shows the list (the 2) of "condition" and "control". It is explanatory drawing which shows an example of a combination definition file. It is explanatory drawing which shows the content which can be taken with respect to the item by which conditions were designated. It is explanatory drawing which shows the content which can be taken with respect to the item by which conditions were designated. It is explanatory drawing which shows the content which can be taken with respect to the item by which conditions were designated. It is explanatory drawing which shows an example of a verification item table | surface. It is explanatory drawing which shows an example when the verification item of a verification item table | surface and the description content of an outline scenario do not match. It is a flowchart which shows the procedure of the verification scenario output process in the verification scenario creation apparatus concerning embodiment of this invention. It is a flowchart which shows the procedure of the verification scenario output process in the verification scenario creation apparatus concerning embodiment of this invention. It is explanatory drawing which shows an example of a simulation scenario. It is explanatory drawing which shows an example of a parameter file.

Explanation of symbols

DESCRIPTION OF SYMBOLS 201 Input part 202 General scenario data generation part 203 Display part 204 Display control part 205 Selection part 206 Verification scenario data generation part 207 Judgment part 401 CPU
402 External block 403 Memory 404 Image processing apparatus

Claims (5)

An input process for accepting an input of a path analysis result regarding the verification target;
A general scenario data generation step for generating general scenario data related to the verification target logical verification based on the path analysis result input in the input step;
A list display step for displaying a list representing a combination of verification items necessary for logical verification related to the verification target selected from a set of verification items related to the logical verification on a display screen for each path analysis result;
From the list displayed by the list display step, a selection step for accepting selection of a combination of verification items regarding an arbitrary path analysis result by a user operation input,
A verification scenario data generation step for generating verification scenario data related to the logical verification using the combination of verification items selected in the selection step and the general scenario data generated by the general scenario data generation step;
A verification scenario creation program characterized by causing a computer to execute. An outline scenario data display step for displaying the outline scenario data on the display screen;
Causing the computer to execute a determination step of determining whether or not the general scenario data displayed on the display screen by the general scenario data display step has been corrected by the user's operation input;
The verification scenario data generation step includes:
The verification scenario creation program according to claim 1, wherein verification scenario data relating to the logical verification is generated based on a determination result determined by the determination step.   A recording medium readable by the computer on which the verification scenario creating program according to claim 1 is recorded. An input means for receiving an input of a path analysis result related to the verification target;
Based on the path analysis result input by the input means, schematic scenario data generating means for generating schematic scenario data related to the verification target logical verification;
Display means having a display screen;
Display control for controlling the display screen and displaying a list representing a combination of verification items necessary for the logical verification related to the verification target selected from the set of verification items related to the logical verification for each path analysis result Means,
A selection unit that receives selection of a combination of verification items related to an arbitrary path analysis result from a list displayed by the display control unit;
Verification scenario data generating means for generating verification scenario data related to the logical verification using the combination of verification items selected by the selection means and the schematic scenario data generated by the schematic scenario data generating means;
A verification scenario creating device comprising: An input process for receiving an input of a path analysis result related to the verification target;
Based on the path analysis result input in the input step, a schematic scenario data generating step for generating schematic scenario data related to the verification target logical verification;
A list display step for displaying, on the display screen for each path analysis result, a list representing a combination of verification items necessary for the logical verification related to the verification target selected from the set of verification items related to the logical verification;
A selection step for accepting selection of a combination of verification items related to an arbitrary path analysis result by a user operation input from the list displayed by the list display step;
A verification scenario data generation step for generating verification scenario data related to the logical verification using the combination of verification items selected in the selection step and the general scenario data generated by the general scenario data generation step;
A verification scenario creation method characterized by including

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