JP2007316805A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by preventing the deterioration of processing performance due to dynamic clock control in a semiconductor integrated circuit. <P>SOLUTION: A main circuit 10 performs access to a subordinate circuit 70 by using a subordinate circuit control signal 11, and a clock gating control circuit 20 senses access from the main circuit 10 to the subordinate circuit 70, and generates a gating control signal 40 as a signal for controlling the ON/OFF of a clock 50 to be generated by a clock generation circuit 60, and to be supplied to the subordinate circuit 70. Furthermore, a clock gating validity control circuit 30 generates a gating permission signal 41 for controlling the validity/invalidity of the gating control signal 40, and the gating control signal 40 validated by the gating permission signal 41 controls the ON/OFF of the clock 50 from the clock generation circuit 60, and controls clock supply to the subordinate circuit 70. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to clock control for the purpose of balancing performance degradation and power saving.

  In recent years, the degree of integration of semiconductor integrated circuits has been dramatically improved by the advancement of semiconductor process miniaturization techniques. For this reason, the circuit scale that can be built in one semiconductor device is increased, and most of the system is realized by one system LSI. At the same time, a volatile memory and a non-volatile memory are connected to the system LSI, and the memory operating frequency increases year by year together with the operating frequency of the system LSI.

  In a conventional semiconductor integrated circuit, a technique for reducing power consumption by supplying a clock only to an operating circuit is introduced. In particular, there is a technique for reducing power consumption by supplying a clock only when accessing a peripheral circuit (see, for example, Patent Document 1).

  Similarly, a technique for reducing power consumption by supplying a clock only when accessing a memory is also disclosed. (For example, refer to Patent Document 2) In this technique, a plurality of banks are grouped together, and clocks are supplied only to groups of banks that are accessed.

FIG. 5 is a diagram showing a conventional configuration example. The semiconductor integrated circuit of FIG. 5 includes a CPU 10 as a main circuit, a subordinate circuit control signal 11, a memory 70 as a subordinate circuit, a clock gating control circuit 20 and a clock generation circuit 60. Conventionally, the clock supply to the memory 70 is directly ON / OFF controlled by the gating control signal 40 generated by the clock gating control circuit 20, and the clock is supplied only when the CPU 10 accesses the memory 70.
Japanese Patent Laid-Open No. 9-237131 JP 2003-122628 A

  However, when the clock control is performed on the memory by the above technique, there is a setup time until the memory is accessible after the supply is started after the clock is stopped. Due to the presence of this setup time, the response time at the time of memory access may deteriorate. In particular, when access to a plurality of bank groups occurs, the clock control of the bank groups is performed depending on the presence or absence of access each time. Therefore, the waiting time due to memory access tends to increase as compared with the case where no clock control is performed. Therefore, the processing time is affected and the processing performance is degraded.

  Further, since the processing time is extended, the period for stopping the clock supply to the main circuit (for example, CPU) accessing the memory is shortened, and the power consumption on the main circuit side is increased.

In order to solve the above problems, the present invention provides:
A semiconductor integrated circuit for dynamically controlling clock supply to a subordinate circuit,
A main circuit for transmitting and receiving a subordinate circuit control signal to the subordinate circuit;
A clock generation circuit for generating a clock signal for the subordinate circuit;
A clock gating control circuit for generating a gating control signal from the subordinate circuit control signal;
A clock gating enable control circuit for generating a gating permission signal for controlling the clock gating enablement for the subordinate circuit,
When the gating permission signal indicates valid, gating control to the clock signal by the gating control signal,
The gating control signal is configured not to perform gating control on the clock signal when the gating permission signal indicates invalidity.

  In the present invention, it is possible to suppress degradation in processing performance by providing a period in which clock control is dynamically performed and a period in which clock control is not performed, and to reduce power consumption as a system.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a configuration diagram of a semiconductor integrated circuit showing Embodiment 1 of the present invention.

  The semiconductor integrated circuit of FIG. 1 includes a CPU 10 as a main circuit, a subordinate circuit control signal 11, a memory 70 as a subordinate circuit, a clock gating control circuit 20, a lock gating effective control circuit 30, and a clock generation circuit 60. It is configured.

  According to such a configuration, the CPU 10 first accesses the memory 70 using the dependent circuit control signal 11. The subordinate circuit control signal 11 is normally connected via a bus, and controls and communicates with the memory 70 using a control signal in accordance with an address, data, and bus protocol.

  The clock gating control circuit 20 senses access from the CPU 10 to the memory 70, and generates a gating control signal 40 that is a signal for controlling ON / OFF of the clock 50 generated by the clock generation circuit 60 to the memory 70.

  Further, the clock gating valid control circuit 30 generates a gating permission signal 41 that controls validity / invalidity of the gating control signal 40. The gating control signal 40 validated by the gating permission signal 41 is used for controlling ON / OFF of the clock 50 generated by the clock generation circuit 60.

  In the present invention, unlike the conventional configuration of FIG. 5, the validity / invalidity of the gating control signal 40 is controlled using the clock gating effective control circuit 30. Although details of the clock gating effective control circuit 30 will be described in the second embodiment, the clock gating effective circuit 30 can control the period during which the conventional gating control signal 40 is enabled or disabled. is there.

  FIG. 3 is an example for explaining the presence / absence of a delay until the dependent circuit is enabled by the gating permission signal 41. In this example, the period during which the gating permission signal 41 validates the gating control signal 40 is the LOW period of the gating permission signal 41. In the period when the gating permission signal 41 is LOW, when the gating control signal 40 generated by detecting access to the memory 70 of the CPU 10 becomes HI, the gating clock 51 is generated with a delay of one cycle. Further, after the gating clock 51 is generated, one cycle is required until the memory 70 becomes accessible, and a total delay of two cycles occurs.

  During the period when the gating permission signal 41 is HI, the gating clock 51 is generated one cycle after the gating permission signal 41 becomes HI. Since the gating clock 51 is supplied to the memory 70 regardless of the HI / LOW of the gating control signal 40, the memory 70 is already accessible when the CPU 10 accesses the memory 70. There is no delay.

  In this example, the cycle until the memory 70 becomes accessible in accordance with the transition from the clock OFF state to the ON state is one cycle. However, a delay further occurs depending on the type of the subordinate circuit.

  According to the configuration of the present invention, memory access frequently occurs during a period when processing performance is required, for example, the CPU, and the access is memory access across a plurality of banks, and the clock control is dynamically performed in units of the plurality of banks. When performing the above, it is possible to prevent the degradation of the processing performance by turning off the dynamic clock control only during the period when the processing performance is required.

  In addition, when the power consumption in the memory is more important than the processing performance, for example, the CPU performs memory access in advance, and the CPU processing time is designed to conceal the data writing / reading time. By performing dynamic clock control, the power consumed by the memory can be reduced.

(Embodiment 2)
FIG. 2 is a configuration diagram of the clock gating effective control circuit 30 showing the second embodiment of the present invention.

  The clock gating effective control circuit 30 shown in FIG. 2 includes a set value circuit 31, a control circuit 32, and a timer / counter circuit 33.

  According to this configuration, first, the period during which the gating permission signal 41 is turned on and the cycle thereof are set in the set value circuit 31. The timer / counter circuit 33 counts with a predetermined clock and notifies the control circuit 32 of the counted number. First, when the gating permission signal 40 is ON, the control circuit 32 turns OFF the gating permission signal 41 when detecting that the gating permission signal 41 set by the setting value circuit 31 is counted during the ON period. Then, the timer / counter circuit 33 is reset, the count number is initialized, and the timer / counter circuit 33 is started to recount. When the control circuit 32 detects that the period value set by the set value circuit 31 is counted while the gating permission signal 40 is OFF, the control circuit 32 turns ON the gating permission signal 41 and resets the timer / counter circuit 33. The count number is initialized, and the timer / counter circuit 33 is started to recount.

  By performing the above-described configuration and operation, it is possible to turn off dynamic clock control only for processes that require periodic processing performance, and it is possible to prevent deterioration in processing performance.

  In addition, since there are a wide variety of applications to be processed by the system LSI, it is difficult to use common setting values for all applications. Therefore, by configuring the set value circuit 31 with a register or a memory, dynamic clock control suitable for the application can be performed by rewriting the set value by an application processed by the LSI.

  Furthermore, the set period and period are not limited to one set, and a plurality of settings can be set. Thereby, it is possible to cope with a case where a plurality of processes are performed. FIG. 4 shows a configuration example of the set value circuit 30.

  The set value circuit 30 in FIG. 4 includes a set value storage circuit 35 and a selection circuit 36. The set value storage circuit 35 is composed of a register or a memory, and the value can be rewritten from the CPU 10. Further, the set values can hold a plurality of combinations. If the values are set values A, B, C..., The set values A, B, C are selected by the selection circuit 36 in accordance with an instruction from the CPU 10. ... Select the set value instructed from... And output it to the control circuit 32.

  In addition, it may be necessary to adjust the timing for starting the effective period. For example, the period timing when the dynamic clock control is turned off at the start of the application depends on the application. Therefore, by setting the phase information in the set value circuit 31 and starting it, the start time of the effective period can be adjusted, and dynamic control suitable for the application can be performed.

  In addition, when a plurality of applications processed by the LSI do not have periodicity, it can be easily imagined that it is difficult to optimally set the above effective period and period. In that case, for example, a plurality of setting values of the ratio between the effective period and the ineffective period of the dynamic clock control are prepared, and a suitable setting value can be found by measuring the processing performance and power.

  The dynamic clock control technology for a semiconductor integrated circuit according to the present invention allows a user to adjust processing performance degradation and low power consumption, and can be applied to a system LSI in general.

Configuration diagram of semiconductor integrated circuit according to the present invention for clock control Configuration diagram of clock gating effective control circuit Timing chart for clock control Configuration diagram of set value circuit Configuration diagram of a conventional semiconductor integrated circuit that performs clock control

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Main circuit 11 Dependent circuit control signal 70 Dependent circuit 20 Clock gating control circuit 30 Clock gating effective control circuit 40 Gating control signal 41 Gating permission signal 50 Clock signal 51 Gating clock signal 60 Clock generating circuit 31 Set value circuit 32 control circuit 33 timer / counter circuit 35 set value storage circuit 36 selection circuit

Claims (4)

A semiconductor integrated circuit for dynamically controlling clock supply to a subordinate circuit,
A main circuit for transmitting and receiving a subordinate circuit control signal to the subordinate circuit;
A clock generation circuit for generating a clock signal for the subordinate circuit;
A clock gating control circuit for generating a gating control signal from the subordinate circuit control signal;
A clock gating enable control circuit for generating a gating permission signal for controlling the clock gating enablement for the subordinate circuit,
When the gating permission signal indicates valid, gating control to the clock signal by the gating control signal,
A semiconductor integrated circuit configured not to perform gating control on the clock signal by the gating control signal when the gating permission signal indicates invalidity. The clock gating effective control circuit includes:
A set value circuit in which a cycle for generating the gating permission signal and an effective period of the gating control signal are set as set values;
A timer / counter circuit that counts a fixed count;
A control circuit for generating the gating permission signal based on a result of counting the period and the effective period specified by the set value circuit by the timer / counter circuit;
The semiconductor integrated circuit according to claim 1, further comprising: The set value of the set value circuit further includes phase information,
The semiconductor integrated circuit according to claim 2, wherein the control circuit controls a phase of the gating control signal based on the phase information. 4. The semiconductor integrated circuit according to claim 2, wherein the set value circuit includes a register or a memory for holding a set value, and at least a part of the set value is rewritable.

Images