JP2007052897A - Memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem in a dynamic RAM represented by SDRAM, that an area is increased by use of a huge counter due to need of many bits in order to obtain 200μs pause period by the counter, although securement of the pause period (mainly 200μs) is generally required as an initial starting sequence at the start of power supply called as power-on sequence. <P>SOLUTION: For the SDRAM, a refresh operation is absolutely necessary for every predetermined period, then the area is reduced by actualizing the pause period in such a manner that a refresh counter already mounted on a memory control circuit is utilized for counting the predetermined period. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a synchronous DRAM that performs data input / output in synchronization with a clock input.

  As the operating frequency of the microprocessor increases, a DRAM capable of high-speed access is required, and a synchronous DRAM has been developed as a response thereto. The synchronous DRAM includes a mode register, and by setting a burst length, a wrap type, and a CAS latency to the mode register, it is possible to cause the system to perform an optimum operation. Here, the burst length is the number of data input / output continuously, and one of 1, 2, 4, 8, and full page can be selected. The wrap type is a method of changing the internally generated column address during burst access (continuous input / output). The sequential method changes the column address continuously in the same bank, and the column address. Any one of the interleaving schemes for scrambling can be selected. In addition, the information of the SDRAM is stored with “Yes” or “No” charge on the capacitor, but this charge decreases with time. For this reason, in order to correctly store (hold) the data, it is necessary to periodically perform recharging such as refresh.

FIG. 2 shows a conventional memory control circuit for realizing the initial startup sequence.
In FIG. 2, 201 is an SDRAM, 202 is a control unit that controls the SDRAM 201, 203 is an instruction processing device that processes an instruction to the SDRAM 201, and 204 is one of the instructions to the instruction processing device 203. A refresh counter that counts the refresh interval for storing correctly, 205 is a power-on counter for counting the 200 μsec pause period, and 206 is a state machine that outputs a state signal to the control unit 202. .

  FIG. 3 is a timing chart showing an initial startup sequence of the synchronous DRAM. In FIG. 3, an NRAS (ROW Address Strobe) signal indicates a row address at the edge of CLK when the NRAS signal becomes “L”. The NRAS signal enables row access and precharge. An NCAS (Column Address Strobe) signal indicates a column address at the edge of CLK when the NCAS signal becomes “L”. Column access and precharge are enabled by the NCAS signal. An NWE (Write Enable) signal enables a write operation when the NWE signal becomes “L”. A command is issued to the device by these NRAS signal, NWE signal, and NCAS signal. When the NCAS signal is “H”, the NWE signal and the NRAS signal are “L”, a precharge command is indicated. The state of the synchronous DRAM immediately after power-on is indefinite. If proper initialization is not performed, the synchronous DRAM cannot be guaranteed to operate normally. Initialization of the internal circuit is performed after a power supply is stabilized, and after a pause period of 200 μSec, a precharge command or the like is issued to precharge all banks. After the precharge is completed, CBR (auto) refresh is issued 8 times. Thereafter, after the mode register setting is executed, the synchronous DRAM can be used.

Next, the operation of the conventional memory control circuit configured as described above will be described.
When executing the initial activation sequence shown in FIG. 3 for the SDRAM 201, the power-on counter 205 counts 200 μSec and activates the state machine 206. Next, in order to issue a precharge command, the instruction processing device 203 decodes the instruction and transmits the command content to the control unit 202. The control unit 202 generates a control signal from the contents of the command and issues the command to the SDRAM 201. Next, the refresh counter 204 counts and issues a refresh command after 25 μSec, for example. The instruction processing device 203 decodes the command and transmits the command content to the control unit 202. The control unit 202 generates a control signal from the contents of the command and issues the command to the SDRAM 201. This is repeated eight times, and then the instruction processing unit 203 decodes the instruction and transmits the command contents to the control unit 202 in order to set the mode register. The control unit 202 generates a control signal from the contents of the command and issues the command to the SDRAM 201. Thereafter, the SDRAM becomes usable.
Japanese Patent Laid-Open No. 2000-11643

  However, in the conventional configuration, since the time of 200 μSec is counted, there is a problem that the number of bits of the counter increases and the circuit area increases.

  The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a memory control device capable of realizing a reduction in circuit area.

  To achieve this object, a memory control circuit according to the invention of claim 1 uses a dynamic ram, a refresh counter for generating a refresh signal for the dynamic ram, and an access start using the refresh counter. By providing a power-on counter that generates timing, the number of bits of the counter that generates the access start timing can be reduced, and the circuit area can be reduced.

  According to a second aspect of the present invention, in the memory control circuit according to the first aspect, the power-on counter is activated only at the time of resetting. By counting up only when an error occurs, it is possible to avoid starting unnecessary counters.

  According to a third aspect of the present invention, there is provided a memory control circuit according to the second aspect, wherein the reset for starting up the power-on counter is performed only at the time of a hard reset. A wide range of systems can be supported.

  According to a fourth aspect of the present invention, there is provided a memory control circuit comprising a dynamic ram, a refresh counter for generating the refresh signal for the dynamic ram, and an instruction stock for stocking instructions for the dynamic ram. And a power-on counter that generates an access start timing according to the number of instruction stocks of the instruction stock. By using the instruction stock, generation of an access start timing can be realized without using a counter. The circuit area can be reduced.

  A memory control circuit according to a fifth aspect of the present invention is the memory control circuit according to the fourth aspect, wherein the power-on counter is activated only at the time of resetting. It is possible not to generate the start timing.

  According to a sixth aspect of the present invention, in the memory control circuit according to the fifth aspect, the reset for starting the power-on counter is performed only at the time of a hard reset. By not generating unnecessary access start timing, it is possible to support a wider range of systems.

  A memory control circuit according to a seventh aspect of the present invention is the memory control circuit according to the first aspect, wherein the power-on counter is not activated at the time of the test. Test costs can be reduced without spending time.

  The memory control circuit according to an eighth aspect of the present invention is the memory control circuit according to the seventh aspect, wherein the power-on counter is activated only at the time of resetting. It is possible not to generate the start timing.

  A memory control circuit according to a ninth aspect of the present invention is unnecessary in the memory control circuit according to the eighth aspect, characterized in that the power-on counter is activated only at the time of a hard reset. By not generating the access start timing, it is possible to deal with a wider range of systems.

  According to a tenth aspect of the present invention, there is provided a memory control circuit according to the fourth aspect, wherein the power-on counter is not activated during a test in the memory control circuit according to the fourth aspect. In the configuration for generating the access start timing, it is possible to reduce the test cost without taking extra time during the test.

  According to an eleventh aspect of the present invention, there is provided a memory control circuit according to the tenth aspect of the present invention, wherein the power-on counter is activated only at a reset time. In the configuration of using and generating the access start timing, it is possible not to generate an unnecessary access start timing.

  A memory control circuit according to a twelfth aspect of the present invention is the memory control circuit according to the eleventh aspect, wherein the power-on counter is activated only at the time of a hard reset. In the configuration in which the access start timing is generated using, it is possible to deal with a wider range of systems by not generating unnecessary access start timing.

  The memory control circuit of the present invention can reduce the circuit area by configuring a power-on counter using a refresh counter, and can perform a wider system by starting the power-on counter only at the time of a hard reset. It can correspond to. In addition, the test cost can be reduced by enabling the use of the SDRAM without using the power-on counter during the test.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a memory control circuit according to the first embodiment of the present invention.
In FIG. 1, reference numeral 101 denotes an SDRAM, 102 denotes a control unit that controls the SDRAM 101, 103 denotes an instruction processing device that processes an instruction for the SDRAM 101, and 104 denotes one of instructions to the instruction processing device 103. A refresh counter that counts refresh intervals for correctly storing data, 105 is a power-on counter that counts the pause period of 200 μSec, and 106 is a state machine that outputs a state signal to the control unit 102 , 107 is an instruction stock for holding an instruction to the instruction processing device 103, 108 is a selector for switching whether to secure a pause period of 200 μSec, and 109 notifies the memory control circuit of an operating mode. This is a mode signal.

Next, the operation of the memory control circuit configured as described above according to the first embodiment of the present invention will be described.
When the power is turned on for the SDRAM 101, the above-described initial startup sequence shown in FIG. 3 is executed. The refresh counter 104 issues a refresh command every 25 μSec. The power-on counter 105 counts the refresh command output from the refresh counter 104 and counts it up eight times to ensure the 200 μSec pause period, and then starts the state machine 106. Next, in order to issue a precharge command, the instruction processing device 103 decodes the instruction and transmits the command content to the control unit 102. The control unit 102 generates a control signal from the contents of the command and issues the command to the SDRAM 101.

  Next, the refresh counter 104 counts and issues a refresh timing. The command processing device 103 transmits the command content to the control unit 102. The control unit 102 generates a control signal from the contents of the command and issues the command to the SDRAM 101. Thereafter, the SDRAM 101 becomes usable.

  Here, the pause period in the initial activation sequence is not limited to 200 μSec, and the refresh timing is not limited to 25 μSec.

  As described above, by securing the 200 μSec pause period using the refresh timing, the power-on counter 105 can be realized with a small number of bits, and the area can be reduced.

  Further, by limiting the activation of the refresh counter 104 only to a hard reset at the time of power-on, a power-on counter when it is not necessary such as when the refresh command is output continuously eight times when it is unnecessary Can be prevented, that is, useless count-up can be avoided, and a wide range of systems can be supported without limiting the number of refresh instructions.

  Further, in the configuration in which the refresh instruction output from the refresh counter 104 is held in the instruction stock 107, the state machine 106 is activated by the number of instructions held in the instruction stock 107, thereby enabling 200 μSec. It is possible to secure a pause period.

  As a result, 200 μSec can be secured depending on the number of instruction stocks, so that it is not necessary to configure a counter and the circuit area can be further reduced.

  The selector 108 can switch whether to hold a pause period of 200 μSec by the mode signal 109.

This makes it possible to start the state machine 106 without counting by the power-on counter 105 when it is not necessary to ensure a pause period of 200 μSec as in the test mode, thereby reducing the test cost. Can be realized.
Here, the test mode is not limited, and other modes may be used.

  As described above, in the memory control circuit according to the present invention, the memory control circuit that realizes the initial start-up sequence of the SDRAM can reduce the circuit, support a wide range of systems, and reduce the test cost. This is useful in that it is possible to provide low-cost electronic devices.

1 is a block diagram of a memory control circuit according to a first embodiment of the present invention. Block diagram of a conventional memory control circuit Operation timing diagram of conventional memory control circuit

Explanation of symbols

101,201 SDRAM
102, 202 Control unit 103, 203 Instruction processing unit 104, 204 Refresh counter 105, 205 Power-on counter 106, 206 State machine 107 Instruction stock 108 Selector 109 Mode signal

Claims (12)

With dynamic ram,
A refresh counter for generating a refresh signal for the dynamic ram;
A power-on counter that generates an access start timing using the refresh counter, and
A memory control circuit. The memory control circuit according to claim 1.
The power-on counter is activated only at reset.
A memory control circuit. The memory control circuit according to claim 2.
The reset for starting the power-on counter is performed only at the time of a hard reset.
A memory control circuit. With dynamic ram,
A refresh counter for generating the refresh signal for the dynamic ram;
A power-on counter having an instruction stock for stocking instructions for the dynamic ram, and generating an access start timing according to the number of instruction stocks of the instruction stock,
A memory control circuit. The memory control circuit according to claim 4.
The power-on counter is activated only at reset.
A memory control circuit. The memory control circuit according to claim 5,
The reset for starting the power-on counter is performed only at the time of a hard reset.
A memory control circuit. The memory control circuit according to claim 1.
The power-on counter is not activated during testing,
A memory control circuit. The memory control circuit according to claim 7,
The power-on counter is activated only at reset.
A memory control circuit. The memory control circuit according to claim 8.
The power-on counter is activated only during a hard reset.
A memory control circuit. The memory control circuit according to claim 4.
The power-on counter is not activated during testing,
A memory control circuit. The memory control circuit according to claim 10,
The power-on counter is activated only at reset.
A memory control circuit. The memory control circuit according to claim 11,
The power-on counter is activated only during a hard reset.
A memory control circuit.

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