JP2007316670A - Liquid crystal display - Google Patents

Abstract

In a lateral electric field type liquid crystal display device in which at least a part of a signal line is covered with a common electrode through an interlayer insulating film, a short circuit between the signal line and the common electrode is reduced.
A display portion is partitioned by a scanning line and a signal line, and pixels are provided. However, contact holes 27 for connecting common wirings and common electrodes are not formed for each pixel, but are thinned out and arranged in a staggered manner. For example, a configuration in which the pixel line is provided every four pixels reduces the short circuit between the signal line and the common electrode.
[Selection] Figure 4

Description

  The present invention relates to a liquid crystal display device, and more particularly to a lateral electric field type liquid crystal display device in which at least part of a signal line is covered with a common electrode through an interlayer insulating film.

  As a switching element for driving and controlling a pixel electrode, a transmissive liquid crystal display device using a thin film transistor (TFT) or an MIM (Metal Insulator Metal) is widely used. In particular, a lateral electric field type (IPS) liquid crystal display device capable of realizing a wide viewing angle similar to that of a cathode ray tube is used as a monitor.

  26 to 28 show a configuration of one pixel portion of an active matrix substrate in a lateral electric field type liquid crystal display device using a TFT disclosed in Patent Document 1, FIG. 26 is a plan view, and FIG. FIG. 28 is a cross-sectional view taken along the line YY ′ of FIG. In the active matrix substrate of the lateral electric field type liquid crystal display device, a plurality of pixel electrodes and a common electrode are formed so as to face each other in a comb-like shape, and an electric field substantially parallel to the substrate is generated between the electrodes. Controls the array.

  As shown in FIG. 26, a scanning line 111 that supplies a scanning signal and a signal line 112 that supplies a display signal are orthogonal to each other, and a common wiring 113 that supplies a potential to the common electrode 122 is provided in parallel to the scanning line 111. ing. On the other hand, the common electrode 122 and the pixel electrode 121 are provided so as to face each other in a comb shape, and the TFT 114 is connected to the scanning line 111, the signal line 112, and the pixel electrode 121 at the intersection of the scanning line 111 and the signal line 112. Is provided.

  The gate electrode 123 of the TFT 114 is provided as a part of the scanning line 111, the drain electrode 125 is connected to the signal line 112, the source electrode 124 is connected to the pixel electrode 121 through the contact hole 126, and the common wiring 113 is connected to the contact hole 127. To the common electrode 122. Further, at least a part of the signal line 112 is disposed so as to be covered with the common electrode 122.

  As shown in FIG. 27, a gate electrode 123, a gate insulating film 131, and an island-shaped semiconductor layer 134 are provided on the transparent insulating substrate 120. Further, the semiconductor layer 134 (amorphous silicon (a-Si) layer 164, n + type amorphous silicon (n + type a-Si) layer 174) is covered, and the source electrode 124 and the drain electrode 125 are provided separately to form the TFT 114. Has been. Further, an interlayer insulating film (a protective film 132 and an organic insulating film 133) is provided to cover the TFT 114. In addition, as shown in FIG. 28, the pixel electrode 121 is a source electrode through a contact hole 126 formed in the organic insulating film 133 and a contact hole 127 formed in the organic insulating film 133 and the gate insulating film 131, respectively. 124, the common electrode 122 is connected to the common wiring 113.

  Next, a manufacturing process of the active matrix substrate having the above configuration will be described. First, a metal film made of a Cr—Mo alloy film is formed on a transparent insulating substrate 120 such as glass and patterned to form the gate electrode 123, the scanning line 111, and the common wiring 113. Next, the gate insulating film 131, the a-Si layer 164, and the n + -type a-Si layer 174 are sequentially formed and then patterned to form the semiconductor layer 134. Next, a metal film made of a Cr—Mo alloy film is formed and turned to form the source electrode 124, the drain electrode 125, and the signal line 112. Using these as a mask, the n + type a-Si layer 174 is etched. Remove to form a channel.

  Subsequently, a protective film 132 made of a silicon nitride film is formed and patterned. Next, after applying and patterning a photosensitive organic insulating film 133, the gate insulating film 131 is further patterned using this as a mask, and contact holes 126 and 127 are opened. Thereafter, a transparent conductive film made of an indium tin oxide film (ITO) is formed to cover the organic insulating film 133 and patterned to form the common electrode 122 and the pixel electrode 121. In this way, the common electrode 122 and the common wiring 113 and the pixel electrode 121 and the source electrode 124 are connected.

  As described above, the organic insulating film 133 having a low relative dielectric constant is used as a part of the interlayer insulating film when the common electrode 122 and the signal line 112 are partially overlapped in order to improve the aperture ratio. This is to reduce the capacitive coupling between the line and the common electrode and suppress crosstalk. In addition, the flatness of the active matrix substrate is improved, the variation in gap with the counter substrate is reduced, and the uniformity of luminance is improved.

  In the case where an organic insulating film is not used for the interlayer insulating film, the protective film 132 made of a silicon nitride film is formed thickly. At this time, the contact holes 126 and 127 are opened by one photolithography process.

WO 98/47044 (pages 8-18, FIGS. 1, 3, 4)

  However, in the lateral electric field type liquid crystal display device in which at least a part of the signal line as described above is covered with the common electrode through the interlayer insulating film, a pinhole is generated in the interlayer insulating film due to its structure. There is a problem in manufacturing yield that the signal line and the common electrode are short-circuited and vertical line defects are likely to occur.

  According to an experiment by the present inventor, in a signal line patterning process, a defective patterning of the metal film of the signal line occurs from the signal line 112 to the contact hole 127 due to foreign matters such as a photoresist, and the signal line passes through the contact hole 127. It was confirmed that 112 and the common electrode 122 were short-circuited. This phenomenon has been found to be particularly noticeable in high-definition panels with a narrow pixel pitch.

  Further, in the case where the interlayer insulating film is formed using only an inorganic film such as a silicon nitride film without using an organic insulating film, if the opening is performed using at least dry etching in the opening process of the contact holes 126 and 127, a photoresist is obtained. It was confirmed that the plasma was concentrated on the foreign matter and the defect portion of the metal, and as a result, the interlayer insulating film was etched into a pinhole shape, and the signal line 112 and the common electrode 122 were short-circuited through the pinhole.

  An object of the present invention is to provide a horizontal electric field type liquid crystal display device in which at least a part of a signal line is covered with a common electrode through an interlayer insulating film, and a vertical line defect caused by a short between the signal line and the common electrode. It is an object of the present invention to provide a liquid crystal display device capable of reducing and improving the manufacturing yield.

  In order to achieve the above object, a liquid crystal display device according to the present invention is formed on a substrate with a thin film transistor, a plurality of scanning lines and signal lines that are connected to the thin film transistor and intersect vertically and horizontally, and in the same layer as the scanning line. A common electrode connected to the common line through an interlayer insulating film formed on the thin film transistor, and formed on the thin film transistor so as to cover at least part of the signal line. In a lateral electric field type liquid crystal display device that generates an electric field substantially parallel to the substrate between the connected pixel electrodes, for the plurality of pixels defined by the plurality of scanning lines and signal lines, A contact hole for connecting the common wiring and the common electrode is formed at a ratio of one for a plurality of pixels, and the definition is QSXGA or more.

  Further, in this liquid crystal display device, when another pixel in which another contact hole is formed around the one pixel in which the contact hole is formed is viewed, the other pixel has at least one pixel in the vertical and horizontal directions. It is characterized by being arranged in a space.

  In the lateral electric field type liquid crystal display device in which at least a part of the signal line is covered with the common electrode through the interlayer insulating film by the configuration as described above, the contact for connecting the common line and the common electrode The probability that the signal line and the common electrode are short-circuited through the hole can be reduced, and the manufacturing yield can be improved.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view conceptually showing the structure of the TFT substrate in the lateral electric field type liquid crystal display device according to the first embodiment of the present invention. As shown in FIG. 1, a plurality of scanning lines 11 and signal lines 12 are provided orthogonally on the opposite substrate side surface of the TFT substrate 10, and a common wiring 13 is provided in parallel between adjacent scanning lines 11. It has been. TFTs 14 are formed at the intersections between the scanning lines 11 and the signal lines 12, and these are arranged in a matrix. A scanning line terminal 15 and a signal line terminal 16 are provided at the ends of the scanning line 11 and the signal line 12, respectively, and a driving signal from an external driving circuit is input thereto.

  The common wiring 13 is bound to give a common potential as a reference for AC driving of the liquid crystal, and a common wiring binding line 17 to which both ends of each common wiring 13 are respectively connected is a TFT substrate 10. One is provided on each side of the short side. A capacitance is formed between the common wiring 13 and the pixel electrode connected to the source electrode of the TFT 14. A common wiring terminal 18 is provided at an end of each common wiring binding wire 17.

  FIG. 2 is an enlarged plan view showing one pixel portion of the TFT substrate of FIG. 1, and FIG. 3 is a cross-sectional view taken along the lines Aa, Bb, and Cc of FIG. As shown in FIG. 2, pixel electrodes 21 and common electrodes 22 formed in a comb shape are alternately arranged at the intersection of the scanning line 11 and the signal line 12 formed on the TFT substrate. In addition, an electric field substantially parallel to the TFT substrate 10 is generated to control the alignment of liquid crystal molecules. Further, the pixel electrode 21 and the common electrode 22 are provided on an interlayer insulating film made of a passivation film 32 and an organic insulating film 33 formed on the TFT 14 as shown in FIG.

  In this embodiment, the TFT 14 is an example of an inverted staggered thin film transistor. A gate electrode 23 of the TFT 14 is formed as a part of the scanning line 11, and a pixel formed in an interlayer insulating film on the source electrode 24. The pixel electrode 21 is connected through the electrode contact hole 26, and the common electrode 22 is connected to the common wiring 13 through the common electrode contact hole 27 formed in the interlayer insulating film and the gate insulating film 31. A signal line 12 is connected to the drain electrode 25. A scanning signal is input to the TFT 14 through the scanning line 11 and the gate electrode 23, and a display signal is input through the signal line 12 and the drain electrode 25, and charge is written to the pixel electrode 21. In addition, a storage capacitor is formed between the common wiring 13 and the storage capacitor electrode 35.

  FIG. 4 is a schematic plan view showing the arrangement of the contact holes 27 for the common electrode. As shown in FIG. 4, the contact holes 27 are not formed in all the pixels, but are thinned out in a staggered manner. Here, an example in which the number of pixels is thinned to ¼ is shown. Needless to say, the pixel electrode contact hole 26 is provided in every pixel.

  Next, a manufacturing method of the TFT substrate of the first embodiment will be described. 5, 7, 9, 11, 13, and 2 are plan views showing manufacturing steps of one pixel portion, and FIGS. 6, 8, 10, 12, 14, and 3 are 5, FIG. 7, FIG. 9, FIG. 11, FIG. 13 and FIG. 2, respectively, the Aa line ((a) diagram), the Bb line ((b) diagram), and the Cc line ((c) diagram). FIG. Here, the cross-sectional portion along the Aa line indicates a TFT portion, a contact hole portion for a pixel electrode, and a storage capacitor portion, the cross-sectional portion along the BB line indicates a pixel portion, and the cross-section along the Cc line. The part indicates a signal line part, a contact hole part for a common electrode, and a storage capacitor part.

  First, as shown in FIGS. 5 and 6, a conductive layer made of Cr, Mo, a Cr / Al laminated film, a Mo / Al laminated film, or the like is formed on a transparent insulating substrate 20 such as a glass substrate by sputtering. A film having a thickness of about 100 to 300 nm is formed, and a scanning line 11 that also serves as the gate electrode 23, a common wiring 13, a scanning line terminal portion (not shown), and a common wiring terminal portion (not shown) are formed by a photolithography process. .

  Next, as shown in FIGS. 7 and 8, the gate insulating film 31 made of a silicon nitride film is formed with a thickness of about 300 to 500 nm by plasma CVD, and further amorphous silicon (a-Si) is about 150 to 300 nm. Amorphous silicon doped with phosphorus (n + type a-Si) is sequentially formed with a film thickness of about 30 to 50 nm, and a semiconductor layer 34 serving as an active layer of the TFT 14 is formed by a photolithography process. The reason why the breakdown voltage improving semiconductor layer 64 is formed at the intersection of the scanning line 11, the common wiring 13 and the signal line is to increase the dielectric strength of both.

  Next, as shown in FIGS. 9 and 10, a conductive layer made of Cr, Mo, Cr / Al / Cr laminated film, Mo / Al / Mo laminated film, etc. is formed by sputtering to a thickness of about 100 to 400 nm. A source electrode 24, a drain electrode 25, a storage capacitor electrode 35, a signal line 12, and a signal line terminal portion (not shown) are formed by photolithography, and then the source and drain electrodes 24, 25 are used as a mask. Then, the n + type a-Si on the semiconductor layer 34 is removed by etching to form a channel.

  Thereafter, a passivation film 32 made of an inorganic film such as a silicon nitride film is formed to a thickness of about 100 to 300 nm by plasma CVD.

  Next, as shown in FIGS. 11 and 12, a positive photosensitive novolac resist is used to form an organic insulating film 33 having a thickness of about 1.5 to 3.5 μm, and an opening is formed in the contact hole forming portion. 66, 67 are formed.

  After that, as shown in FIGS. 13 and 14, the passivation film 32 is etched by a photolithography process, and the pixel electrode contact hole 26 for exposing the source electrode 24 to the portion corresponding to the openings 66 and 67, and the signal line A contact hole (not shown) for exposing the terminal portion is formed. At the same time, the passivation film 32 and the gate insulating film 31 are etched to expose a common electrode contact hole 27 for exposing the common wiring 13, and a contact hole (not shown) for exposing the scanning line terminal portion and the common wiring terminal portion. Then, contact holes (not shown) for common wiring bundling lines that expose end portions of the respective common wirings 13 are formed.

  Next, as shown in FIGS. 2 and 3, a transparent conductive film made of ITO or the like is formed on the organic insulating film 33 by sputtering, and the pixel electrode 21, the common electrode 22, the scanning line terminal portion, the signal are formed by a photolithography process. A line terminal part, a connection electrode (not shown) on the common wiring terminal part, and a common wiring binding line (not shown) are formed. At this time, as shown in FIG. 3B, one of the common electrodes 22 is positioned on the organic insulating film 33 corresponding to the signal line 12, and as shown in FIG. The pixel electrode 21 is formed so that one of the pixel electrodes 21 is positioned on the organic insulating film 33 corresponding to the capacitor electrode 35. Accordingly, the pixel electrode 21 connected to the source electrode 24 via the pixel electrode contact hole 26 and the common electrode 22 connected to the common wiring 13 via the common electrode contact hole 27 are also scanned. Through the contact hole for the line, the signal line, the common wiring terminal part, the connection electrode connected to the scanning line terminal part, the signal line terminal part, the common wiring terminal part is connected via the contact hole for the common wiring binding line, A common wire binding line connected to the end of each common wire 13 is formed. (The structure of the terminal portion will be described later.) Next, the structure of the terminal portion of the TFT substrate of the first embodiment will be described. 15 is a plan view of a terminal portion around the substrate. FIG. 16 is a cross-sectional view taken along the line D-d in FIG. 15 and shows a scanning line terminal and a common wiring terminal. FIG. 17 is a line E-e in FIG. A signal line terminal is shown in a sectional view along the line. The scanning line terminal and the common wiring terminal are connected to the terminal part metal film 41 formed of the same metal film as the scanning line, the connection electrode 42 formed of the same transparent conductive film as the common electrode, and the signal line terminal is connected to the signal line. A connection electrode 82 formed of the same transparent conductive film as the common electrode is formed on the terminal metal film 81 formed of the same metal film, and the terminal contact holes formed in the gate insulating film, the passivation film, and the passivation film, respectively. 43 and 83 are connected. Thus, no organic insulating film is formed on each terminal portion.

  Each common wiring 13 is connected to the common wiring binding line 17 through a contact hole 44 for the common wiring binding line. Although the cross-sectional structure of the contact hole 44 is not shown, it has the same structure as FIG.

  Next, a method for manufacturing a liquid crystal panel in which liquid crystal is sandwiched between the TFT substrate and the counter substrate according to the first embodiment will be briefly described. FIG. 18 is a cross-sectional view of one pixel portion of the liquid crystal panel. After forming an alignment film 51 made of a polyimide-based alignment agent with a thickness of 30 to 60 nm on the TFT substrate 10 described above and performing an alignment treatment, a sealing material (not shown) made of an epoxy-based resin adhesive is applied to the TFT substrate 10. It is formed along the periphery.

  On the other hand, a negative electrode is formed on a transparent insulating substrate 30 such as a glass substrate in which a transparent conductive layer 56 such as ITO having a thickness of about 80 to 150 nm is formed on the surface opposite to the surface on which the color filter is formed in advance. The black matrix 52 is formed using a type photosensitive acrylic pigment dispersion resist or a carbon resist with a film thickness of about 1 to 3 μm, an optical density (OD value) of 3 or more, and a sheet resistance value of 1 × 10 10 Ω / □ or more. . Next, a red color filter 53R having a film thickness of about 1.0 to 1.5 μm is formed using a negative photosensitive acrylic pigment dispersion resist. Similarly, the color layers of the blue color filter 53B and the green color filter 53G are formed. Next, an overcoat film 54 which is an organic insulating film having a thickness of about 2.0 to 3.5 μm is formed using a novolac resist. Further, an alignment film 51 having a film thickness of 30 to 6 nm made of a polyimide-based alignment agent is formed thereon, and an alignment process is performed to obtain the counter substrate 50.

  Thereafter, the counter substrate 50 is overlaid on the TFT substrate 10 via a sealing material and an in-plane spacer (not shown), and a liquid crystal 55 made of a fluorine compound is injected between the two substrates from an injection port (not shown). After that, the inlet is sealed with a sealing material (not shown) made of a UV curable acrylate resin to obtain a panel with a predetermined gap.

  Finally, a polarizing plate 57 made of an iodine polarizing film is attached to the surface of the TFT substrate 10 opposite to the element surface and the surface of the counter substrate 50 opposite to the color filter. Thereby, a wide viewing angle and high aperture ratio liquid crystal panel using the above-described TFT substrate 10 is manufactured.

  As described above, in the lateral electric field type liquid crystal display device in which at least a part of the signal line is covered with the common electrode through the interlayer insulating film, the contact hole for connecting the common line and the common electrode is provided for each pixel. Since it is formed by thinning without forming, even if patterning failure occurs due to foreign matters etc. in the signal line forming step, the probability that the signal line and the common electrode are short-circuited through this contact hole can be reduced, Manufacturing yield can be improved. In particular, this effect is remarkable in a large high-definition panel of QSXGA class with a small pixel area. Furthermore, since the contact holes described above are arranged in a staggered manner, display uniformity can be ensured.

(Second Embodiment)
The second embodiment of the present invention relates to the case where the interlayer insulating film on the TFT is formed of only an inorganic film. The configuration of the TFT substrate is the same as that of the first embodiment of FIG.

  19 is an enlarged plan view showing one pixel portion of the TFT substrate of FIG. 1, and FIG. 20 is a cross-sectional view taken along lines Aa, Bb, and Cc of FIG. As shown in FIG. 19, pixel electrodes 21 and common electrodes 22 formed in a comb-like shape are alternately arranged at the intersection of the scanning lines 11 and the signal lines 12 formed on the TFT substrate. In addition, an electric field substantially parallel to the TFT substrate 10 is generated to control the alignment of liquid crystal molecules. Further, as shown in FIG. 20, the pixel electrode 21 and the common electrode 22 are provided on an interlayer insulating film composed of two layers of passivation films 61 and 62 formed on the TFT 14.

  Just as in the first embodiment, in this embodiment, the TFT 14 is an example of an inverted staggered thin film transistor, the gate electrode 23 of the TFT 14 is formed as a part of the scanning line 11, and the source electrode 24. The pixel electrode 21 is connected to the common wiring 13 through a contact hole 27 for the common electrode formed in the interlayer insulating film and the gate insulating film 31. The common electrode 22 is connected to each other, and the signal line 12 is connected to the drain electrode 25. In the present embodiment, the contact hole 27 for the common electrode is provided in all the pixels.

  Next, a manufacturing method of the TFT substrate of the second embodiment will be described. Since the process of forming the TFT 14 is exactly the same as that in the first embodiment (FIGS. 5 to 10), description thereof is omitted. 21, FIG. 23, and FIG. 19 are plan views showing manufacturing steps after the passivation film forming step for one pixel portion, and FIGS. 22, 24, and 20 are A-a in FIG. 21, FIG. 23, and FIG. It is process sectional drawing in alignment with line ((a) figure), BB line ((b) figure), and CC line ((c) figure). Here, the cross-sectional portion along the line Aa indicates the TFT portion, the contact hole portion for the pixel electrode, and the storage capacitor portion, the cross-sectional portion along the line BB indicates the pixel portion, and the cross-section along the line Cc. The part indicates a signal line part, a contact hole part for a common electrode, and a storage capacitor part.

  As shown in FIGS. 21 and 22, a first passivation film 61 made of an inorganic film such as a silicon nitride film is formed with a film thickness of about 300 to 500 nm by plasma CVD, and the first passivation is performed by a photolithography process. The film 61 is etched to form a pixel electrode opening 86 exposing the source electrode 24 and a contact hole (not shown) exposing the signal line terminal portion. At the same time, the first passivation film 61 and the gate insulating film 31 are etched to expose a common electrode opening 87 for exposing the common wiring 13 and a contact hole for exposing the scanning line terminal portion and the common wiring terminal portion (not shown). ) And a contact hole (not shown) for the common wiring bundling line that exposes the end portion of each common wiring 13. The contact hole etching at this time is performed by dry etching or a combination of wet etching and dry etching, and includes at least dry etching.

  Next, as shown in FIGS. 23 and 24, a second passivation film 62 made of an inorganic film such as a silicon nitride film is formed again by plasma CVD to a film thickness of about 300 to 500 nm, and then by a photolithography process. The second passivation film 62 is etched using the same mask as in the above process, and the pixel electrode contact hole 96 for exposing the source electrode 24 and the contact hole for exposing the signal line terminal portion (not shown). The first passivation film 61 and the gate insulating film 31 are etched to expose a common electrode contact hole 97, and a scanning line terminal portion and a contact hole (not shown) that expose the common wiring terminal portion. ) And a contact hole (not shown) for the common wire binding line that exposes the end of each common wire 13 To Re opening. At this time, the exposure amount is adjusted, and an opening is provided inside the contact hole in the above process. Further, the contact hole may be etched by either wet etching or dry etching, or a combination of both.

  Next, as shown in FIGS. 19 and 20, a transparent conductive film made of ITO or the like is formed on the organic insulating film 33 by sputtering in the same manner as in the first embodiment, and a pixel is formed by a photolithography process. The electrode 21, the common electrode 22, the scanning line terminal portion, the signal line terminal portion, the connection electrode (not shown) on the common wiring terminal portion, and the common wiring binding line (not shown) are formed. At this time, one of the common electrodes 22 is positioned on the first and second passivation films 61 and 62 corresponding to the signal line 12, and on the organic insulating film 33 corresponding to the storage capacitor electrode 35. It is formed so that one of the pixel electrodes 21 is located. As a result, the pixel electrode 21 connected to the source electrode 24 via the pixel electrode contact hole 96 and the common electrode 22 connected to the common wiring 13 via the common electrode contact hole 97 are also scanned. Through the contact hole for the line, the signal line, the common wiring terminal part, the connection electrode connected to the scanning line terminal part, the signal line terminal part, the common wiring terminal part is connected via the contact hole for the common wiring binding line, A common wire binding line connected to the end of each common wire 13 is formed. Here, the structure of each terminal portion is exactly the same as that of the first embodiment (FIGS. 16 and 17) except that the passivation film has two layers.

  The subsequent cell process is performed in exactly the same manner as in the first embodiment, and a liquid crystal panel using the TFT substrate of this embodiment is manufactured.

  According to the experiment by the present inventor, when the passivation film is a single layer and the contact hole opening process is performed once, the signal line and the common electrode are frequently short-circuited. The cause was found to be that pinholes were formed in the interlayer insulating film due to dry etching when the contact holes were opened. This is presumed to occur because plasma concentrates on the foreign matter or defect portion of the photoresist in the contact hole opening process. By forming the passivation film into two layers and dividing the contact hole opening process into two times, a pinhole is generated in the first passivation film 61. Even if a pinhole is generated in the second passivation film 62, The probability of occurring at the same location is very low. That is, when dry etching is used when the second passivation film 62 is opened, pinholes are similarly formed, but the time for etching the second passivation film 62 is naturally the same as that of the first passivation film 61 and the second passivation film 62. Since the time required for etching the entire thickness of the passivation film 62 is shorter than that of the second passivation film 62, pinholes are not formed through the entire thickness of the passivation film. Of course, when the second passivation film 62 is wet-etched, no pinhole is generated in the second passivation film 62, and the pinhole is formed only for the thickness of the first passivation film. Therefore, in the horizontal electric field type liquid crystal display device in which at least a part of the signal line is covered with the common electrode through the interlayer insulating film, the manufacturing method as in this embodiment is used to share the signal line. It is possible to significantly reduce the short circuit of the electrode.

  In this embodiment, since the opening of the first passivation film 61 and the opening of the second passivation film 62 are performed using the same mask, the photolithography process is increased by one process, but there is an advantage that the number of masks is not increased. . Further, since the opening of the second passivation film 62 is provided inside the opening of the first passivation film 61, the shape of the contact hole is kept good even if the opening of the second passivation film 62 is performed by wet etching. be able to. That is, when the opening of the second passivation film 62 is provided outside the opening of the first passivation film 61, particularly when a film different from the silicon nitride film, such as a silicon oxide film, is used for the gate insulating film. Then, side etching occurs in the silicon oxide film, and the shape of the contact hole cannot be maintained in a staircase shape, causing a step in the transparent conductive film formed thereon. By providing the opening of the second passivation film 62 inside the opening of the first passivation film 61, the opening side wall of the first passivation film 61 is protected by the second passivation film 62. Problems can be prevented.

(Third embodiment)
As in the second embodiment, the third embodiment of the present invention relates to the case where the interlayer insulating film on the TFT is formed of only an inorganic film. In this embodiment, the inorganic film of the interlayer insulating film is formed as a single layer, except that it is different from the second embodiment, and the other configuration is exactly the same as that of the second embodiment.

  19 is an enlarged plan view showing the same pixel portion of the TFT substrate of FIG. 1 (same as the second embodiment), and FIG. 25 is an Aa line, BB line, C- It is sectional drawing which follows c line. As shown in FIG. 25, the pixel electrode 21 and the common electrode 22 of this TFT substrate are provided on an interlayer insulating film made of a single-layer passivation film 32 formed on the TFT 14.

  Next, a manufacturing method of the TFT substrate of the third embodiment will be described. The only difference from the second embodiment is the passivation film formation and contact hole opening process. That is, the passivation film 32 made of an inorganic film such as a silicon nitride film is formed by plasma CVD to a thickness of about 700 to 1000 nm, and the passivation film 32 is etched by a photolithography process to expose the source electrode 24. A contact hole 96 for the pixel electrode and a contact hole (not shown) for exposing the signal line terminal portion, a contact hole 97 for the common electrode for exposing the common wiring 13 by etching the passivation film 32 and the gate insulating film 31. Then, a contact hole (not shown) exposing the scanning line terminal portion and the common wiring terminal portion and a contact hole (not shown) for the common wiring binding line exposing the end portion of each common wiring 13 are opened. Etching of the contact hole at this time is performed by a combination of wet etching and dry etching, and the thickness of the passivation film 32 is thicker than the film thickness etched by dry etching (more precisely, the film thickness corresponding to the time for dry etching). It is a feature.

  As described above, even when a pinhole is formed in the passivation film for the same reason as described above by forming the passivation film thicker than the film thickness corresponding to the time for etching by dry etching when the contact hole is opened, Does not penetrate the entire film thickness, and therefore it is possible to significantly reduce the short circuit between the signal line and the common electrode.

  In the first embodiment, an example in which an organic insulating film such as a photosensitive novolak resist is used has been described. Of course, a polyimide resin or an acrylic resin may be used, or a silicon oxide film or a silicon nitride film may be used. An inorganic resin material such as Further, it may be non-photosensitive and non-photosensitive. In this case, an etching process and a resist stripping process are required after development, as in a normal photolithography process. In addition, although the example in which the organic insulating film forming process and the passivation film opening process are separate photolithography processes has been described, the opening may be performed in the same photolithography process.

  In the above-described embodiment, a liquid crystal display device having an inverted staggered channel etch type TFT has been described. However, a channel protection type or a forward stagger type TFT may be used, and not only a staggered type TFT but also a coplanar type TFT. It goes without saying that is also applicable. Further, it can be applied not only to a-Si TFTs but also to polysilicon (p-Si) TFTs. Further, the switching element may be a MIM.

  As described above, according to the present invention, in a horizontal electric field type liquid crystal display device in which at least a part of a signal line is covered with a common electrode through an interlayer insulating film, display performance is not deteriorated. It is possible to remarkably reduce the short circuit between the signal line and the common electrode and improve the manufacturing yield.

1 is a plan view conceptually showing the structure of a TFT substrate in a lateral electric field type liquid crystal display device according to a first embodiment of the present invention. It is a top view which expands and shows 1 pixel part of the TFT substrate of FIG. It is sectional drawing which follows the Aa line of FIG. 2, Bb line, and Cc line. It is a schematic diagram which shows arrangement | positioning of the contact hole for common electrodes. FIG. 4 is a process plan view (first process) of one pixel portion for explaining an example of a method for manufacturing a liquid crystal panel using the TFT substrate of FIG. 1. It is process sectional drawing which follows the Aa line of FIG. 5, Bb line, and Cc line. It is a process top view (2nd process) of 1 pixel part explaining an example of the manufacturing method of the liquid crystal panel using the TFT substrate of FIG. It is process sectional drawing which follows the Aa line of FIG. 7, Bb line, and Cc line. It is a process top view (3rd process) of 1 pixel part explaining an example of the manufacturing method of the liquid crystal panel using the TFT substrate of FIG. It is process sectional drawing which follows the Aa line of FIG. 9, Bb line, and Cc line. It is a process top view (4th process) of 1 pixel part explaining an example of the manufacturing method of the liquid crystal panel using the TFT substrate of FIG. It is process sectional drawing which follows the Aa line of FIG. 11, Bb line, and Cc line. It is a process top view (5th process) of 1 pixel part explaining an example of the manufacturing method of the liquid crystal panel using the TFT substrate of FIG. It is process sectional drawing which follows the Aa line of FIG. 13, Bb line, and Cc line. It is a top view of the terminal part around the TFT substrate of FIG. It is sectional drawing which follows the DD line | wire of FIG. It is sectional drawing which follows the EE line | wire of FIG. It is sectional drawing of the 1 pixel part of the liquid crystal panel using the TFT substrate of FIG. It is a top view which expands and shows 1 pixel part of the TFT substrate in the horizontal electric field type liquid crystal display device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which follows the Aa line of FIG. 19, Bb line, and Cc line. It is a process top view (4th process) of 1 pixel part of a TFT substrate of a 2nd embodiment of the present invention. It is process sectional drawing which follows the Aa line of FIG. 21, Bb line, and Cc line. It is a process top view (5th process) of 1 pixel part of the TFT substrate of the 2nd Embodiment of this invention. FIG. 24 is a process cross-sectional view taken along the lines Aa, Bb, and Cc in FIG. 23. The Aa line, BB line, C of the top view (the same as FIG. 19) which expands and shows 1 pixel part of the TFT substrate in the horizontal electric field type liquid crystal display device which concerns on the 3rd Embodiment of this invention. It is sectional drawing which follows the -c line. It is a top view which expands and shows 1 pixel part of the TFT substrate in the conventional horizontal electric field type | mold liquid crystal display device. It is sectional drawing which follows the X-X 'line | wire of FIG. It is sectional drawing which follows the Y-Y 'line | wire of FIG.

Explanation of symbols

10 TFT substrate 20, 30, 120 Transparent conductive substrate 11, 111 Scan line 12, 112 Signal line 13, 113 Common wiring 14, 114 TFT
DESCRIPTION OF SYMBOLS 15 Scan line terminal 16 Signal line terminal 17 Common wiring bundling line 18 Common wiring terminal 21, 71, 121 Pixel electrode 22, 72, 122 Common electrode 23, 123 Gate electrode 24, 124 Source electrode 25, 125 Drain electrode 26, 27, 44, 96, 97, 126, 127 Contact hole 31, 131 Gate insulating film 32 Passivation film 33, 133 Organic insulating film 34, 134 Semiconductor layer 35 Storage capacitor electrode 41, 81 Terminal metal film 42, 82 Connection electrode 43, 83 Terminal part contact hole 50 Counter substrate 51 Alignment film 52 Black matrix 53R, 53G, 53B Color filter 54 Overcoat film 55 Liquid crystal 56 Transparent conductive layer 57 Polarizing plate 61 First passivation film 62 Second passivation film 64 Semiconductor for improving withstand voltage Layer 66, 67, 86, 87 Opening 132 Protective film 164 Amorphous silicon (a-Si) layer 174 n + type amorphous silicon (n + type a-Si) layer

Claims (2)

A thin film transistor on a substrate, a plurality of scanning lines and signal lines connected to the thin film transistor and intersecting in the vertical and horizontal directions, and a common wiring formed in the same layer as the scanning line, and an interlayer insulation formed on the thin film transistor Between the common electrode connected to the common wiring and covering at least a part of the signal line through a film, and a pixel electrode connected to the thin film transistor, and substantially parallel to the substrate In a horizontal electric field type liquid crystal display device that generates an electric field, a contact hole that connects the common wiring and the common electrode is provided in a plurality of pixels for a plurality of pixels defined by the plurality of scanning lines and signal lines. A liquid crystal display device formed by one ratio and having a definition of QSXGA or higher. When another pixel in which another contact hole is formed is viewed around one pixel in which the contact hole is formed, the other pixel is arranged with at least one pixel left and right in the vertical and horizontal directions. The liquid crystal display device according to claim 1.

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