JP2007310831A - Autonomous adjusting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an autonomous adjusting device 10 autonomously adjusting the configuration of a target circuit 20 even after shipping a product. <P>SOLUTION: The autonomous adjusting device 10 for autonomously adjusting the target circuit 20 is provided with a nonvolatile memory 4 holding a parameter set composed of a combination of a plurality of parameters for setting operation performance of the target circuit 20, and a parameter control part 1 for shifting from a normal mode in which the target circuit 20 normally operates to an adjustment mode for adjusting the target circuit 20 to set the parameter set held in the nonvolatile memory 4 in the target circuit 20 during a standby state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to post-fabrication technology, and more particularly, to an autonomous adjustment device that autonomously adjusts a target circuit.

  As semiconductor integrated circuits (ICs) are miniaturized, performance variations due to process variations have become prominent. As a countermeasure, post-fabrication technology considering process variation is being used. The post-fabrication technology is to reduce power consumption by adjusting a delay adjustment circuit to improve the maximum operating frequency or adjusting a power supply voltage or a threshold voltage after manufacturing an IC, for example. (For example, refer to Patent Document 1).

  However, if the above-described operation performance adjustment is performed at the system-on-chip (SoC) level, the number of parameters to be adjusted and their combinations are enormous, and it is difficult to construct a unified algorithm. . In other words, since various parameters are correlated with each other, it is extremely difficult to derive a logical algorithm.

  Therefore, a genetic algorithm is often used. A `` genetic algorithm '' is a method that imitates the evolution process of a living organism and repeats selection, crossover, and mutation based on the past optimal solution to obtain a better solution. The algorithm to pursue.

There are various ways of applying the genetic algorithm, but there is no general method in any of them, and an enormous number of trial and error must be repeated. However, it does not necessarily converge within a limited adjustment time before product shipment, and even if the shipment acceptance standard is reached, it is often the case that the individual has not reached the optimum optimum value.
International Publication No. WO 98/13742 Pamphlet

  The present invention provides an autonomous adjustment device capable of autonomously adjusting the configuration of a target circuit even after product shipment.

  According to one aspect of the present invention, an autonomous adjustment device that autonomously adjusts a target circuit, the nonvolatile memory holding a parameter set including a combination of a plurality of parameters that set the operation performance of the target circuit, and a standby A parameter control unit that shifts from a normal mode in which the target circuit performs a normal operation to an adjustment mode in which an adjustment operation is performed on the target circuit in a state, and sets a parameter set held in a nonvolatile memory in the target circuit An autonomous adjustment device is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the autonomous adjustment apparatus which can adjust the structure of a target circuit autonomously even after product shipment can be provided.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings in the following embodiments, the same or similar parts are denoted by the same or similar reference numerals.

(Autonomous adjustment device)
As shown in FIG. 1, the semiconductor integrated circuit according to the embodiment of the present invention includes an autonomous adjustment device 10, a target circuit 20 to be subjected to autonomous adjustment, and a control device 30 that controls the autonomous adjustment device 10. The target circuit 20 is, for example, an image processing circuit or a communication processing circuit, and is configured by a digital circuit, an analog circuit, or a combination thereof.

  When it is determined that the device on which the semiconductor integrated circuit shown in FIG. 1 is mounted is in the standby state, the control device 30 requests a signal (hereinafter referred to as “adjustment”) for shifting to the adjustment mode for performing the adjustment operation of the target circuit 20. A mode request signal "). When there is no input operation from the user for a certain period of time, when the operating state of the target circuit 20 is measured and determined to be a non-operating state, the device on which the semiconductor integrated circuit of FIG. 1 is mounted is connected to an AC adapter (not shown). In such a case, it is determined to be in a standby state.

  In addition, the control device 30 is triggered by an input operation from the user or the like as a trigger to request a signal for returning to the normal mode in which the target circuit 20 is normally operated without performing the adjustment operation of the target circuit 20 (hereinafter referred to as “normal mode request”). Signal "). When a RISC processor is used as the control device 30, the target circuit 20 can return to normal operation in a sufficiently short period by generating a normal mode request signal using the interrupt function of the RISC processor. As a result, the autonomous adjustment device 10 operates in one of the normal mode M1 and the adjustment mode M2, as shown in FIG.

The autonomous adjustment device 10 supplies a parameter set including a combination of parameters such as a power supply voltage, a delay amount, and a threshold voltage to the target circuit 20 and adjusts the operation performance in the target circuit 20. That is, the target circuit 20 is configured such that the power supply voltage, the delay amount, the threshold voltage, and the like can be adjusted for each circuit block by the parameter set supplied from the autonomous adjustment device 10. As an example, the power supply voltage or threshold value of the target circuit 20 is changed for each circuit block using a parameter set, and the power consumption is measured using an evaluation function, so that an adjustment mode for reducing power consumption is executed. The A specific configuration example of the target circuit 20 will be described later.
The autonomous adjustment device 10 includes a mode register 2 that holds information indicating whether the current operation mode is a normal mode or an adjustment mode, a parameter generator 3 that generates a parameter set, and a nonvolatile memory 4 that stores the parameter set. A multiplexer (MUX) 5 that selects one of the outputs of the parameter generator 3 and the nonvolatile memory 4, a parameter register unit 6 that holds the parameter set selected by the MUX 5, and a target circuit 20 in which the parameter set is set. A measurement circuit 9 for measuring the operation characteristics of the automatic adjustment device 10 and a parameter control unit 1 for controlling each circuit in the autonomous adjustment device 10.

  The parameter register unit 6 includes a plurality of parameter registers 6_1 to 6_n that hold the parameters P1, P2,. Immediately after the operation is started (reset), the parameter set is supplied from the nonvolatile memory 4 to the parameter register unit 6, but when the mode is shifted to the adjustment mode, the parameter register unit 6 takes in the parameter set generated by the parameter generator 3.

  The measurement circuit 9 has a pass determination circuit 7 that determines whether the operation performance such as the operation frequency and power consumption of the target circuit 20 satisfies the specifications, and the operation performance of the target circuit 20 is superior to the operation characteristics measured in the past. And a performance evaluation circuit 8 for evaluating whether the Specifically, the pass determination circuit 7 determines whether or not the target circuit 20 satisfies the specifications as a product when the parameters are changed. If the product does not meet the specifications, the parameter set is rejected as inappropriate even if the evaluation value is high. For example, when the purpose of optimization is to achieve low power consumption, parameters (power supply voltage value, threshold voltage, etc.) are used to improve power consumption as much as possible. The lowest operating frequency.

  The performance evaluation circuit 8 creates an evaluation function. For example, if the operating frequency of the circuit is measured, the higher the operating frequency, the higher the evaluation value is determined. If the power consumption is measured, the lower the power consumption value, the higher the evaluation value is determined. To do. As described above, in the case where the minimum operating frequency is set as the specification to be satisfied, a configuration is considered in which the minimum operating frequency satisfies the pass condition and achieves low power consumption.

  The parameter generator 3 generates parameter set candidates for adjusting the target circuit 20. For example, a random genetic algorithm can be used as the parameter set generation algorithm of the parameter generator 3, but other algorithms may be used. The parameter generator 3 is supplied with the outputs of the pass determination circuit 7 and the performance evaluation circuit 8 when using the parameter under trial, and is used to generate the next parameter candidate.

  Specifically, in the adjustment mode, the parameter control unit 1 satisfies the specification, and the operation performance of the target circuit 20 is superior to the operation characteristics measured in the past. The nonvolatile memory 4 is updated.

  The nonvolatile memory 4 stores one set of parameters. At reset, the parameter set stored in the nonvolatile memory 4 is loaded into the parameter register and used for adjustment of the target circuit 20. In addition, when a parameter set determined to have high performance is found in the adjustment mode, the parameter control unit 1 stores the parameter set stored in the nonvolatile memory 4 using the parameter set held in the parameter register unit 6. The content of the parameter set is updated.

  The parameter control unit 1 outputs a write permission signal for the parameter register unit 6, an input selection signal for the parameter register unit 6, a control signal for the parameter generator 3, a write permission signal for the nonvolatile memory 4, an update signal for the mode register 2, and the like. . The parameter control unit 1 receives an adjustment mode request signal and a normal mode request signal from the control device 30.

(Autonomous adjustment processing flow)
Next, an autonomous adjustment processing flow of the autonomous adjustment device 10 according to the embodiment of the present invention will be described with reference to the flowchart shown in FIG.

  In step S101, when the autonomous adjustment device 10 shifts to the adjustment mode, the mode register 2 holds information indicating that the current operation mode is the adjustment mode. Immediately after the start of the adjustment mode, the parameter generator 3 refers to the parameter set held in the nonvolatile memory 4 and generates a new parameter set. Further, the parameter control unit 1 switches the MUX 5 to the parameter generator 3 side, so that the parameter set generated by the parameter generator 3 is set in the target circuit 20 via the parameter register unit 6. Test data covering each circuit block of the target circuit 20 is preset in the target circuit 20, and the target circuit 20 operates using the test data.

  In step S <b> 102, the measurement circuit 9 measures the operation performance of the target circuit 20. That is, the pass determination circuit 7 and the performance evaluation circuit 8 measure the operation performance such as the operation frequency and power consumption of the target circuit 20 when the target circuit 20 is operated using the test data.

  In step S103, the pass determination circuit 7 determines whether or not the operation performance of the target circuit 20 measured in step S102 satisfies the specification. The performance evaluation circuit 8 determines whether the operation performance of the target circuit 20 measured in step S102 is higher than the operation performance measured in the past. When the operation performance of the target circuit 20 satisfies the specifications and is higher than the operation performance measured in the past, the process proceeds to step S104. When it is determined that the operation performance of the target circuit 20 measured in step S102 does not satisfy the specification or is lower than the operation performance measured in the past, the process returns to step S101. When it is determined that the measured operation performance has not seen the specification or is inferior to the past measurement result, the parameter control unit 1 is notified to that effect. In this case, the parameter set held in the parameter register unit 6 is not stored in the nonvolatile memory 4, and the parameter set newly generated by the parameter generator 3 is held in the parameter register unit 6.

  In step S <b> 104, the parameter control unit 1 transfers the parameter set held in the parameter register unit 6 to the nonvolatile memory 4. As a result, the parameter set stored in the nonvolatile memory 4 is updated. When the parameter set stored in the nonvolatile memory 4 is updated, the process returns to step S101.

  When a normal mode request signal is output from the control device 30 in the process of steps S101 to S104, the normal mode is restored as shown in FIG. 2, and the parameter control unit 1 switches the MUX 5 to the nonvolatile memory 4 side. The parameter set held in the nonvolatile memory 4 is held in the parameter register unit 6. As described above, the normal mode request signal from the control device 30 is generated as an interrupt, and when the normal mode request signal is output, the parameter set held in the nonvolatile memory 4 is held in the parameter register unit 6, The adjustment mode in FIG. 3 is exited.

  As described above in detail, according to the embodiment of the present invention, it is possible to adjust the SoC parameters to be enlarged not only “before shipment” but also “in standby after use”. Performance improvement, adaptation to the operating environment, extension of product life by adapting to aging, etc. can be realized. Furthermore, if the relationship between the parameter set and the evaluation function is appropriate, the autonomous adjustment device 10 is applicable not only to the operating frequency and power consumption but also to other operating performance improvements.

(Specific example of target circuit)
Next, a specific example of the parameter set update operation will be described with reference to FIG. Here, an example of autonomously adjusting the first circuit block 20a and the second circuit block 20b in the target circuit 20 will be described. The first circuit block 20a and the second circuit block 20b are manufactured by the same process and have the same configuration. In addition, as the first to third parameters P1 to P3, the delay value of the clock input is taken and the respective periods of the first circuit block 20a and the second circuit block 20b are evaluated.

  In FIG. 4, the first parameter P1 is a delay value with respect to the clock inputs of the first FFs 201 and 211, the second parameter P2 is a delay value with respect to the clock inputs of the second FFs 203 and 213, and the third parameter P3 is the delay value with respect to the third FFs 205 and 215. This is the delay value for the clock input.

  Combination circuits 202 and 212 exist between the first FF 201 and 211 and the second FF 203 and 213, and combination circuits 204 and 214 exist between the second FF 203 and 213 and the third FF 203 and 213. However, the delay times of the combinational circuits 202, 212, 204, and 214 may vary among individuals due to manufacturing variations. In the example of FIG. 4, in the first circuit block 20a, the delay times of the combinational circuits 202 and 204 are 60 ns and 40 ns, respectively, whereas in the second circuit block 20b, the delay times of the combinational circuits 212 and 214 are 52 ns and 48 ns, respectively. .

  Here, an example in which a delay value is updated by changing a parameter is shown. For example, assume that the parameter generator 3 outputs (P1, P2, P3) = (5 ns, 0 ns, 0 ns) as a new parameter set candidate for the first circuit block 20a. In this case, since the delay time between the first FF 201 and the second FF 203 corresponds to 65 ns when the clock delay of the first FF 201, 211 occurs for 5 ns, the cycle of the circuit becomes long. This parameter set is therefore considered inappropriate and rejected.

  Next, it is assumed that the parameter generator 3 outputs (P1, P2, P3) = (0 ns, 5 ns, 0 ns) as a new parameter set candidate. In that case, since the above-mentioned period is 55 ns, it is determined that this parameter set is more appropriate.

  Similarly, the parameter set is shaken for the second circuit block 20b. The period between the first FF 211 and the second FF 213 in the second circuit block 20b is 52 ns. If (P1, P2, P3) = (5 ns, 0 ns, 0 ns) as a new parameter set candidate, the period becomes 57 ns, and the parameter set is rejected. Next, if (P1, P2, P3) = (0 ns, 5 ns, 0 ns), the period between the second FF 213 and the third FF 215 is 53 ns, which is rejected.

  As described above, even in the same product, parameters that can be adopted in the first circuit block 20a are not necessarily adopted in the second circuit block 20b. In the second circuit block 20b, for example, if (P1, P2, P3) = (0 ns, 1 ns, 0 ns), the cycle between the second FF 213 and the third FF 215 is 51 ns, and it is determined that the state is better. It is determined that the second circuit block 20b can also be employed.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the above-described embodiment, it has been described that the nonvolatile memory 4 stores one set of parameter sets. However, a configuration may be used in which a plurality of sets of parameter sets are stored.

  As shown in FIG. 5, a configuration in which a sensor 40 is provided outside the autonomous adjustment device 10 and a plurality of optimum parameter sets corresponding to the operating environment conditions is prepared is also conceivable. As an example, the operating temperature zone may be divided into three, and the optimum parameters in each operating temperature zone may be loaded.

  Further, it is conceivable to have a function of holding a plurality of parameter sets and a history function of a finite number of parameter sets. However, even in this case, the optimum parameter set is one.

  Further, although the function of directly adjusting the target circuit 20 is not provided, metadata accompanying the parameter set may be stored in the nonvolatile memory 4. As metadata, for example, usage condition information (temperature, etc.) at the time of generating the parameter, algorithm information (random number seed) used by the parameter generator 3, etc. are added, and those information are stored. A configuration used for the next parameter generation can be considered.

  In the embodiment described above, it has been described that each circuit of FIG. 1 is integrated on one chip. However, a part of the circuit may be externally attached to the chip. For example, the power evaluation circuit 8 may be provided outside as the performance evaluation circuit 8 and the power value may be fed back to the chip.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

It is a block diagram which shows the structural example of the autonomous adjustment apparatus which concerns on embodiment of this invention. It is a state transition diagram which shows the transition of the operation state of the autonomous adjustment apparatus which concerns on embodiment of this invention. It is a flowchart which shows the operation example in the adjustment mode of the autonomous adjustment apparatus which concerns on embodiment of this invention. It is a figure for demonstrating the operation example at the time of adjustment mode of the autonomous adjustment apparatus which concerns on embodiment of this invention. It is a block diagram which shows the structural example of the autonomous adjustment apparatus which concerns on other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Parameter control part 4 ... Non-volatile memory 7 ... Pass determination circuit 8 ... Performance evaluation circuit 9 ... Measurement circuit 10 ... Autonomous adjustment device 20 ... Target circuit 30 ... Control device

Claims (5)

An autonomous adjustment device that autonomously adjusts a target circuit,
A non-volatile memory holding a parameter set consisting of a combination of a plurality of parameters for setting the operation performance of the target circuit;
In a standby state, the target circuit shifts from a normal mode in which a normal operation is performed to an adjustment mode in which an adjustment operation is performed on the target circuit, and the parameter set held in the nonvolatile memory is set in the target circuit. An autonomous adjustment device comprising: a parameter control unit.   The autonomous adjustment apparatus according to claim 1, wherein the nonvolatile memory and the parameter control unit are monolithically integrated on the same semiconductor chip. A measurement circuit for measuring the operation performance of the target circuit set with the parameter set in the adjustment mode;
The measuring circuit is
A pass determination circuit for determining whether the operation performance of the target circuit satisfies the specification; and
A performance evaluation circuit for evaluating whether the operation performance of the target circuit is superior to the operation characteristics measured in the past,
The parameter control unit, when the operation performance of the target circuit satisfies a specification and the operation performance of the target circuit is superior to the operation characteristics measured in the past in the adjustment mode, The autonomous adjustment apparatus according to claim 1, wherein the parameter set held in the system is updated.   The autonomous adjustment device according to claim 1, wherein the nonvolatile memory holds a plurality of parameter sets.   5. The autonomous adjustment device according to claim 1, wherein the parameter control unit updates the parameter set in accordance with information on an operating environment detected by an external sensor.

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