JP2007306710A - Motor-driven power steering system - Google Patents

Motor-driven power steering system Download PDF

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JP2007306710A
JP2007306710A JP2006132754A JP2006132754A JP2007306710A JP 2007306710 A JP2007306710 A JP 2007306710A JP 2006132754 A JP2006132754 A JP 2006132754A JP 2006132754 A JP2006132754 A JP 2006132754A JP 2007306710 A JP2007306710 A JP 2007306710A
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motor
driver
fet
bridge circuit
power steering
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Kazumichi Tsutsumi
和道 堤
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a motor-driven power steering system that suppresses noise harmful to peripheral equipment. <P>SOLUTION: This motor-driven power steering system assists a driver's steering force by conducting a current corresponding to the driver's steering force detected by a torque sensor 1 to a motor 2 by controlling a bridge circuit 31. In this power steering system, inductance elements 311, 312 are inserted in series to the source of field-effect transistors constituting the bridge circuit 31 that controls the motor 2. At the same time, a control voltage of the bridge circuit 31 is added to obtain a gate drive voltage of the field-effect transistors, by using the electric potential of the opposite-to-source end of the inductance elements 311, 312 or the electric potential in the middle of the inductance elements 311, 312 as a reference. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は，自動車の運転者の操舵力をモータにより補助する電動パワーステアリング装置に関するものである。   The present invention relates to an electric power steering apparatus that assists a steering force of a driver of an automobile with a motor.

モータを用いた自動車の電動パワーステアリング装置においては、バッテリから供給される電圧を、駆動回路にてパルス幅変調(ＰＷＭ：pulse width modulation)してモータに印加する手法が一般に用いられている。しかし、操舵を補助するには大きな電流が必要であって、この大電流が上記ＰＷＭ駆動により高周波でスイッチングされるので、電動パワーステアリング装置はラジオ等の周辺機器に対して有害なノイズを発生する。この対策として、例えば特許文献１においては、上記駆動回路を構成するＦＥＴ（fieldeffect transistor）のゲートを駆動する為の電圧を得るのに、従来の昇圧回路ではなく、ブートストラップ回路を用いれば、昇圧回路が発生するノイズが除去できる、との提案がなされている。   In an electric power steering apparatus for an automobile using a motor, a method is generally used in which a voltage supplied from a battery is applied to a motor after being subjected to pulse width modulation (PWM) by a drive circuit. However, since a large current is required to assist steering, and this large current is switched at a high frequency by the PWM drive, the electric power steering device generates harmful noise for peripheral devices such as a radio. . As a countermeasure, for example, in Patent Document 1, if a bootstrap circuit is used instead of a conventional booster circuit in order to obtain a voltage for driving a gate of an FET (field effect transistor) constituting the drive circuit, a booster is used. It has been proposed that noise generated by the circuit can be removed.

特開平５−６９８３３号公報（[０００７]―[００１０]、図１）JP-A-5-69833 ([0007]-[0010], FIG. 1)

前記従来装置においては、昇圧回路が発生するノイズは除去できるものであるが、大電流をスイッチングすることにより発生するノイズと比較して、昇圧回路が発生するノイズは軽微であって、前記従来装置では対策の効果は不十分であった。この発明は、このような従来の電動パワーステアリング装置の問題を解消するためになされたもので、周辺機器に対して有害なノイズの発生を抑制できる電動パワーステアリング装置を提供することを目的としている。   In the conventional device, the noise generated by the booster circuit can be removed. However, the noise generated by the booster circuit is small compared to the noise generated by switching a large current. Then, the effect of the countermeasure was insufficient. The present invention has been made to solve the problems of the conventional electric power steering apparatus, and an object thereof is to provide an electric power steering apparatus capable of suppressing generation of noise harmful to peripheral devices. .

この発明に係わる電動パワーステアリング装置は、自動車の運転者の操舵力を検出するトルクセンサと、運転者の操舵力を補助するモータと、電界効果トランジスタで構成されるブリッジ回路を有し前記モータを制御する制御装置とを備え、前記トルクセンサで検出された運転者の操舵力に応じた電流を前記ブリッジ回路を制御して前記モータに通電することにより、運転者の操舵力を補助する電動パワーステアリング装置において、前記モータを制御する前記ブリッジ回路を構成する電界効果トランジスタのソースに直列にインダクタンス素子を挿入すると共に、前記インダクタンス素子の反ソース端の電位を基準として、又は、前記インダクタンス素子の中間の電位を基準として、前記ブリッジ回路の制御電圧を加算して前記電界効果トランジスタのゲート駆動電圧を得るようにしたものである。   An electric power steering apparatus according to the present invention includes a torque sensor that detects a steering force of an automobile driver, a motor that assists the steering force of the driver, and a bridge circuit that includes a field effect transistor. An electric power for assisting the steering force of the driver by controlling the bridge circuit and energizing the motor with a current corresponding to the steering force of the driver detected by the torque sensor. In the steering device, an inductance element is inserted in series with the source of the field effect transistor that constitutes the bridge circuit that controls the motor, and the potential at the non-source end of the inductance element is used as a reference or in the middle of the inductance element. The control voltage of the bridge circuit is added on the basis of the potential of the It is obtained so as to obtain a gate drive voltage of Njisuta.

また、この発明に係わる電動パワーステアリング装置は、自動車の運転者の操舵力を検出するトルクセンサと、運転者の操舵力を補助するモータと、電界効果トランジスタで構成されるインバータ回路を有し前記モータを制御する制御装置とを備え、前記トルクセンサで検出された運転者の操舵力に応じた電流を前記インバータ回路を制御して前記モータに通電することにより、運転者の操舵力を補助する電動パワーステアリング装置において、前記モータを制御する前記インバータ回路を構成する電界効果トランジスタのソースに直列にインダクタンス素子を挿入すると共に、前記インダクタンス素子の反ソース端の電位を基準として、又は、前記インダクタンス素子の中間の電位を基準として、前記インバータ回路の制御電圧を加算して前記電界効果トランジスタのゲート駆動電圧を得るようにしたものである。   An electric power steering device according to the present invention includes a torque sensor that detects a steering force of a driver of an automobile, a motor that assists the steering force of the driver, and an inverter circuit including a field effect transistor. A control device for controlling the motor, and assisting the driver's steering force by controlling the inverter circuit and energizing the motor with a current corresponding to the driver's steering force detected by the torque sensor. In the electric power steering apparatus, an inductance element is inserted in series with a source of a field effect transistor constituting the inverter circuit for controlling the motor, and the inductance element is based on the potential at the non-source end of the inductance element. Add the control voltage of the inverter circuit with reference to the middle potential of It is obtained so as to obtain a gate drive voltage of the serial field effect transistor.

この発明の電動パワーステアリング装置によれば、前記モータを制御する前記ブリッジ回路を構成する電界効果トランジスタのソースに直列にインダクタンス素子を挿入すると共に、前記インダクタンス素子の反ソース端の電位を基準として、又は、前記インダクタンス素子の中間の電位を基準として、前記ブリッジ回路の制御電圧を加算して前記電界効果トランジスタのゲート駆動電圧を得るようにしたので、周辺機器に対して有害なノイズを抑制できる電動パワーステアリング装置を得ることができる。   According to the electric power steering device of the present invention, an inductance element is inserted in series with the source of the field effect transistor that constitutes the bridge circuit that controls the motor, and the potential at the non-source end of the inductance element is used as a reference. Alternatively, since the gate drive voltage of the field effect transistor is obtained by adding the control voltage of the bridge circuit with reference to the intermediate potential of the inductance element, the electric motor can suppress noise harmful to peripheral devices. A power steering device can be obtained.

この発明の電動パワーステアリング装置によれば、前記モータを制御する前記インバータ回路を構成する電界効果トランジスタのソースに直列にインダクタンス素子を挿入すると共に、前記インダクタンス素子の反ソース端の電位を基準として、又は、前記インダクタンス素子の中間の電位を基準として、前記インバータ回路の制御電圧を加算して前記電界効果トランジスタのゲート駆動電圧を得るようにしたので、周辺機器に対して有害なノイズを抑制できる電動パワーステアリング装置を得ることができる。   According to the electric power steering apparatus of the present invention, an inductance element is inserted in series with the source of the field effect transistor that constitutes the inverter circuit that controls the motor, and the potential at the non-source end of the inductance element is used as a reference. Alternatively, since the gate drive voltage of the field effect transistor is obtained by adding the control voltage of the inverter circuit with the intermediate potential of the inductance element as a reference, the electric motor capable of suppressing noise harmful to peripheral devices A power steering device can be obtained.

実施の形態１．
図１はこの発明の実施の形態１による電動パワーステアリング装置を示す回路構成図である。図において、１は自動車の運転者の操舵力を検出するトルクセンサ、２は運転者の操舵力を補助するモータである。３は制御装置であって、自動車のバッテリ４から電源の供給を受けて、モータを駆動するＨブリッジ回路３１と、このＨブリッジ回路３１を構成する４個のＦＥＴ（field effect transistor）を制御するＦＥＴドライバ３２と、モータ２の駆動ライン内に挿入されたシャント抵抗３７の両端の電圧差からモータ２への通電電流を検出する電流検出回路３３と、モータ２の電流制御を司るＣＰＵ３４から構成されている。ここで、Ｈブリッジ回路３１による後述するスイッチング動作の影響がバッテリ４に及ばないように、バッテリ４からの電源はチョークコイル３５を経てコンデンサ３６に蓄電された後に、Ｈブリッジ回路３１へ供給されるように構成されている。 Embodiment 1 FIG.
1 is a circuit diagram showing an electric power steering apparatus according to Embodiment 1 of the present invention. In the figure, reference numeral 1 denotes a torque sensor for detecting the steering force of the driver of the automobile, and 2 denotes a motor for assisting the steering force of the driver. Reference numeral 3 denotes a control device which receives power from the automobile battery 4 and controls an H bridge circuit 31 for driving the motor and four FETs (field effect transistors) constituting the H bridge circuit 31. It comprises an FET driver 32, a current detection circuit 33 that detects a current flowing to the motor 2 from a voltage difference between both ends of a shunt resistor 37 inserted in the drive line of the motor 2, and a CPU 34 that controls current control of the motor 2. ing. Here, the power from the battery 4 is stored in the capacitor 36 via the choke coil 35 and then supplied to the H bridge circuit 31 so that the influence of the switching operation described later by the H bridge circuit 31 does not affect the battery 4. It is configured as follows.

前記構成にて、トルクセンサ１は運転者の操舵トルクに比例した信号を出力する。このトルクセンサ１の出力を受けて、ＣＰＵ３４の目標電流設定ブロック３４１は予め設定されたデータテーブルに従って、モータ２に通電すべき電流の目標値(ＩＴ)を設定する。一方、ＣＰＵ３４は電流検出回路３３にて検出されたモータ２の通電電流をＡ／Ｄ変換器３４４でＡ／Ｄ変換し、このＡ／Ｄ変換された検出電流値(ＩＭ)を前記目標電流値(ＩＴ)から減算して差を求め、次段のＤｕｔｙ比算出ブロック３４２にて、この差が零となるように、例えば比例積分制御の手法により、Ｈブリッジ回路３１を制御すべきＰＷＭ(pulsewidth modulation)パルスのＤｕｔｙ比を算出する。次段のパルス発生器３４３では、この算出されたＤｕｔｙ比を受けて、Ｈブリッジ回路３１を構成する４個のＦＥＴへの制御パルス（制御電圧）を発生する。Ｈブリッジ回路３１は、ＦＥＴドライバ３２を介してこの制御パルスにより制御される。以上のようにして、モータ２の通電電流(ＩＭ)は目標電流(ＩＴ)に制御され、運転者の操舵力に応じた補助力に制御される。   With the above configuration, the torque sensor 1 outputs a signal proportional to the driver's steering torque. In response to the output of the torque sensor 1, the target current setting block 341 of the CPU 34 sets a target value (IT) of the current to be supplied to the motor 2 in accordance with a preset data table. On the other hand, the CPU 34 A / D converts the energization current of the motor 2 detected by the current detection circuit 33 by the A / D converter 344, and the detected current value (IM) obtained by the A / D conversion is converted into the target current value. (IT) is subtracted to obtain a difference, and in the next-stage duty ratio calculation block 342, the PWM (pulsewidth) to control the H-bridge circuit 31 is controlled by, for example, a proportional integral control method so that the difference becomes zero. modulation) Calculate the duty ratio of the pulse. The next-stage pulse generator 343 receives the calculated duty ratio and generates control pulses (control voltages) for the four FETs constituting the H-bridge circuit 31. The H bridge circuit 31 is controlled by this control pulse via the FET driver 32. As described above, the energization current (IM) of the motor 2 is controlled to the target current (IT), and is controlled to the auxiliary force according to the steering force of the driver.

以下、実施の形態１におけるＨブリッジ回路３１の動作について説明する。図1に示すように、Ｈブリッジ回路３１の下段の二つのＦＥＴ(ＦＥＴ３,ＦＥＴ４)には、各々ソースと直列にインダクタンスLを持つコイル（インダクタンス素子）３１１、３１２が挿入されており、その下端の電位がＦＥＴドライバ３２に帰還される。このＦＥＴドライバ３２は、Ｈブリッジ回路３１を構成する４個のＦＥＴに対応した４個のバッファ回路から成り、内二つの下段ＦＥＴ(ＦＥＴ３,ＦＥＴ４)に対応するバッファ回路は、前記の帰還された電位（基準とする電位）に、前段のパルス発生器３４３からのＯＮ・ＯＦＦ信号に応じた所定のゲート制御電圧を加算して出力する。例えば、ゲート制御電圧を１０Ｖとして帰還電位が２Ｖの場合、パルス発生器３４３の出力がＯＮであれば２Ｖに１０Ｖを加算して１２Ｖを出力してＦＥＴのゲート駆動電圧とし、ＯＦＦであれば帰還電位のみの２Ｖを出力してＦＥＴのゲート駆動電圧としている。   Hereinafter, the operation of the H-bridge circuit 31 in the first embodiment will be described. As shown in FIG. 1, coils (inductance elements) 311 and 312 having inductance L in series with the source are inserted in the lower two FETs (FET3 and FET4) at the lower stage of the H-bridge circuit 31, respectively. Is fed back to the FET driver 32. The FET driver 32 is composed of four buffer circuits corresponding to the four FETs constituting the H-bridge circuit 31, and the buffer circuits corresponding to the two lower FETs (FET3, FET4) are fed back as described above. A predetermined gate control voltage corresponding to the ON / OFF signal from the preceding pulse generator 343 is added to the potential (reference potential) and output. For example, when the gate control voltage is 10 V and the feedback potential is 2 V, if the output of the pulse generator 343 is ON, 10 V is added to 2 V and 12 V is output as the gate drive voltage of the FET, and if it is OFF, feedback Only 2V of potential is output and used as the gate drive voltage of the FET.

Ｈブリッジ回路３１の下段の２個のＦＥＴ(ＦＥＴ３,ＦＥＴ４)は、モータ２への通電の方向（モータの回転方向）に応じて右アーム又は左アームがＰＷＭ駆動され、モータ２への時間平均された印加電圧はＰＷＭ駆動パルスのＤｕｔｙ比に比例する。この時、ＰＷＭ駆動されていない他方のＦＥＴ(ＦＥＴ３又はＦＥＴ４)はＯＦＦの状態に駆動される。上段の２個のＦＥＴ(ＦＥＴ１,ＦＥＴ２)はＰＷＭ駆動では無く、モータ２への通電の方向に応じてＯＮ又はＯＦＦの状態に駆動される。モータ２の通電の方向と４個のＦＥＴの駆動状態との関係について、図２（ａ）（ｂ）に従って説明する。図２はＰＷＭ駆動されるブリッジ回路のＦＥＴのタイミングチャートである。図２（ａ）に示すように、右アームの上段のＦＥＴ２をＯＮ、それと対を成す左アームの下段のＦＥＴ３をＰＷＭ駆動した場合、モータ２はそのＭ＋端子からＭ−端子へ向かって通電される。次に図２（ｂ）に示すように、左アームの上段のＦＥＴ１をＯＮ状態に駆動し、それと対を成す右アームの下段のＦＥＴ４をＰＷＭ駆動した場合、モータ２はそのＭ−端子からＭ＋端子へ向かって通電される。ここで、ＰＷＭパルスは、図２（ｂ）に示すように所定の周期Ｔのパルスであって、同図中Ｔｏｎで示す所定の区間ＯＮされ、Ｔｏｆｆで示す区間ＯＦＦされる。通常、このＰＷＭパルスは２０ｋＨｚに設定されることが多い。   The two lower FETs (FET3, FET4) at the lower stage of the H-bridge circuit 31 are PWM-driven on the right arm or the left arm according to the direction of energization to the motor 2 (motor rotation direction), and the time average to the motor 2 The applied voltage is proportional to the duty ratio of the PWM drive pulse. At this time, the other FET (FET3 or FET4) not PWM-driven is driven to an OFF state. The upper two FETs (FET1, FET2) are not driven by PWM, but are driven to ON or OFF depending on the direction of energization of the motor 2. The relationship between the energization direction of the motor 2 and the driving states of the four FETs will be described with reference to FIGS. FIG. 2 is a timing chart of the FET of the bridge circuit driven by PWM. As shown in FIG. 2 (a), when the upper FET 2 of the right arm is turned on and the lower FET 3 of the left arm that is paired with it is PWM driven, the motor 2 is energized from its M + terminal to its M− terminal. The Next, as shown in FIG. 2B, when the upper FET 1 of the left arm is driven to the ON state and the lower FET 4 of the right arm that is paired with the upper FET 1 is PWM driven, the motor 2 receives M + from its M− terminal. Energized toward the terminal. Here, the PWM pulse is a pulse having a predetermined cycle T as shown in FIG. 2B, and is turned ON for a predetermined section indicated by Ton and turned OFF for Toff in the figure. Usually, this PWM pulse is often set to 20 kHz.

以下、図３（ａ）（ｂ）（ｃ）及び図４に従ってＦＥＴ３、ＦＥＴ４のソースに直列に挿入されたインダクタンス素子（コイル）の働きについて詳述する。図３（ａ）（ｂ）（ｃ）は、Ｈブリッジ回路３１を構成する４個のＦＥＴの駆動状態とモータ２の電流経路の関係を模式的に表した説明図であり、各ＦＥＴの駆動状態をスイッチのＯＮ・ＯＦＦ又は抵抗で表現している。また、スイッチと並列に記したダイオードはＦＥＴの寄生ダイオードを示し、図中の破線はモータ２の電流経路を示し、破線中の矢印は電流の方向を表している。ここではＨブリッジ回路３１の右アームの上段ＦＥＴ２をＯＮ状態に駆動し、左アームの下段のＦＥＴ３をＰＷＭ駆動した場合を示している。この場合、モータ２の電流はＭ＋端子からＭ−端子の方向に流れる。左アームの上段ＦＥＴ１をＯＮ状態に駆動して右アームの下段のＦＥＴ４をＰＷＭ駆動した場合にも同様に動作し、この場合にはモータ２の電流方向が逆となる。   Hereinafter, the function of the inductance element (coil) inserted in series with the sources of the FET3 and FET4 will be described in detail with reference to FIGS. 3 (a), (b), (c) and FIG. FIGS. 3A, 3B, and 3C are explanatory views schematically showing the relationship between the drive states of the four FETs constituting the H-bridge circuit 31 and the current path of the motor 2, and the drive of each FET. The state is expressed by switch ON / OFF or resistance. Further, a diode written in parallel with the switch indicates a parasitic diode of the FET, a broken line in the figure indicates a current path of the motor 2, and an arrow in the broken line indicates a current direction. Here, a case is shown in which the upper FET 2 of the right arm of the H bridge circuit 31 is driven to the ON state and the lower FET 3 of the left arm is PWM driven. In this case, the current of the motor 2 flows from the M + terminal to the M− terminal. The same operation is performed when the upper FET 1 of the left arm is driven ON and the lower FET 4 of the right arm is PWM driven. In this case, the current direction of the motor 2 is reversed.

図３（ｃ）に示す、ＰＷＭ駆動されるＦＥＴ３がＯＮの状態にある期間、モータ電流は同図に示すようにコンデンサ３６を出て、ＦＥＴ２、モータ２、ＦＥＴ３を通って該コンデンサ３６に戻る経路を流れる。この間、モータ電流はコンデンサ３６から供給されて徐々に増加する。次にＦＥＴ３の駆動状態がＯＦＦに変わると、図３（ａ）に示すようにモータ電流は経路が転流され、ＯＮ状態にあるＦＥＴ２とＯＦＦ状態にあるＦＥＴ１の寄生ダイオードから成るループを循環する。この間、この循環経路内の抵抗分により電力損失が発生するので電流は徐々に減少する。以上のように、モータ電流の経路はＦＥＴのＰＷＭ駆動状態に応じて切り替わる。操舵の補助に必要な電流値は、通常は数十アンペアと大きく、またＰＷＭ駆動の周波数は通常は２０ｋＨｚ程度と高周波であるので、このモータ電流の転流によりノイズが発生し、その程度は転流速度が高速である程大きくなる。従って、この転流速度を低下させることにより、ノイズの発生を抑制できるのであるが、転流の間、ＦＥＴは後述するようにＯＮとＯＦＦとの中間の状態にあって、抵抗分による電力損失を生じるので、転流速度はノイズの抑制と電力損失の抑制とを両立し得る値に設定する必要がある。つまり電力損失が許容できる範囲で転流速度を抑制する必要がある。   As shown in FIG. 3C, during the period in which the PWM-driven FET 3 is in the ON state, the motor current exits the capacitor 36 as shown in the figure, and returns to the capacitor 36 through the FET 2, the motor 2, and the FET 3. Flowing the route. During this time, the motor current is supplied from the capacitor 36 and gradually increases. Next, when the driving state of the FET 3 is changed to OFF, as shown in FIG. 3A, the path of the motor current is commutated and circulates through a loop composed of a parasitic diode of the FET 2 in the ON state and the FET 1 in the OFF state. . During this time, power loss occurs due to the resistance in the circulation path, so the current gradually decreases. As described above, the path of the motor current is switched according to the PWM driving state of the FET. The current value required for steering assistance is usually as high as several tens of amperes, and the frequency of PWM drive is usually as high as about 20 kHz. The higher the flow velocity, the larger the flow velocity. Therefore, by reducing the commutation speed, it is possible to suppress the generation of noise, but during the commutation, the FET is in an intermediate state between ON and OFF as will be described later, and the power loss due to the resistance component Therefore, the commutation speed must be set to a value that can achieve both noise suppression and power loss suppression. That is, it is necessary to suppress the commutation speed within a range where the power loss is allowable.

以下、この転流時の動作について、特にコイル３１１、３１２の作用に着目して説明する。図４はＰＷＭ駆動の1周期内の各部の動作の詳細を表したタイミングチャートである。同図において、Ｓ１はＣＰＵ３４からの出力パルス、Ｓ２はＦＥＴドライバ３２の出力、Ｓ３はＦＥＴ３のゲート電圧、Ｓ４はＦＥＴ３のソース電流、Ｓ５はＦＥＴ３のドレイン電圧を表している。なお、同図の各信号の電圧レベルはＦＥＴ３のソース電位を基準にして表している。   Hereinafter, the operation at the time of commutation will be described by focusing attention on the action of the coils 311 and 312. FIG. 4 is a timing chart showing details of the operation of each part in one cycle of PWM driving. In the figure, S1 represents an output pulse from the CPU 34, S2 represents an output of the FET driver 32, S3 represents a gate voltage of the FET 3, S4 represents a source current of the FET 3, and S5 represents a drain voltage of the FET 3. Note that the voltage level of each signal in the figure is expressed with reference to the source potential of the FET 3.

まず、ＣＰＵ３４から出力されるパルス(Ｓ１)がＯＦＦ状態にある期間、上述したように、モータ電流は図３（ａ）に示す経路を循環する。次にＦＥＴ３がＯＦＦ状態からＯＮ状態へと転じるターンＯＮの動作について説明する。図４にＴ１で示すタイミングにてＣＰＵ３４からＯＮのパルス(Ｓ１)が出力されると、ＦＥＴドライバ３２の出力(Ｓ２)はHighとなり、図1に示すゲート抵抗Ｒｇを介して、ＦＥＴ３のゲートの入力容量が充電されてゲート電圧(Ｓ３)が上昇する。このゲート電圧(Ｓ３)が図４にＴ２で示すタイミングにて所定の閾値(Ｖthon)に達すると、モータ電流の転流が開始する。即ち、それ迄はＯＦＦの状態にあったＦＥＴ３のドレインとソースの間の抵抗値が低下して、モータ電流の一部が図３（ｂ）に示すように、ＦＥＴ３を流れ始める。この電流はソースに直列に挿入されたコイル３１１を流れるので、コイル３１１の両端間には下記(1)式に従って電流の増加の速度に比例した電圧(Ｖｃ)が生じる。   First, during the period in which the pulse (S1) output from the CPU 34 is in the OFF state, the motor current circulates through the path shown in FIG. Next, the turn-on operation in which the FET 3 turns from the OFF state to the ON state will be described. When the ON pulse (S1) is output from the CPU 34 at the timing indicated by T1 in FIG. 4, the output (S2) of the FET driver 32 becomes High, and the gate of the FET 3 is passed through the gate resistance Rg shown in FIG. The input capacitance is charged and the gate voltage (S3) rises. When this gate voltage (S3) reaches a predetermined threshold value (Vthon) at the timing indicated by T2 in FIG. 4, commutation of the motor current starts. That is, the resistance value between the drain and the source of the FET 3 that has been in the OFF state decreases until then, and a part of the motor current starts to flow through the FET 3 as shown in FIG. Since this current flows through the coil 311 inserted in series with the source, a voltage (Vc) proportional to the rate of increase of the current is generated between both ends of the coil 311 according to the following equation (1).

Ｖｃ＝Ｌ×[dＩｓ／dｔ] ------（１）
ここで、Ｌはコイル３１１のインダクタンス、ＩｓはＦＥＴ３のソース電流、ｔは時間を示す。前述したようにＦＥＴドライバ３２は、このコイルの下端の電位を基準として、これに所定の制御電圧を加算して出力するので、モータ電流の転流開始（Ｔ２）と共にその出力電圧（Ｓ２）は低下し、ＦＥＴ３のソース電流の増加が速まろうとすると、ＦＥＴドライバ３２からの出力(Ｓ２)はより低下してＦＥＴ３のドレインとソースの間の抵抗値の低下速度が抑制される。 Vc = L × [dIs / dt] ------ (1)
Here, L is the inductance of the coil 311, Is is the source current of the FET 3, and t is time. As described above, the FET driver 32 adds and outputs a predetermined control voltage with reference to the potential at the lower end of the coil, and therefore, the output voltage (S2) at the same time as the commutation of the motor current (T2) starts. If the source current of the FET 3 increases and the source current of the FET 3 increases, the output (S2) from the FET driver 32 further decreases, and the rate of decrease in the resistance value between the drain and source of the FET 3 is suppressed.

つまり、ＦＥＴ３を流れるモータ電流の増加速度が、コイル３１１のインダクタンスＬによって規定される。以降、ＦＥＴ３を流れる電流が増加を続け、図４にＴ３で示すタイミングにてモータ電流の全てがＦＥＴ３へ流れると、即ちモータ電流の転流が完了すると、ＦＥＴ３のドレイン電圧(Ｓ５)は低下してソース電位に達し、その後にゲートの入力電圧(Ｓ３)はＦＥＴドライバ３２の出力電圧（Ｓ２）に達する。以上でターンＯＮの動作を完了し、モータ電流は図３（ｃ）に示すように、右アームの上段のＦＥＴ２から左アームの下段のＦＥＴ３に向かって流れる。   That is, the increasing speed of the motor current flowing through the FET 3 is defined by the inductance L of the coil 311. Thereafter, the current flowing through the FET 3 continues to increase, and when all of the motor current flows to the FET 3 at the timing indicated by T3 in FIG. 4, that is, when the commutation of the motor current is completed, the drain voltage (S5) of the FET 3 decreases. Then, the source potential is reached, and then the gate input voltage (S3) reaches the output voltage (S2) of the FET driver 32. Thus, the turn-on operation is completed, and the motor current flows from the upper FET 2 in the right arm toward the lower FET 3 in the left arm as shown in FIG.

次にＦＥＴ３がＯＮ状態からＯＦＦ状態へと転じるターンＯＦＦの動作について説明する。図４にＴ４で示すタイミングにて、ＣＰＵ３４からのパルス(Ｓ１)がＯＦＦに変化すると、ＦＥＴドライバ３２の出力(Ｓ２)はLowとなり、図1に示すゲート抵抗Ｒｇを介してＦＥＴ３のゲートの入力容量が放電されて、ゲート電圧(Ｓ３)が下降する。このゲート電圧(Ｓ３)が、図４にＴ５で示すタイミングにて所定の閾値(Ｖthon)に達すると、ＦＥＴ３のドレイン電圧が上昇して電源電圧に達し、以降モータ電流の転流が開始する。   Next, the turn-off operation in which the FET 3 turns from the ON state to the OFF state will be described. When the pulse (S1) from the CPU 34 changes to OFF at the timing indicated by T4 in FIG. 4, the output (S2) of the FET driver 32 becomes Low, and the input of the gate of the FET 3 via the gate resistance Rg shown in FIG. The capacitance is discharged, and the gate voltage (S3) decreases. When the gate voltage (S3) reaches a predetermined threshold value (Vthon) at the timing indicated by T5 in FIG. 4, the drain voltage of the FET 3 rises to reach the power supply voltage, and then the commutation of the motor current starts.

即ち、それ迄はＯＮの状態にあったＦＥＴ３のドレインとソースの間の抵抗値が増加して、モータ電流の一部が図３（ｂ）に示すように、ＦＥＴ１の寄生ダイオードを流れ始める。ＦＥＴ３を流れる電流はソースに直列に挿入されたコイル３１１を流れるので、その減少の速度は、上述のターンＯＮ時と同様にして、コイル３１１のインダクタンスＬにより規定される。以降、ＦＥＴ３を流れる電流が減少を続け、図４にＴ６で示すタイミングにてモータ電流の全てがＦＥＴ１の寄生ダイオードへ流れると、即ちモータ電流の転流が完了すると、ＦＥＴ３のゲート電圧(Ｓ３)は低下してソース電位に達する。以上でターンＯＦＦの動作を完了し、モータ電流は図３（ａ）に示すようにＯＮ状態にあるＦＥＴ２とＯＦＦ状態にあるＦＥＴ１の寄生ダイオードから成る経路を循環して流れる。   That is, the resistance value between the drain and the source of the FET 3 that has been in the ON state increases until then, and a part of the motor current starts to flow through the parasitic diode of the FET 1 as shown in FIG. Since the current flowing through the FET 3 flows through the coil 311 inserted in series with the source, the rate of decrease is defined by the inductance L of the coil 311 in the same manner as in the above-described turn-on. Thereafter, when the current flowing through the FET 3 continues to decrease and all of the motor current flows to the parasitic diode of the FET 1 at the timing indicated by T6 in FIG. 4, that is, when the commutation of the motor current is completed, the gate voltage of the FET 3 (S3) Decreases to the source potential. Thus, the turn-off operation is completed, and the motor current circulates through a path composed of the FET2 in the ON state and the parasitic diode of the FET1 in the OFF state as shown in FIG.

以上の動作の中で、コイル３１１のインダクタンスＬは電流の変化速度検出器として作用し、検出した値をＦＥＴドライバ３２へ帰還することにより、ＦＥＴ３のソース電流の変化速度を規定し抑制している。このようにして、ＦＥＴのＰＷＭ駆動に伴うモータ電流の転流時の電流の増減速度がコイル３１１のインダクタンスＬにより規定し抑制されるので、このインダクタンスＬを適切な値に設定することにより、転流時のスイッチング損失を抑えると共に（スイッチング損失を許容できる範囲に抑えると共に）発生するノイズを抑制することができる。   In the above operation, the inductance L of the coil 311 acts as a current change rate detector, and by feeding back the detected value to the FET driver 32, the change rate of the source current of the FET 3 is specified and suppressed. . In this way, the speed of increase / decrease of the current during commutation of the motor current accompanying PWM drive of the FET is regulated and suppressed by the inductance L of the coil 311. Therefore, by setting this inductance L to an appropriate value, While suppressing the switching loss at the time of flowing (with suppressing the switching loss within an allowable range), the generated noise can be suppressed.

実施の形態２．
ところで、以上の説明では、ＦＥＴのソースと直列にコイルを挿入した場合について述べたが、このコイル（インダクタンス素子）のインダクタンスを、Ｈブリッジ回路３１を実装したプリント基板の銅箔パターンで形成しても同様の効果を得ることができる。これについて、図５、及び図６に従って説明する。図５は実施の形態２に用いるプリント基板を示す構成図である。図６は実施の形態２に用いるプリント基板の動作を説明するタイミングチャートである。 Embodiment 2. FIG.
By the way, in the above description, the case where the coil is inserted in series with the source of the FET has been described, but the inductance of this coil (inductance element) is formed by the copper foil pattern of the printed circuit board on which the H bridge circuit 31 is mounted. The same effect can be obtained. This will be described with reference to FIGS. FIG. 5 is a block diagram showing a printed circuit board used in the second embodiment. FIG. 6 is a timing chart for explaining the operation of the printed circuit board used in the second embodiment.

図５において、３１３はＨブリッジ回路３１を実装したプリント基板の一部を示したもので、ＦＥＴ２、ＦＥＴ３とその周辺部を表している。簡単の為に他の部分は省略し、またプリント基板以外の部分は図1と同様の回路構成図で記述している。なお、銅箔は同図中に斜線を付して示している。ＦＥＴ２及びＦＥＴ３のゲート(Ｇ)は、各々抵抗Ｒｇを介してＦＥＴドライバ３２から駆動される。ここで、ＦＥＴ２がＯＮ状態に駆動され、ＦＥＴ３がＰＷＭ駆動されている場合、モータ２はそのＭ＋端子からM-端子に向かって通電される。ＰＷＭ駆動にてＦＥＴ３がＯＮ状態にある期間では、モータ電流は、コンデンサ３６を出て、ＦＥＴ２のドレイン(Ｄ)、ＦＥＴ２のソース(Ｓ)、モータ２、ＦＥＴ３のドレイン(Ｄ)、ＦＥＴ３のソース(Ｓ)を順次通ってコンデンサ３６に戻る電流経路を流れる。   In FIG. 5, reference numeral 313 denotes a part of the printed circuit board on which the H-bridge circuit 31 is mounted, and represents FET2, FET3 and their peripheral parts. Other parts are omitted for the sake of simplicity, and parts other than the printed circuit board are described in a circuit configuration diagram similar to FIG. The copper foil is indicated by hatching in FIG. The gates (G) of the FET2 and FET3 are each driven from the FET driver 32 via the resistor Rg. Here, when the FET 2 is driven to the ON state and the FET 3 is PWM-driven, the motor 2 is energized from the M + terminal toward the M− terminal. During the period in which FET3 is in the ON state by PWM driving, the motor current exits the capacitor 36, the drain (D) of FET2, the source (S) of FET2, the drain (D) of motor 2, FET3, and the source of FET3. A current path that sequentially passes through (S) and returns to the capacitor 36 flows.

ここで、ＦＥＴ３のソース(Ｓ)とコンデンサ３６は銅箔で接続されているが、銅箔はその厚みと幅と長さにて定まる所定のインダクタンスを持っている。従って、このＦＥＴ３のソース(Ｓ)とコンデンサ３６を接続する銅箔の所定の個所から電位信号を引き出して、ＦＥＴドライバ３２のＦＥＴ３のゲート(Ｇ)を駆動するバッファ回路へ帰還すると、前述したコイル３１１と同等の効果を得ることができる。また、銅箔によるインダクタンスは銅箔の長さに比例するので、ＦＥＴ３のソース(Ｓ)から帰還電圧を引き出す点までの距離によってモータ電流が転流する時の電流の増減の速度を調整することができる。   Here, the source (S) of the FET 3 and the capacitor 36 are connected by a copper foil, and the copper foil has a predetermined inductance determined by its thickness, width and length. Therefore, when a potential signal is extracted from a predetermined portion of the copper foil connecting the source (S) of the FET 3 and the capacitor 36 and fed back to the buffer circuit for driving the gate (G) of the FET 3 of the FET driver 32, the coil described above is obtained. The same effect as 311 can be obtained. Further, since the inductance due to the copper foil is proportional to the length of the copper foil, the speed of increase / decrease of the current when the motor current is commutated is adjusted by the distance from the source (S) of the FET 3 to the point where the feedback voltage is drawn. Can do.

図６にその様子を示す。同図にてＳ６はＣＰＵ３４からのＰＷＭ駆動パルス、Ｓ７はＦＥＴ３のソース電流を示し、Ｓ７の実線は図５にて[ＰＡ]で記述した点からＦＥＴドライバ３２への帰還電圧信号を引き出した場合を示し、破線は[ＰＢ]で記述した点から帰還電圧（電位）信号を引き出した場合を示している。点[ＰＢ]のＦＥＴ３のソース(Ｓ)からの距離は、点[ＰＡ]からの距離よりも短くインダクタンスの値が小さいので、同図に示すように電流の増減速度が速くなっている。   This is shown in FIG. In the figure, S6 represents a PWM drive pulse from the CPU 34, S7 represents a source current of the FET 3, and a solid line of S7 represents a case where a feedback voltage signal to the FET driver 32 is drawn from the point described as [PA] in FIG. The broken line indicates the case where the feedback voltage (potential) signal is drawn from the point described by [PB]. Since the distance of the point [PB] from the source (S) of the FET 3 is shorter than the distance from the point [PA] and the inductance value is small, the current increasing / decreasing speed is faster as shown in FIG.

実施の形態３．
ＰＷＭ駆動に伴うモータ電流の転流には、ＯＦＦからＯＮへ変化するターンＯＮと、ＯＮからＯＦＦへ変化するターンＯＦＦとの二通りがあるが、ＦＥＴドライバ３２への帰還電圧信号を引き出す点をこのターンＯＮ時とターンＯＦＦ時とで切り替えることにより、両方の電流の変化速度を独立に調整することができる。図７はその切り替える方法を示したものであって、ＦＥＴドライバ３２へ帰還する電圧信号を[ＰＡ]と[ＰＢ]との２点から引き出し、アナログスイッチ３８によりいずれかを選択してＦＥＴドライバ３２へ帰還する構成としている。なお、図７ではアナログスイッチ３８を機械式スイッチの記号を用いて模式的に記述しているが、半導体スイッチで構成される。このアナログスイッチ３８をＣＰＵ３４からのＰＷＭ駆動パルスに応じて選択動作させる事により、モータ電流の転流速度をターンＯＮ時とターンＯＦＦ時とで独立に調整することが可能となり、転流速度のきめ細かい調整が行なえるので、ノイズの抑制がより効果的となる。 Embodiment 3 FIG.
There are two types of motor current commutation associated with PWM drive: a turn-on that changes from OFF to ON, and a turn-off that changes from ON to OFF. By switching between the turn-on time and the turn-off time, the change rate of both currents can be adjusted independently. FIG. 7 shows the switching method. The voltage signal fed back to the FET driver 32 is extracted from two points, [PA] and [PB], and either one is selected by the analog switch 38 to select the FET driver 32. It is configured to return to. In FIG. 7, the analog switch 38 is schematically described using a mechanical switch symbol, but is configured by a semiconductor switch. By selectively operating the analog switch 38 in accordance with the PWM drive pulse from the CPU 34, the commutation speed of the motor current can be adjusted independently at turn-on and at turn-off, and the commutation speed is fine. Since adjustment can be performed, noise suppression is more effective.

実施の形態４．
Ｈブリッジ回路３１は、ＦＥＴで構成したが、図８に示すように、ＦＥＴをトランジスタに置き換えても同様に構成することができる。図８は実施の形態４のブリッジ回路３１４を示す回路構成図である。
トランジスタに置き換える場合は、トランジスタのエミッタが、ＦＥＴのソースに相当し、トランジスタのコレクタがＦＥＴのドレインに相当し、トランジスタのゲートがＦＥＴのゲートに相当する。そして、モータを制御するブリッジ回路を構成するトランジスタＴＲ３，ＴＲ４のエミッタに直列にインダクタンス素子３１１,３１２を挿入すると共に、前記インダクタンス素子３１１,３１２の反エミッタ端の電位を基準として、又は、前記インダクタンス素子の中間の電位を基準として、ブリッジ回路の制御電圧を加算してトランジスタのゲート駆動電圧を得るようにすればよい。 Embodiment 4 FIG.
Although the H-bridge circuit 31 is configured by an FET, as shown in FIG. 8, it can be configured in the same manner by replacing the FET with a transistor. FIG. 8 is a circuit configuration diagram showing the bridge circuit 314 of the fourth embodiment.
When replacing with a transistor, the emitter of the transistor corresponds to the source of the FET, the collector of the transistor corresponds to the drain of the FET, and the gate of the transistor corresponds to the gate of the FET. Then, inductance elements 311 and 312 are inserted in series with the emitters of the transistors TR3 and TR4 constituting the bridge circuit for controlling the motor, and the potential at the non-emitter end of the inductance elements 311 and 312 is used as a reference, or the inductance The gate drive voltage of the transistor may be obtained by adding the control voltage of the bridge circuit with reference to the intermediate potential of the element.

実施の形態５．
以上、補助力を発生するモータとしてＤＣモータを用い、これをＨブリッジ回路にて駆動する場合について述べたが、ブラシレスモータを用いてインバータ回路にて駆動する場合にもこの発明は同様に適応できる。図９は実施の形態５のインバータ回路３１５を示す回路構成図である。図において、５１−５６はインバータ回路３１５を構成する電界効果トランジスタ、３１６−３１８はコイル（インダクタンス素子）である。２１はブラシレス三相モータである。モータ２１を制御するインバータ回路３１５を構成する下段の電界効果トランジスタ５４，５５，５６のソースにそれぞれ直列にコイル（インダクタンス素子）３１６,３１７，３１８を挿入すると共に、前記コイル３１６,３１７，３１８の反ソース端の電位を基準として、又は、前記コイル３１６,３１７，３１８の中間の電位を基準として、インバータ回路３１５の制御電圧を加算して、電界効果トランジスタ５４，５５，５６のゲート駆動電圧を得るようにすればよい。 Embodiment 5 FIG.
As described above, the case where the DC motor is used as the motor for generating the auxiliary force and this is driven by the H bridge circuit has been described. However, the present invention can be similarly applied to the case where the brushless motor is driven by the inverter circuit. . FIG. 9 is a circuit configuration diagram showing the inverter circuit 315 of the fifth embodiment. In the figure, 51-56 are field effect transistors constituting the inverter circuit 315, and 316-318 are coils (inductance elements). 21 is a brushless three-phase motor. Coils (inductance elements) 316, 317, and 318 are inserted in series in the sources of the lower-stage field effect transistors 54, 55, and 56 constituting the inverter circuit 315 that controls the motor 21, and the coils 316, 317, and 318 are connected. The control voltage of the inverter circuit 315 is added on the basis of the potential at the non-source end or the intermediate potential of the coils 316, 317, 318, and the gate drive voltages of the field effect transistors 54, 55, 56 are obtained. You can get it.

この発明の実施の形態１による電動パワーステアリング装置を示す回路構成図である。It is a circuit block diagram which shows the electric power steering apparatus by Embodiment 1 of this invention. ＰＷＭ駆動されるブリッジ回路のＦＥＴのタイミングチャートである。It is a timing chart of FET of the bridge circuit driven by PWM. 実施の形態１におけるブリッジ回路を構成する４個のＦＥＴの駆動状態とモータの電流経路の関係を模式的に表した説明図である。FIG. 3 is an explanatory diagram schematically showing the relationship between the drive states of four FETs constituting the bridge circuit in Embodiment 1 and the current path of a motor. 実施の形態１におけるＰＷＭ駆動の1周期内の各部の動作の詳細を表すタイミングチャートである。3 is a timing chart illustrating details of operations of respective units within one cycle of PWM driving in the first embodiment. 実施の形態２に用いるプリント基板を示す構成図である。6 is a configuration diagram showing a printed circuit board used in Embodiment 2. FIG. 実施の形態２に用いるプリント基板の動作を説明するタイミングチャートである。6 is a timing chart for explaining the operation of the printed circuit board used in the second embodiment. 実施の形態３に用いるプリント基板を示す構成図である。6 is a configuration diagram showing a printed circuit board used in Embodiment 3. FIG. 実施の形態４のブリッジ回路を示す回路構成図である。FIG. 6 is a circuit configuration diagram illustrating a bridge circuit according to a fourth embodiment. 実施の形態５のインバータ回路を示す回路構成図である。FIG. 10 is a circuit configuration diagram illustrating an inverter circuit according to a fifth embodiment.

符号の説明Explanation of symbols

１ トルクセンサ ２ モータ
３ 制御装置 ４ バッテリ
２１ 三相モータ ３１ Ｈブリッジ回路
３２ ＦＥＴドライバ ３３ 電流検出回路
３４ ＣＰＵ ３５ チョークコイル
３６ コンデンサ ３７ シャント抵抗
５１−５６ 電界効果トランジスタ ３１１ コイル
３１２ コイル ３１４ ブリッジ回路
３１５ インバータ回路 ３１６−３１８ コイル
３４１ 目標電流設定ブロック ３４２ Ｄｕｔｙ比算出ブロック
３４３ パルス発生器 ３４４ Ａ／Ｄ変換器 DESCRIPTION OF SYMBOLS 1 Torque sensor 2 Motor 3 Control apparatus 4 Battery 21 Three-phase motor 31 H bridge circuit 32 FET driver 33 Current detection circuit 34 CPU 35 Choke coil 36 Capacitor 37 Shunt resistance 51-56 Field effect transistor 311 Coil 312 Coil 314 Bridge circuit 315 Inverter Circuit 316-318 Coil 341 Target current setting block 342 Duty ratio calculation block 343 Pulse generator 344 A / D converter

Claims (5)

自動車の運転者の操舵力を検出するトルクセンサと、運転者の操舵力を補助するモータと、電界効果トランジスタで構成されるブリッジ回路を有し前記モータを制御する制御装置とを備え、
前記トルクセンサで検出された運転者の操舵力に応じた電流を前記ブリッジ回路を制御して前記モータに通電することにより、運転者の操舵力を補助する電動パワーステアリング装置において、
前記モータを制御する前記ブリッジ回路を構成する電界効果トランジスタのソースに直列にインダクタンス素子を挿入すると共に、前記インダクタンス素子の反ソース端の電位を基準として、又は、前記インダクタンス素子の中間の電位を基準として、前記ブリッジ回路の制御電圧を加算して前記電界効果トランジスタのゲート駆動電圧を得るようにしたことを特徴とする電動パワーステアリング装置。 A torque sensor for detecting the steering force of the driver of the automobile, a motor for assisting the steering force of the driver, and a control device for controlling the motor having a bridge circuit composed of a field effect transistor,
In the electric power steering device that assists the steering force of the driver by controlling the bridge circuit and energizing the motor with a current corresponding to the steering force of the driver detected by the torque sensor,
An inductance element is inserted in series with the source of the field effect transistor that constitutes the bridge circuit that controls the motor, and the potential at the non-source end of the inductance element is used as a reference, or an intermediate potential of the inductance element is used as a reference. An electric power steering apparatus characterized in that the gate drive voltage of the field effect transistor is obtained by adding the control voltage of the bridge circuit. 前記インダクタンス素子のインダクタンスを前記ブリッジ回路が実装されたプリント基板の銅箔パターンで形成したことを特徴とする請求項１記載の電動パワーステアリング装置。   2. The electric power steering apparatus according to claim 1, wherein the inductance of the inductance element is formed by a copper foil pattern of a printed board on which the bridge circuit is mounted. 前記銅箔パターン上に前記電界効果トランジスタのゲート駆動電圧の基準とする電位を得る点を２箇所設け、前記電界効果トランジスタのオンとオフの駆動状態に応じて、この２箇所の基準電位のいずれか一方を選択するようにしたことを特徴とする請求項２記載の電動パワーステアリング装置。   Two points are provided on the copper foil pattern to obtain a potential as a reference for the gate drive voltage of the field effect transistor. 3. The electric power steering apparatus according to claim 2, wherein one of the two is selected. 自動車の運転者の操舵力を検出するトルクセンサと、運転者の操舵力を補助するモータと、トランジスタで構成されるブリッジ回路を有し前記モータを制御する制御装置とを備え、
前記トルクセンサで検出された運転者の操舵力に応じた電流を前記ブリッジ回路を制御して前記モータに通電することにより、運転者の操舵力を補助する電動パワーステアリング装置において、
前記モータを制御する前記ブリッジ回路を構成するトランジスタのエミッタに直列にインダクタンス素子を挿入すると共に、前記インダクタンス素子の反エミッタ端の電位を基準として、又は、前記インダクタンス素子の中間の電位を基準として、前記ブリッジ回路の制御電圧を加算して前記トランジスタのゲート駆動電圧を得るようにしたことを特徴とする電動パワーステアリング装置。 A torque sensor that detects the steering force of the driver of the automobile, a motor that assists the steering force of the driver, and a control device that has a bridge circuit composed of transistors and controls the motor;
In the electric power steering device that assists the steering force of the driver by controlling the bridge circuit and energizing the motor with a current corresponding to the steering force of the driver detected by the torque sensor,
Inserting an inductance element in series with the emitter of the transistor that constitutes the bridge circuit that controls the motor, and using the potential at the non-emitter end of the inductance element as a reference, or using the intermediate potential of the inductance element as a reference, An electric power steering apparatus characterized in that the gate drive voltage of the transistor is obtained by adding the control voltage of the bridge circuit. 自動車の運転者の操舵力を検出するトルクセンサと、運転者の操舵力を補助するモータと、電界効果トランジスタで構成されるインバータ回路を有し前記モータを制御する制御装置とを備え、
前記トルクセンサで検出された運転者の操舵力に応じた電流を前記インバータ回路を制御して前記モータに通電することにより、運転者の操舵力を補助する電動パワーステアリング装置において、
前記モータを制御する前記インバータ回路を構成する電界効果トランジスタのソースに直列にインダクタンス素子を挿入すると共に、前記インダクタンス素子の反ソース端の電位を基準として、又は、前記インダクタンス素子の中間の電位を基準として、前記インバータ回路の制御電圧を加算して前記電界効果トランジスタのゲート駆動電圧を得るようにしたことを特徴とする電動パワーステアリング装置。
A torque sensor that detects the steering force of the driver of the automobile, a motor that assists the steering force of the driver, and a control device that controls the motor having an inverter circuit composed of a field effect transistor;
In the electric power steering device that assists the steering force of the driver by controlling the inverter circuit and energizing the motor with a current corresponding to the steering force of the driver detected by the torque sensor,
An inductance element is inserted in series with the source of the field effect transistor that constitutes the inverter circuit that controls the motor, and the potential at the non-source end of the inductance element is used as a reference, or an intermediate potential of the inductance element is used as a reference. An electric power steering apparatus characterized in that the gate drive voltage of the field effect transistor is obtained by adding the control voltage of the inverter circuit.
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