JP2007305750A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the latch up of a semiconductor device having a parasitic thyristor. <P>SOLUTION: A channel region is formed having a width Y2 narrower than the width Y1 of a drain region 14 in a direction perpendicular to a direction crossing between a source region 17 and the drain region 14. This restricts only a current flowing on the channel to prevent the latch up without increasing the resistance value of the drain region 14. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a mask ROM.

  In recent years, a semiconductor device such as a mask ROM in which a diode is provided in a memory cell has been proposed.

  FIG. 6 is a cross-sectional view showing a part of a memory cell array of a semiconductor device according to the prior art.

  An n-type impurity region 14 is provided on the upper surface of the p-type silicon substrate 13.

  Here, a plurality of (eight) p-type impurity regions 15 are formed in the n-type impurity region 14 at a predetermined interval. One p-type impurity region 15 and n-type impurity region 14 form one diode 10. That is, eight diodes 10 are formed.

The n-type impurity region 14 is also used as the drain region of the selection transistor 11. Further, the source region 17 of the selection transistor 11 is formed on both sides of the n-type impurity region 14. Also, on the channel region between the n-type impurity region 14 and the source region 17 of the p-type silicon substrate 13. A gate electrode 19 is formed through the gate insulating film 18. The gate electrode 19 is formed integrally with the word line 7 made of a polysilicon film. Although not shown, a plurality of the word lines 7 are provided at a predetermined interval.

  A first interlayer insulating film 21 is provided on the upper surface of the p-type silicon substrate 13 so as to cover the gate electrode 19 (word line 7). A contact hole 22 is provided in a region corresponding to the p-type impurity region 15 and the source region 17 of the first interlayer insulating film 21. The contact hole 22 is filled with a first-layer plug 23 made of W (tungsten).

  On the first interlayer insulating film 21, a source line 12 made of Al and a first connection layer 24 are provided so as to be connected to the first plug 23. A second interlayer insulating film 25 is provided on the first interlayer insulating film 21 so as to cover the source line 12 and the first connecting layer 24. A contact hole 26 is formed in a region corresponding to the first connection layer 24 of the second interlayer insulating film 25. A second layer plug 27 made of W is embedded in the contact hole 26.

  A second connection layer 28 made of Al is provided on the second interlayer insulating film 25 so as to be connected to the second plug 27. A third interlayer insulating film 29 is provided on the second interlayer insulating film 25 so as to cover the second connection layer 28. The third interlayer insulating film 29 is provided with a contact hole 30, and a third layer plug 31 made of W is embedded in the contact hole 30. The third layer plug 31 is connected to the second connection layer 28. On the third interlayer insulating film 29, a plurality of bit lines 8 made of Al are provided at a predetermined interval. The bit line 8 is connected to the plug 31 in the third layer. A contact hole 30 is provided in the third interlayer insulating film 29, and data “0” depends on whether the bit line 8 is connected to the second connection layer 28 via the third plug 31. "Or" 1 "is stored.

As related technical literatures, for example, the following patent literatures can be cited.
JP 2005-268370 A

  As shown in FIG. 7, the semiconductor device includes a parasitic pnp transistor having a p-type impurity region 15 as an emitter, an n-type impurity region 14 as a base, and a p-type silicon substrate 13 as a collector, and a source region 17 as an emitter. There is a parasitic thyristor composed of an npn transistor having a p-type silicon substrate 13 as a base and an n-type impurity region 14 as a collector. Here, in the semiconductor device described above, eight p-type impurity regions 15 are formed in the n-type impurity region 14, so that a sufficient current is supplied to all the p-type impurity regions 15 in the n-type impurity region having a large resistance value. A large potential is applied between the n-type impurity region 14 and the source region 17 so as to flow. However, in this case, since the current flowing in the channel region of the select transistor 11 increases, the potential in the vicinity of the channel region increases, and this thyristor may be turned on. In this case, there is a possibility of a latch-up state, and the operating current increases.

  In view of the above, a semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate insulating film, and a first surface formed on the main surface of the semiconductor substrate. A source region and a drain region of two conductivity types, and a plurality of first conductivity type impurity regions formed at predetermined intervals on the surface of the drain region, and straddling the source region and the drain region The width of the channel region is narrower than that of the drain region.

  Preferably, the drain region is formed longer than the source region in a direction straddling the source region and the drain region.

  Preferably, the gate electrode functions as a word line, and the impurity regions are connected to different bit lines.

  In the semiconductor device according to the present invention, the current flowing through the channel region can be reduced. For this reason, it is possible to suppress the potential in the vicinity of the channel region from increasing and to prevent the occurrence of latch-up.

  Further, the above technical effect can be obtained without increasing the resistance value of the drain region.

  In addition, a high-performance memory can be obtained.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram of a semiconductor device according to the present invention.

  The semiconductor device according to this embodiment includes an address input circuit 1, a row decoder 2, a column decoder 3, a sense amplifier 4, an output circuit 5, and a memory cell array 6. The address input circuit 1, the row decoder 2, the column decoder 3, the sense amplifier 4 and the output circuit 5 constitute a peripheral circuit. The address input circuit 1 is configured to output address data to the row decoder 2 and the column decoder 3 when a predetermined address is input from the outside. A plurality of word lines (WL) 7 are connected to the row decoder 2. The row decoder 2 receives the address data from the address input circuit 1 and selects the word line 7 corresponding to the input address data, and raises the potential of the selected word line 7 to the H level. A plurality of bit lines (BL) 8 are connected to the column decoder 3. The column decoder 3 receives the address data from the address input circuit 1 and selects the bit line 8 corresponding to the input address data, and connects the selected bit line 8 and the sense amplifier 4. The sense amplifier 4 discriminates and amplifies the potential of the bit line 8 selected by the column decoder 3 and then outputs an H level signal when the potential of the selected bit line 8 is L level. When the potential of the selected bit line 8 is H level, an L level signal is output. The sense amplifier 4 includes a load circuit (not shown) that raises the potential of the bit line 8 to H level when the potential of the selected bit line 8 is not L level. The output circuit 5 is configured to output a signal to the outside when the output of the sense amplifier 4 is input.

  In the memory cell array 6, a plurality of memory cells 9 are arranged in a matrix. Each memory cell 9 includes one diode 10. The memory cell array 6 includes a memory cell 9 including a diode 10 whose anode is connected to the bit line 8 and a memory cell 9 including a diode 10 whose anode is not connected to the bit line 8. Depending on whether or not the anode of the diode 10 is connected to the bit line 8, the data stored in the memory cell 9 is distinguished as "0" or "1". The cathode of the diode 10 is connected to the drain of the selection transistor 11 made of an n-channel transistor. The source of the selection transistor 11 is grounded via a source line (GND line) 12, and the gate is connected to the word line 7.

  FIG. 2 is a plan layout showing the configuration of the memory cell array of the semiconductor device according to the present invention. FIG. 3 is a cross-sectional view taken along line 100-100 in FIG.

  In the memory cell array 6, a plurality of n-type impurity regions 14 are provided on the upper surface of the p-type silicon substrate 13 at a predetermined interval. The n-type impurity region 14 includes an n-type low-concentration impurity region 14a and an n-type impurity region 14b formed deeper than the impurity region 14a. Here, the impurity region 14b has a slightly higher impurity concentration than the impurity region 14a.

  A plurality (eight) of p-type impurity regions 15 are formed in one n-type impurity region 14 at a predetermined interval. A diode 10 is formed by one p-type impurity region 15 and n-type impurity region 14. Thereby, the n-type impurity region 14 is used as a common cathode of the plurality of diodes 10. The p-type impurity region 15 is used as an anode of the diode 10. Here, a plurality (eight) of diodes 10 are formed in the n-type impurity region 14. That is, one n-type impurity region 14 is commonly used for a plurality (eight) of diodes 10.

  The n-type impurity region 14 is also used as the drain region of the selection transistor 11. On both sides of the n-type impurity region 14, the source region 17 of the selection transistor 11 is formed at a predetermined interval. The source region 17 includes an n-type low concentration impurity region 17a and an n-type high concentration impurity region 17b. Here, the n-type low concentration impurity region 17 a is formed in a relatively shallow region from the surface of the p-type silicon substrate 13. On the other hand, the n-type high concentration impurity region 17b is formed to a region deeper than the n-type low concentration impurity region 17a. Further, an n-type contact region 17 c is formed in the source region 17. The n-type contact region 17c is provided in order to reduce contact resistance when connecting a first-layer plug 23 described later to the source region 17.

  Further, the n-type low concentration impurity region 17a of the source region 17 and the impurity region 14a of the n-type impurity region 14 have the same impurity concentration. On the other hand, the n-type high concentration impurity region 17 b of the source region 17 has a higher impurity concentration than the impurity region 14 b of the n-type impurity region 14. Further, the adjacent n-type impurity regions 14 are arranged at predetermined intervals from the common source region 17 of the two select transistors 11. That is, the n-type impurity region 14 is divided at regions corresponding to the two select transistors 11 of the p-type silicon substrate 13.

  A gate electrode 19 is formed on the channel region between the n-type impurity region 14 and the source region 17 of the p-type silicon substrate 13 via a gate insulating film 18. The gate electrode 19 is formed integrally with the word line 7 made of a polysilicon film. A plurality of word lines 7 are provided at a predetermined interval. Further, the gate electrode 19 is formed by bending a part of the word line 7 and intersects obliquely with respect to the extending direction of the n-type impurity region 14.

  Further, side wall spacers 20 made of an insulating film are provided on both sides of the gate electrode 19. A first interlayer insulating film 21 is provided on the upper surface of the p-type silicon substrate 13 so as to cover the gate electrode 19 (word line 7) and the sidewall spacer 20. A contact hole 22 is provided in a region corresponding to the p-type impurity region 15 and the n-type contact region 17 c of the first interlayer insulating film 21. The contact hole 22 is filled with a first-layer plug 23 made of W (tungsten). Thereby, the plug 23 is connected to the p-type impurity region 15 and the n-type contact region 17c.

  On the first interlayer insulating film 21, a source line 12 made of Al and a first connection layer 24 are provided so as to be connected to the first plug 23. A second interlayer insulating film 25 is provided on the first interlayer insulating film 21 so as to cover the source line 12 and the first connecting layer 24. A contact hole 26 is formed in a region corresponding to the first connection layer 24 of the second interlayer insulating film 25. A second layer plug 27 made of W is embedded in the contact hole 26.

  A second connection layer 28 made of Al is provided on the second interlayer insulating film 25 so as to be connected to the second plug 27. A third interlayer insulating film 29 is provided on the second interlayer insulating film 25 so as to cover the second connection layer 28. The third interlayer insulating film 29 is provided with a contact hole 30, and a third layer plug 31 made of W is embedded in the contact hole 30. The third layer plug 31 is connected to the second connection layer 28. On the third interlayer insulating film 29, a plurality of bit lines 8 made of Al are provided at a predetermined interval. The bit line 8 is connected to the plug 31 in the third layer. The third-layer plug 31 is provided between the bit-line 31 and the second-layer connection layer 28 connected to the predetermined p-type impurity region 15 (the anode of the diode 10). It is not provided between the second connection layer 28 connected to the type impurity region 15 (the anode of the diode 10) and the bit line 31. Thereby, the diode 10 whose anode is connected to the bit line 31 and the diode 10 whose anode is not connected to the bit line 31 are configured. That is, data “0” or “1” is stored depending on whether or not the contact hole 30 is provided in the third interlayer insulating film 29.

  FIG. 4 is an enlarged plan view showing a region A in FIG. The n-type impurity region 14 has a width Y1 in a direction orthogonal to the direction between the n-type impurity region 14 and the source region 17 so that a sufficient current flows from each diode 10. It is formed to have a low value. However, even if the width Y1 is wide, the resistance value of the n-type impurity region 14 is larger than the resistance value of the metal wiring or the like. In addition, since the eight diodes 10 are formed in the n-type impurity region 14, the n-type impurity region 14 is formed longer than the source region 17. Therefore, a large potential difference is required between the word line 7 and the bit line 8 in order for sufficient current to flow from each diode 10.

  However, as shown in FIG. 5, in the semiconductor device according to the present invention, a parasitic pnp transistor having a p-type impurity region 15 as an emitter, an impurity region 14b as a base, and a p-type silicon substrate 13 as a collector, and an n-type high concentration There is a parasitic thyristor composed of an npn transistor having the impurity region 17b as an emitter, the p-type silicon substrate 13 as a base, and the impurity region 14b as a collector. Therefore, when the current flowing in the channel region of the select transistor 11 increases, the potential in the vicinity of the channel region increases, and this thyristor may be turned on. In this case, there is a possibility of a latch-up state, and the operating current increases.

  However, if the width Y1 is narrowed to prevent latch-up, sufficient current will not flow from each diode 10 to the n-type impurity region 14 as described above. Therefore, in the semiconductor device according to the present invention, only the width Y2 (the width between the virtual lines 32) of the n-type impurity region 14 in the vicinity of the gate electrode 19 is made smaller than the width Y1. In this case, the channel width of each MOS transistor is equal to the width Y2. That is, an increase in the resistance value of the n-type impurity region 14 can be minimized, and the current flowing through the channel region of the selection transistor 11 can be reduced. Therefore, the potential of the p-type silicon substrate 13 can be prevented from rising and latch-up can be prevented from occurring.

  The word line 7 and the gate electrode 19 are formed with a large width in order to reduce the resistance value. In this case, since the distance between the plug 23 in the first layer and the gate electrode 19 is small, interference may occur. Therefore, in the semiconductor device according to the present invention, the gate electrode 19 is bent so that the minimum distance X1 between the gate electrode 19 and the first-layer plug 23 satisfies a reference distance that does not cause interference. In the semiconductor device according to the present embodiment, the gate electrode 19 is bent on both sides of the source region 17 side and the n-type impurity region 14 side. However, the distance between the gate electrode 19 and the first-layer plug 23 may be different between the source region 17 side and the n-type impurity region 14 side. In this case, the gate electrode 19 does not need to be bent on both sides, and may be bent only on the side where X1 is equal to or less than the reference distance.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiment but by the scope of claims for patent, and all modifications within the meaning and scope equivalent to the scope of claims for patent are included.

  For example, in the present embodiment, an example in which the present invention is applied to a mask ROM has been described. However, the present invention is not limited to this and can be applied to memories other than the mask ROM.

  In the present embodiment, a plurality of n-type impurity regions are isolated by a LOCOS film as an element isolation region. However, the present invention is not limited to this, and STI (Shallow Trench Isolation) and other element isolation methods are used. A plurality of n-type impurity regions may be separated by.

  In this embodiment, the case where the gate electrode 19 (word line 7) is a polysilicon layer has been described. However, a tungsten polycide layer, a tantalum polycide layer, a molybdenum polycide layer, or the like may be used.

  In this embodiment, the sense amplifier outputs an H level signal when a current higher than a predetermined current flows through the selected bit line, and a current less than the predetermined current flows through the selected bit line. However, the present invention is not limited to this, and the sense amplifier outputs an L level signal when a current higher than a predetermined current flows through the selected bit line. In addition, an H level signal may be output when a current less than a predetermined current flows through the selected bit line.

  In the present embodiment, the case where the width of the n-type impurity region 14 and the width of the source region 17 are the same has been described. However, since the source region 17 is shorter than the n-type impurity region 14, the resistance value of the source region 17 does not need to be as small as that of the n-type impurity region 14. Therefore, the width of the source region 17 may be narrower than that of the n-type impurity region 14.

1 shows a circuit diagram according to an embodiment of the present invention. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Sectional drawing of the semiconductor device which concerns on a prior art is shown. Sectional drawing of the semiconductor device which concerns on a prior art is shown.

Explanation of symbols

1 address input circuit 2 row decoder 3 column decoder 4 sense amplifier 5 output circuit 6 memory cell array 7 word line 8 bit line 9 memory cell 10 diode 11 selection transistor 12 source line (GND line)
13 p-type silicon substrate (semiconductor substrate)
14 n-type impurity region (first impurity region)
15 p-type impurity region 17 source region (second impurity region)
17c n-type contact region 18 gate insulating film 19 gate electrode 20 sidewall spacer 21 first layer interlayer insulating film 22 first layer contact hole 23 first layer plug 24 first layer connection layer 25 second layer interlayer Insulating film 26 Second layer contact hole 27 Second layer plug 28 Second layer connection layer 29 Third layer interlayer insulating film 30 Third layer contact hole 31 Third layer plug 32 Virtual line

Claims (3)

A first conductivity type semiconductor substrate;
A gate electrode formed on the semiconductor substrate via a gate insulating film;
A source region and a drain region of a second conductivity type formed on the main surface of the semiconductor substrate;
A plurality of first conductivity type impurity regions formed at predetermined intervals on the surface of the drain region,
A semiconductor device, wherein a width of a channel region is narrower than a width of the drain region in a direction orthogonal to a direction straddling the source region and the drain region. In the direction straddling the source region and the drain region,
The semiconductor device according to claim 1, wherein the drain region is formed longer than the source region. The gate electrode functions as a word line,
The semiconductor device according to claim 1, wherein the impurity regions are connected to different bit lines.