CN114280863B - Array substrate and display panel - Google Patents
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- CN114280863B CN114280863B CN202111554972.1A CN202111554972A CN114280863B CN 114280863 B CN114280863 B CN 114280863B CN 202111554972 A CN202111554972 A CN 202111554972A CN 114280863 B CN114280863 B CN 114280863B
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Abstract
The application relates to an array substrate and a display panel. The array substrate includes: the display device comprises a substrate, a first metal layer positioned on one side of the substrate and a second metal layer positioned on one side of the first metal layer away from the substrate, wherein the first metal layer is used for setting a clock signal line, the second metal layer is used for setting a grid line, the clock signal line and the grid line are overlapped, the grid line at the overlapped position spans the clock signal line, the orthographic projection width of the grid line at the overlapped position on the substrate is a first width, and the orthographic projection width of the grid line at the non-overlapped position on the substrate is a second width; the first width is larger than or equal to the second width, so that when the grid line is formed by deposition, the occurrence of uneven resistance values of all positions of the grid line caused by metal sinking is reduced, the resistance values of all positions of the grid line are relatively uniform, current at the crossing position cannot jump, the crossing position is prevented from being burst, and the display effect of the display panel is greatly improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display panel.
Background
With the development of display technology, a liquid crystal display (Liquid Crystal Display, abbreviated as LCD) is widely used in various consumer electronic products, and becomes a mainstream in display devices.
The thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-LCD for short) has the characteristics of small volume, low power consumption, no radiation and the like, and is dominant in all liquid crystal displays, and consumers have higher requirements on the liquid crystal display.
The high-frequency GOA (Gate driver On Array, i.e. the gate lines are arranged on the array substrate) is a gate line climbing clock signal line, and the line width of the gate lines at the climbing position is smaller than that of the gate lines at other positions due to the sinking effect generated after the gate lines are deposited at the climbing position. Therefore, the resistance of the gate line is gradually changed, and the current values of different sections are suddenly changed, if the inorganic film layer between the gate line and the clock signal line is poor in film quality, the electrode is easy to be burst at the line crossing position, the electrode breaks down the inorganic film, so that short circuit occurs between the gate line and the clock signal line, and the display effect of the product is greatly affected.
Disclosure of Invention
The application aims to provide an array substrate and a display panel, wherein the array substrate comprises a plurality of clock signal lines and a plurality of grid lines which are overlapped, and the orthographic projection width of the grid lines at the overlapped position on a substrate is larger than or equal to the orthographic projection width of the grid lines at the non-overlapped position on the substrate, so that the occurrence of explosive injury at the line crossing position can be prevented, and the visual effect of a product is improved.
In a first aspect, an embodiment of the present application proposes an array substrate, a first metal layer located at a side of the substrate, and a second metal layer located at a side of the first metal layer away from the substrate, where the first metal layer is used for setting a clock signal line, the second metal layer is used for setting a gate line, the clock signal line and the gate line are overlapped, the gate line at the overlapped position spans the clock signal line, a width of orthographic projection of the gate line at the overlapped position on the substrate is a first width, and a width of orthographic projection of the gate line at a non-overlapped position on the substrate is a second width; wherein the first width is greater than or equal to the second width.
In one alternative of the present application, the first width and the second width have a first difference, the first difference being greater than or equal to 1 μm and less than or equal to 3 μm.
In one alternative of the present application, the first width is greater than or equal to 12 μm and less than or equal to 13 μm, and the second width is greater than or equal to 10 μm and less than or equal to 11 μm.
In one alternative of the present application, the on-state voltage of the gate line at the overlap and the off-state voltage of the clock signal line at the overlap have a second difference value, which is greater than or equal to 12 μm and less than or equal to 35V.
In an alternative scheme of the present application, the on-state voltage of the gate line at the overlapping position is greater than or equal to 5V and less than or equal to 15V, and the off-state voltage of the clock signal line at the overlapping position is greater than or equal to-20V and less than or equal to-15V.
In an alternative scheme of the application, each signal input end of the gate line is provided with a layer transfer hole, and the layer transfer hole is connected with an electrostatic discharge piece.
In an alternative aspect of the present application, the electrostatic discharge member includes an electrostatic ring and an electrostatic discharge wire, and the electrostatic ring is connected to the lamination hole and the electrostatic discharge wire, respectively.
In one alternative of the present application, the electrostatic ring includes a first thin film transistor and a second thin film transistor; the grid electrode and the source electrode of the first thin film transistor are simultaneously connected to the grid electrode line, and the drain electrode of the first thin film transistor is connected to the electrostatic discharge wire; the grid electrode and the source electrode of the second thin film transistor are connected to the static electricity discharge wire, and the drain electrode is connected to the grid line.
In an alternative scheme of the application, the clock signal lines include a plurality of clock signal lines, and the plurality of clock signal lines are arranged on the first metal layer at intervals along a first direction; the grid lines comprise a plurality of grid lines which are arranged on the second metal layer at intervals along the second direction; the first direction and the second direction are perpendicular to each other.
In a second aspect, embodiments of the present application further provide a color film substrate and the array substrate of any one of the first aspect, where a liquid crystal layer is disposed between the color film substrate and the array substrate.
According to the array substrate and the display panel provided by the embodiment of the application, the array substrate comprises the substrate, the first metal layer and the second metal layer are sequentially deposited on the substrate, the first metal layer is used for setting the clock signal line, the second metal layer is used for setting the gate line, the gate line spans the clock signal line at the overlapping position of the gate line and the clock signal line, and the first line width of the gate line spanning the clock signal line is set to be larger than the second line width of the gate line at other positions, so that when the gate line is deposited, the condition that the resistance of each position of the gate line is uneven due to metal sinking is reduced, the resistance of each position of the gate line is relatively uniform, the current at the crossing position is not jumped, the explosion at the crossing position is prevented, and the display effect of the display panel is greatly improved.
Drawings
Features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are designated with like reference numerals. The drawings are not drawn to scale, but are merely for illustrating relative positional relationships, and the layer thicknesses of certain portions are exaggerated in order to facilitate understanding, and the layer thicknesses in the drawings do not represent the actual layer thickness relationships.
FIG. 1 is a top plan view of an array substrate provided herein;
fig. 2 shows a top plan view of an array substrate at a clock signal line and a gate line crossing provided in a first embodiment of the present application;
FIG. 3 is a cross-sectional view of FIG. 2;
fig. 4 shows a cross-sectional view of an array substrate at a clock signal line and a gate line crossing line according to a second embodiment of the present application;
fig. 5 is a plan view showing a clock signal line and a gate line crossing of an array substrate according to a third embodiment of the present disclosure;
fig. 6 shows a cross-sectional view of a display device according to a fourth embodiment of the present application.
Reference numerals illustrate:
100. an array substrate; 200. a backlight module; 300. a color film substrate; 400. a liquid crystal layer;
10. a GOA line;
1. a substrate; 2. a first metal layer; 21. a clock signal line; 3. a second metal layer; 31. a gate line; 4. an insulating layer; 5. a protective layer; 6. a layer-turning hole; 7. an electrostatic ring; 8. a printed circuit board; 9. and (3) a flip chip film.
Detailed Description
Features and exemplary embodiments of various aspects of the present application are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing an example of the present application. In the drawings and the following description, at least some well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The directional terms appearing in the following description are all directions shown in the drawings and do not limit the specific structure of the present application. In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected. The specific meaning of the terms in the present application can be understood as appropriate by one of ordinary skill in the art.
First embodiment
FIG. 1 is a top plan view of an array substrate provided herein; fig. 2 shows a top plan view of an array substrate at a clock signal line and a gate line crossing provided in a first embodiment of the present application; fig. 3 is a cross-sectional view of fig. 2.
Referring to fig. 1-3, an array substrate is provided, in which a GOA line 10 is connected to a printed circuit board 8 through a flip-chip film 9 to input a clock signal to a clock signal line 21 and electrically connected to a gate line 31. Specifically, the array substrate comprises a substrate 1, a first metal layer 2 positioned on one side of the array substrate 1, and a second metal layer 3 positioned on one side of the first metal layer 2 away from the substrate 1, wherein the first metal layer 2 is used for arranging a clock signal line 21, the second metal layer 3 is used for arranging a gate line 31, the clock signal line 21 and the gate line 31 are overlapped, and the gate line 31 at the overlapped part spans the clock signal line 21.
As a reference ground, an input terminal of the clock signal line 21 is connected to a flip Chip Film 9 (Chip On Flex, or Chip On Film, COF) On a printed circuit board 8 (Printed Circuit Board, abbreviated as PCB), and an output terminal of the clock signal line 21 is connected to the gate line 31 in a layer-by-layer manner for inputting a clock signal to the gate line 31.
Alternatively, the substrate 1 may be made of glass, or Polyimide (PI for short). Specifically, the glass substrate 1 is a thin glass sheet with an extremely flat surface, and the production method mainly comprises three methods: float, overflow downdraw, and slot downdraw. In addition, polyimide includes two types, namely, a benzene type polyimide film and a biphenyl type polyimide film, and is formed by casting a polyamide acid solution, stretching, and aminating with high Wen Xianya. The present application describes an array substrate using a glass substrate 1 as an example.
In some embodiments, the clock signal lines 21 include a plurality of clock signal lines 21, and the plurality of clock signal lines 21 are arranged on the first metal layer 2 at intervals along the first direction; the gate lines 31 include a plurality of gate lines 31 arranged on the second metal layer 3 at intervals along the second direction; the first direction and the second direction are perpendicular to each other, and thus the plurality of clock signal lines 21 and the plurality of gate lines 31 together form a grid shape.
For the sake of completeness of the solution, an insulating layer 4 is arranged between the first metal layer 2 and the second metal layer 3, and a protective layer 5 is arranged on the side of the second metal layer 3 remote from the first metal layer 2. The insulating layer 4 and the protective layer 5 are both inorganic film layers.
Specifically, the insulating layer 4 is made of a GI material including silicon nitride (SiNx), silicon oxide (SiOx), or other suitable dielectric material. For example, the GI material may be composed of a single layer of dielectric material or a stack of layers of dielectric material stacked on top of each other, such as a stack of silicon nitride/silicon oxide (SiNx/SiOx). In addition, the GI material may be an organic dielectric material (organic dielectric layer) or an organic-inorganic composite dielectric layer (organic-inorganic hybrid dielectric layer). The protective layer 5 is made of a PV material including silicon nitride (SiNx), silicon oxide (SiOx) or other suitable dielectric material. For example, the protective layer 5PV may be composed of a single layer of dielectric material, or of multiple layers of dielectric material stacked on top of each other, such as a stack of silicon nitride/silicon oxide (SiNx/SiOx). In addition, the material of the protective layer 5PV is, for example, an organic dielectric material (organic dielectric layer) or an organic-inorganic composite dielectric layer (organic-inorganic hybrid dielectric layer).
In addition, the embodiment of the application also provides a display panel based on the array substrate. The display panel is a liquid crystal display panel, and in particular, the display panel is a thin film transistor liquid crystal display panel. In the tft-lcd, the crossing mode of the gate line 31 and the clock signal line 21 is that the gate line 31 climbs the clock signal line 21, and the line width of the gate line 31 at the climbing position is smaller than the line width of the gate line 31 at other positions due to the sinking effect generated after the gate line 31 is deposited. Therefore, the resistance of the gate line 31 will gradually change, and the current values of different segments will be suddenly changed, so that if the inorganic film layer between the gate line 31 and the clock signal line 21 is poor in film quality, a burst is easily generated at the crossing position, and the electrode breaks down the inorganic film, resulting in a short circuit between the gate line 31 and the clock signal line 21, which greatly affects the display effect of the product.
For this purpose, the width of the orthographic projection of the gate line 31 on the array substrate at the overlapping is a first width D 1 The width of the orthographic projection of the gate line 31 at other positions on the array substrate is the second width D 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein D is 1 ≥D 2 。
The array substrate provided in this embodiment of the present application includes a substrate 1, a first metal layer 2 and a second metal layer 3 are sequentially deposited on the substrate 1, the first metal layer 2 is used for setting a clock signal line 21, the second metal layer 3 is used for setting a gate line 31, the gate line 31 spans the clock signal line 21 at a position where the gate line 31 and the clock signal line 21 overlap, and a first line width D of the gate line 31 spans the clock signal line 21 1 Second line width D of gate line 31 set to be larger than other positions 2 Therefore, when the grid line 31 is deposited, the occurrence of uneven resistance of each position of the grid line 31 caused by metal sinking is reduced, the resistance of each position of the grid line 31 is relatively uniform, and the current at the crossing line cannot jump, so that the explosion at the crossing line is prevented, and the display effect of the display panel is greatly improved.
As an example, the first width D 1 And the second width D 2 With a first difference Δd, Δd=d 1 -D 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the delta D is more than or equal to 1 μm and less than or equal to 3 μm. Specifically, 12 μm.ltoreq.D 1 ≤13μm，10μm≤D 2 ≤11μm。
In order to make the resistance value of the whole gate line 31 the same, the width of the gate line 31 is 10 μm-11 μm, the gate line 31 should be widened across the clock signal line 21 before depositing the gate line 31, and the first width D can be ensured even if the gate line 31 is sunk 1 And a second width D 2 The widths of the gate lines 31 are the same, so that the same resistance value of the whole gate line 31 is ensured, current is prevented from jumping at the overline position, the problems of electrode breakdown of the insulating layer 4 and explosion are avoided, and the display effect of the display panel is improved.
In addition, in order to ensure that the resistance of the gate line 31 at the overlapping position is consistent with the resistance of the gate line 31 at the non-overlapping position, other schemes may be adopted:
scheme one: the thickness of the gate line 31 at the overlapping portion is a first thickness, and the thickness of the gate line 31 at the non-overlapping portion is a second thickness, the first thickness being greater than the second thickness, such that the resistance of the gate line 31 at the overlapping portion is greater than the resistance of the gate line 31 at the non-overlapping portion, thereby causing the resistance of the gate line 31 at the overlapping portion per unit length and the resistance of the gate line 31 at the non-overlapping portion per unit length to be consistent after the metal of the gate line 31 at the overlapping portion is submerged.
Scheme II: the gate line 31 at the overlapping portion may be provided in a curved shape, the gate line 31 at the non-overlapping portion may be provided in a linear shape, and the area occupied by the gate line 31 at the overlapping portion in a unit length is larger than the area occupied by the gate line 31 at the non-overlapping portion in a unit length, so that the resistance value of the gate line 31 at the overlapping portion is larger than the resistance value of the gate line 31 at the non-overlapping portion, and thus, after the metal of the gate line 31 at the overlapping portion sinks, the resistance value of the gate line 31 at the overlapping portion in a unit length and the resistance value of the gate line 31 at the non-overlapping portion in a unit length are made to be uniform.
Second embodiment
Fig. 4 is a cross-sectional view of an array substrate according to a second embodiment of the present disclosure, please refer to fig. 4, at a crossing of a clock line and a gate line.
Since the gate lines 31 are opened row by row, when the first gate line 31 is opened, the voltage applied to the first gate line 31 is a high voltage, the voltage value is 25V-35V, when the second gate line 31 is opened, the first gate line 31 is in a closed state, the voltage applied to the first gate line 31 becomes a low voltage, the voltage value is-5V-14V, the on-state voltage and the off-state voltage of the same gate line 31 have a larger voltage difference due to timing problem, the difference is 30V-40V, and after long-time operation, the electrode breaks through the insulating layer 4, resulting in the occurrence of a blast.
In view of the above, as shown in fig. 4, in order to prevent the occurrence of a burst, the gate line 31 at the overlapping portion has an on-state voltage V GH The off-state voltage of the clock signal line 21 at the overlapping position is V GL With a second difference DeltaV, deltaV=V GH -V GL The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the delta V is more than or equal to 30V and less than or equal to 35V. Specifically, the gate line 31 at the overlapping position has an on-state voltage of V GH The off-state voltage of the clock signal line 21 at the overlapping position is V GL The method comprises the steps of carrying out a first treatment on the surface of the Wherein V is not less than 5V GH ≤15V，-20V≤V GL ≤-15V。
When the input voltage is set, a large voltage difference existing between the on-state voltage of the gate line 31 and the off-state voltage of the clock signal line 21 at the overlapping position is reduced, so that the electrode breakdown insulating layer 4 is prevented from being scratched.
In addition, in other schemes, when the other gate line 31 is turned on, the voltage of the gate line 31 at the overlapping position becomes the off-state voltage, the voltage of the clock signal line at the overlapping position becomes the on-state voltage, and by reducing the voltage difference between the on-state voltage and the off-state voltage, the electrode breakdown insulating layer 4 can be prevented from being damaged.
Third embodiment
Fig. 5 is a plan view illustrating a clock signal line and a gate line crossing of an array substrate according to a third embodiment of the present disclosure, and please refer to fig. 5.
Based on the first embodiment, the present embodiment provides an array substrate, which specifically includes eight clock input signals and eight Gate lines 31, gate1, gate2, gate3, gate4, gate5, gate6, gate7, and Gate8 respectively represent eight Gate lines 31, CK1, CK2, CK3, CK4, CK5, CK6, CK7, and CK8 respectively represent eight clock input signals, and each clock input signal functions to provide signals and voltages to the Gate line 31. Specifically, each clock input signal is transferred to the signal input end of the gate line 31, the signal input end is provided with a transfer hole 6, and the electrostatic discharge member is connected to the transfer hole 6.
Through increasing and setting up layer hole 6 at the signal input part that every gate line 31 corresponds to add the static electricity discharge piece on layer hole 6, under the condition of not increasing the cost, the static electricity that discharges the heavy current and produce when clock signal switches to gate line 31, prevent to flow in gate line 31 and clock signal line 21 too big, avoid the cross line position of gate line 31 and clock signal line 21 to fry and hinder, further promote the display effect.
In some embodiments, the electrostatic discharge member comprises an electrostatic ring 7 and an electrostatic discharge wire, and the electrostatic ring 7 is connected to the lamination hole 6 and the electrostatic discharge wire, respectively. The electrostatic ring 7 comprises at least two thin film transistors. As an example, the electrostatic ring 7 includes a first thin film transistor and a second thin film transistor; the grid electrode and the source electrode of the first thin film transistor are simultaneously connected to the grid electrode line 31, and the drain electrode is connected to an electrostatic discharge wire; the gate and source electrodes of the second thin film transistor are connected to the electrostatic discharge wire, the drain electrode is connected to the gate line 31, and the electrostatic discharge wire extends to the chip soft film press-connection part of the array substrate so as to be connected with a power supply end.
The gate and source of the first thin film transistor in the electrostatic ring 7 are connected to the gate line 31 at the same time, and the drain is connected to the electrostatic discharge wire. When the gate line 31 is at a high potential, the gate and the source of the first thin film transistor are both at a high potential, the first thin film transistor is turned on, and the high potential on the gate line 31 is transmitted to the electrostatic discharge wire. The grid electrode and the source electrode of the second thin film transistor are simultaneously connected to the electrostatic discharge wire, and the drain electrode of the second thin film transistor is connected to the grid line. In this connection, when the electrostatic discharge wire is at a high potential, the gate and source of the second thin film transistor are at a high potential, the second thin film transistor is turned on, the high potential of the source thereof (i.e., the high potential of the electrostatic discharge wire) is introduced to the drain thereof and the gate line 31 connected to the drain thereof is at a high potential, and the high potential of the gate line 31 can turn on the gates of the row entirely.
Since the layer-turning holes 6 of each gate line are connected with one electrostatic ring 7, all the electrostatic rings 7 are driven by the current on the electrostatic discharge lead, so that the gate lines 31 of each row control the gates on the array substrate to be opened all at the same time. Because the polarities of the adjacent pixel electrodes are opposite, the charges on the same signal line pixel can be neutralized, and the effect of discharging current can be realized.
It will be appreciated by those skilled in the art that this example only shows one basic connection of two thin film transistors to form the electrostatic ring 7, which is not the only embodiment of the present invention. Specifically, on the basis of the basic connection mode, one or more thin film transistors can be further connected to a certain end (gate, source or drain) of the existing thin film transistor, and the switching characteristic of the thin film transistor is utilized to further control the electric potential in the circuit, so that high-potential energy can be better transferred between the correspondingly connected gate line 31 and the electrostatic discharge wire.
Fourth embodiment
Fig. 6 is a cross-sectional view of a display device according to a fourth embodiment of the present application, please refer to fig. 6.
In addition to at least one of the first embodiment, the second embodiment and the third embodiment, the embodiment of the present application provides a display device, which includes a display panel and a backlight module 200, where the backlight module 200 is located on a backlight side of the display panel and is used for providing a light source for the display panel. The display panel includes a color film substrate 300 and the array substrate 100 according to any of the foregoing embodiments, the backlight module 200 is located at a backlight side of the array substrate 100, the color film substrate 300 is located at a side of the array substrate 100 away from the backlight module 200, and a liquid crystal layer 400 is disposed between the array substrate 100 and the color film substrate 300. The periphery of the array substrate 100 is arranged with GOA lines 10.
It should be readily understood that the terms "on … …", "above … …" and "above … …" in this application should be interpreted in the broadest sense such that "on … …" means not only "directly on something" but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above … …" or "above … …" includes the meaning of "not only" on something "or" above "but also" above "or" above "without intermediate features or layers therebetween (i.e., directly on something).
The term "substrate" as used herein refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added atop the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).
The term "layer" as used herein may refer to a portion of material that includes regions having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of a continuous structure, either homogenous or non-homogenous, having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically and/or along a tapered surface. The display panel may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, and/or therebelow. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (4)
1. An array substrate, comprising: the substrate, the first metal layer that is located one side of the substrate and the second metal layer that is located one side of the first metal layer that is far away from the substrate are arranged, an insulating layer is arranged between the first metal layer and the second metal layer, the first metal layer is used for setting a clock signal line, the second metal layer is used for setting a grid line, the clock signal line and the grid line are overlapped, and the grid line at the overlapped position spans the clock signal line,
the width of the orthographic projection of the grid line positioned at the overlapping position on the substrate is a first width, and the width of the orthographic projection of the grid line positioned at the non-overlapping position on the substrate is a second width; the first width is greater than the second width before the gate line is deposited;
the first width and the second width have a first difference, the first difference being greater than or equal to 1 μm and less than or equal to 3 μm;
the first width is greater than or equal to 12 μm and less than or equal to 13 μm, and the second width is greater than or equal to 10 μm and less than or equal to 11 μm;
the on-state voltage of the gate line at the overlapping position is greater than or equal to 5V and less than or equal to 15V, and the off-state voltage of the clock signal line at the overlapping position is greater than or equal to-20V and less than or equal to-15V;
the signal input end of each gate line is provided with a layer transfer hole, and the layer transfer hole is connected with an electrostatic discharge piece;
the static electricity discharge piece comprises a static electricity ring and a static electricity discharge wire, and the static electricity ring is respectively connected with the layer rotating hole and the static electricity discharge wire;
the electrostatic ring comprises a first thin film transistor and a second thin film transistor; the grid electrode and the source electrode of the first thin film transistor are simultaneously connected to the grid electrode line, and the drain electrode of the first thin film transistor is connected to the electrostatic discharge wire; the grid electrode and the source electrode of the second thin film transistor are connected to the static electricity discharge wire, and the drain electrode is connected to the grid line.
2. The array substrate of claim 1, wherein an on-state voltage of the gate line at the overlap and an off-state voltage of the clock signal line at the overlap have a second difference value, the second difference value being greater than or equal to 12V and less than or equal to 35V.
3. The array substrate of claim 1, wherein the clock signal lines comprise a plurality of the clock signal lines arranged at intervals along a first direction in the first metal layer;
the grid lines comprise a plurality of grid lines which are arranged on the second metal layer at intervals along the second direction;
the first direction and the second direction are perpendicular to each other.
4. A display panel, comprising a color film substrate and an array substrate according to any one of claims 1 to 3, wherein a liquid crystal layer is disposed between the color film substrate and the array substrate.
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| CN114280863A (en) | 2022-04-05 |
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