JP2007304921A - Cpu duplex system - Google Patents

Cpu duplex system Download PDF

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JP2007304921A
JP2007304921A JP2006133409A JP2006133409A JP2007304921A JP 2007304921 A JP2007304921 A JP 2007304921A JP 2006133409 A JP2006133409 A JP 2006133409A JP 2006133409 A JP2006133409 A JP 2006133409A JP 2007304921 A JP2007304921 A JP 2007304921A
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cpu
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duplex
circuit
switching unit
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JP4788469B2 (en
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Yoichi Suetsugu
洋一 末次
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Toshiba Mitsubishi Electric Industrial Systems Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a CPU duplex system having a CPU duplex switching unit capable of easily constructing the CPU duplex system even when the CPU modules are inexpensive and various. <P>SOLUTION: A system has two CPU modules 1 and alternately changes the states of control/standby of two CPU modules has one CPU duplex switching unit 5 for two CPU modules. The CPU duplex switching unit comprises a CPU state input circuit 2 for inputting abnormal states of two CPU modules, an abnormality diagnostic circuit 3 for detecting abnormality, and a duplex system switching circuit 4 for determining the switch between the control state and standby state of two CPU modules. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、高信頼性が求められるプラント等の制御装置において用いられるCPU二重化システムに関するものである。   The present invention relates to a CPU duplication system used in a control apparatus such as a plant that requires high reliability.

一般に、高い信頼性が求められるような重要ブラント等の制御装置においては、その制御演算を行うCPUモジュールを二重に備えることが求められる。   Generally, in a control device such as an important blunt that requires high reliability, it is required to have double CPU modules that perform the control calculation.

図2及び図3は、従来のCPU二重化システムの例を示す構成図である(例えば、特許文献1参照)。図2に示すCPU二重化システムでは、CPUモジュール21に異常診断回路23と二重系切換回路24を搭載している場合である。各々のCPUモジュール21は、それぞれの異常診断回路23によって自己(自系)の異常を監視しており、また二重系切換回路24を介してもう一方の相手(他系)の正常/異常、及び制御/待機の状態を監視している。ここで、現用系のCPUモジュール21に異常が発生した場合や、その他の制御/待機の切換え条件が成立した場合には、双方の二重系切換回路24によって予備系のCPUモジュール21へ制御権が移され、現用系と予備系が入れ替わる。なお、29は双方の二重系切換回路24間を接続して制御/待機状態指令信号を出す信号線である。   2 and 3 are configuration diagrams showing an example of a conventional CPU duplex system (see, for example, Patent Document 1). In the CPU duplex system shown in FIG. 2, the CPU module 21 is equipped with an abnormality diagnosis circuit 23 and a dual system switching circuit 24. Each CPU module 21 monitors its own (own system) abnormality by its own abnormality diagnosis circuit 23, and normal / abnormal of the other party (other system) via the dual system switching circuit 24, And control / standby status is monitored. Here, when an abnormality occurs in the active CPU module 21 or when other control / standby switching conditions are satisfied, the control authority is given to the standby CPU module 21 by both the dual system switching circuits 24. Is transferred, and the active system and the standby system are switched. Reference numeral 29 denotes a signal line for connecting the two dual system switching circuits 24 and outputting a control / standby state command signal.

また、図3に示すCPU二重化システムでは、二つのCPUモジュール31と、それらと1対1に対応するRASモジュール32と、CPUモジュール31とRASモジュール32の間を接続してCPU状態信号を送信するデータバス35と、二つのRASモジュール32間を接続して制御/待機状態信号を送信する信号線39とで構成されており、RASモジュール32上には、それと対をなすCPUモジュール31の異常診断をする異常診断回路33と二重系切換回路34を搭載している。なお、RASモジュール32の異常診断回路33には、その一部として異常監視タイマ38が設けられている。また、RASモジュール32には、二重系切換回路34に対して起動時の制御/待機状態を設定するための優先系選択機能と、制御/待機の状態を手動で切換えるための手動選択機能を備えたスイッチ40が設けられている。   In the CPU duplication system shown in FIG. 3, the CPU status signal is transmitted by connecting the two CPU modules 31, the RAS module 32 corresponding to them, and the CPU module 31 and the RAS module 32. It comprises a data bus 35 and a signal line 39 for connecting the two RAS modules 32 and transmitting a control / standby state signal. On the RAS module 32, an abnormality diagnosis of the CPU module 31 paired therewith is made. An abnormality diagnosis circuit 33 and a dual system switching circuit 34 are mounted. The abnormality diagnosis circuit 33 of the RAS module 32 is provided with an abnormality monitoring timer 38 as a part thereof. In addition, the RAS module 32 has a priority system selection function for setting the control / standby state at the start-up for the dual system switching circuit 34 and a manual selection function for manually switching the control / standby state. A provided switch 40 is provided.

従来はこのようなCPU二重化システムを設けることによって、CPUモジュールにおけるトラブル時の危険回避を図ってきた。   Conventionally, by providing such a CPU duplication system, a risk avoidance at the time of trouble in the CPU module has been attempted.

特開2001−60160号公報(図1、図5)JP 2001-60160 A (FIGS. 1 and 5)

上記で説明した従来のCPU二重化システムは、図2においてはCPUモジュール21上に異常を監視できる十分な機能をする異常診断回路23、二重系切換回路24を有する必要があり、このようなCPU二重化システムを構築するためには、二重化専用CPUモジュールを使用するか、あるいは同等の機能を持ったCPUモジュールの開発が必要であった。また、図3のCPU二重化システムにおいてもバス仕様が同一の汎用CPUモジュールには適用が容易であるが、パス仕様の異なるCPUモジュールに適用する場合は、新たにRASモジュール32の開発が必要である。従って、従来のシステム構成ではコスト面及びCPUモジュールの機種変更の面で問題があった。   In FIG. 2, the conventional CPU duplex system described above needs to have an abnormality diagnosis circuit 23 and a dual system switching circuit 24 having a sufficient function for monitoring an abnormality on the CPU module 21, and such a CPU is required. In order to build a duplex system, it is necessary to use a dedicated CPU module for duplex or develop a CPU module having an equivalent function. Also, the CPU redundant system of FIG. 3 can be easily applied to general-purpose CPU modules having the same bus specifications, but when applied to CPU modules having different path specifications, a new RAS module 32 needs to be developed. . Therefore, the conventional system configuration has problems in terms of cost and changing the model of the CPU module.

この発明は上記のような課題を解決するためになされたもので、低コストで多種多様なCPUモジュールであっても容易にCPU二重化システムが構築できるCPU二重化切換ユニットを備えたCPU二重化システムを提供するものである。   The present invention has been made to solve the above problems, and provides a CPU duplication system including a CPU duplication switching unit that can easily construct a CPU duplication system even with a wide variety of CPU modules at low cost. To do.

この発明にかかるCPU二重化システムにおいては、二つのCPUモジュールを有し、該二つのCPUモジュールにおける制御/待機の状態を必要に応じて交互に変更するものにおいて、二つのCPUモジュールに対して一つのCPU二重化切換ユニットを有し、CPU二重化切換ユニットは、二つのCPUモジュールの異常状態を入力するCPU状態入力回路と、異常を検知する異常診断回路と、二つのCPUモジュールの制御/待機状態を切換える決定を行う二重系切換回路とを備えたものである。   In the dual CPU system according to the present invention, there are two CPU modules, and the control / standby states of the two CPU modules are alternately changed as necessary. The CPU duplication switching unit has a CPU duplication switching unit that switches between a CPU status input circuit that inputs an abnormal state of two CPU modules, an abnormality diagnosis circuit that detects an abnormality, and a control / standby state of the two CPU modules. And a dual system switching circuit for making a decision.

この発明によれば、別置きのCPU二重化切換ユニットにCPU異常検知機能及び二重系切換機能を有しているため、CPUモジュールに特別な切換処理が不必要となり低コストでCPU二重化システムが構築できる。またCPUモジュールの状態信号入力を様々なCPUモジュールの出力仕様に合うようにCPU二重化切換ユニットのCPU状態入力回路に複数搭載することにより、出力仕様の違う各種CPUモジュールにも適用可能となる。   According to the present invention, the CPU redundant detection unit and the dual system switching function are provided in a separate CPU redundant switching unit, so that no special switching processing is required for the CPU module, and a CPU redundant system is constructed at low cost. it can. In addition, by mounting a plurality of CPU module status signal inputs in the CPU status input circuit of the CPU duplex switching unit so as to meet the output specifications of various CPU modules, the CPU module can be applied to various CPU modules having different output specifications.

図1はこの発明の実施の形態1におけるCPU二重化システムを示すシステム構成図である。
図に示すこの発明のCPU二重化システムは、二つのCPUモジュール1と、一つのCPU二重化切換ユニット5と、CPUモジュール1からCPU状態信号を送信する信号線7と、CPU二重化切換ユニット5よりCPUモジュール1に制御/待機状態指令を送信する信号線9とで構成されている。
FIG. 1 is a system configuration diagram showing a dual CPU system according to Embodiment 1 of the present invention.
The CPU duplex system of the present invention shown in the figure includes two CPU modules 1, one CPU duplex switching unit 5, a signal line 7 for transmitting a CPU status signal from the CPU module 1, and a CPU module based on the CPU duplex switching unit 5. 1 and a signal line 9 for transmitting a control / standby state command.

ここで、CPUモジュール1は、異常診断回路、二重系切換回路などを搭載していない汎用的なものである。一方、CPU二重化切換ユニット5は、この発明のCPU二重化システムのために開発されたもので、異常診断機能や二重系切換機能及びCPU信号入力機能等を備えたCPU二重化切換ユニットである。   Here, the CPU module 1 is a general-purpose module not equipped with an abnormality diagnosis circuit, a dual system switching circuit, or the like. On the other hand, the CPU duplex switching unit 5 was developed for the CPU duplex system of the present invention, and is a CPU duplex switching unit having an abnormality diagnosis function, a dual system switching function, a CPU signal input function, and the like.

CPU二重化切換ユニット5上には、二つのCPUモジュール1より出力するCPU状態信号を出力仕様にあわせて入力できる二つのCPU状態入力回路2と、二つのCPUモジュール1それぞれの異常診断をする二つの異常診断回路3と、二つのCPUモジュール1の制御/待機状態を切換える決定を行う一つの二重系切換回路4とを搭載している。なお、CPU二重化切換ユニット5の異常診断回路3には、その一部として異常監視タイマ8が設けられている。また、CPU二重化切換ユニット5には、二重系切換回路4に対して起動時の制御/待機状態を設定するための優先系選択機能と、制御/待機の状態を手動で切換えるための手動選択機能を備えたスイッチ10が設けられている。   On the CPU duplex switching unit 5, two CPU status input circuits 2 that can input CPU status signals output from the two CPU modules 1 in accordance with the output specifications, and two that diagnose each of the two CPU modules 1 are diagnosed. The abnormality diagnosis circuit 3 and one dual system switching circuit 4 for determining switching between the control / standby states of the two CPU modules 1 are mounted. An abnormality monitoring timer 8 is provided as a part of the abnormality diagnosis circuit 3 of the CPU duplex switching unit 5. Further, the CPU duplex switching unit 5 has a priority system selection function for setting the control / standby state at the start-up for the dual system switch circuit 4 and a manual selection for manually switching the control / standby state. A switch 10 having a function is provided.

次に、この発明のCPU二重化切換ユニットの機能及び動作について以下に説明する。まず、CPUモジュール1は信号線7を介してCPU二重化切換ユニット5にCPU状態信号を定周期出力する。なお、この信号は各種CPUモジュールに応じてデジタル(DO)出力、LAN通信出力、シリアル通信出力を可能とする。CPU二重化切換ユニット5はCPU状態入力回路2でCPUモジュール1からのCPU状態信号を受信し、受信毎にCPU状態入力回路2は異常診断回路3にアクセスする。   Next, functions and operations of the dual CPU switching unit of the present invention will be described below. First, the CPU module 1 outputs a CPU status signal to the CPU duplex switching unit 5 through the signal line 7 at regular intervals. This signal enables digital (DO) output, LAN communication output, and serial communication output according to various CPU modules. The CPU duplex switching unit 5 receives the CPU status signal from the CPU module 1 by the CPU status input circuit 2, and the CPU status input circuit 2 accesses the abnormality diagnosis circuit 3 every time it is received.

異常診断回路3はCPU状態入力回路2からのアクセスにより異常監視タイマ8をクリアする。これによりCPUモジュール1の正常/異常の状態を把握し、異常監視タイマ8がタイムアウトとなった場合は、CPUモジュール1を異常と判断し、二重系切換回路4よりCPUモジュール1へ制御/待機状態指令が出力され制御が自系から他系へ切替わる。   The abnormality diagnosis circuit 3 clears the abnormality monitoring timer 8 by access from the CPU state input circuit 2. As a result, the normal / abnormal state of the CPU module 1 is grasped, and when the abnormality monitoring timer 8 times out, the CPU module 1 is determined to be abnormal, and the dual system switching circuit 4 controls / waits to the CPU module 1. A status command is output and control switches from the local system to another system.

また、起動時及び手動切換はスイッチ10からの指示により二重系切換回路4から同様に制御/待機状態指令信号が出力され制御/待機状態が決定される。   At the time of start-up and manual switching, a control / standby state command signal is similarly output from the dual system switching circuit 4 according to an instruction from the switch 10 to determine the control / standby state.

以上説明したように、この発明は、二重化切換専用ユニットをCPUモジュールの外部に設け、CPUモジュールとのインタフェースを各種搭載した構成としている。従って、特別に二重化切換ロジックの作成が不必要でかつ、多種多様なCPUモジュールに適用可能であるため、CPU二重化システムを低コストで構築することが可能となる。   As described above, according to the present invention, the duplex switching dedicated unit is provided outside the CPU module, and various interfaces with the CPU module are mounted. Therefore, it is not necessary to create a duplex switching logic and can be applied to a wide variety of CPU modules. Therefore, it is possible to construct a CPU duplex system at a low cost.

この発明の実施の形態1におけるCPU二重化システムを示すシステム構成図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a system block diagram which shows the CPU duplication system in Embodiment 1 of this invention. 従来のCPU二重化システムの一例を示すシステム構成図である。It is a system block diagram which shows an example of the conventional CPU duplication system. 従来のCPU二重化システムの他の例を示すシステム構成図である。It is a system block diagram which shows the other example of the conventional CPU duplication system.

符号の説明Explanation of symbols

1 CPUモジュール
2 CPU状態入力回路
3 異常診断回路
4 二重系切換回路
5 CPU二重化切換ユニット
7 信号線(CPU状態信号)
8 異常監視タイマ
9 信号線(制御/待機状態指令信号)
10 スイッチ
DESCRIPTION OF SYMBOLS 1 CPU module 2 CPU status input circuit 3 Abnormality diagnosis circuit 4 Duplex system switching circuit 5 CPU duplication switching unit 7 Signal line (CPU status signal)
8 Abnormality monitoring timer 9 Signal line (Control / standby state command signal)
10 switch

Claims (2)

二つのCPUモジュールを有し、該二つのCPUモジュールにおける制御/待機の状態を必要に応じて交互に変更するCPU二重化システムにおいて、
前記二つのCPUモジュールに対して一つのCPU二重化切換ユニットを有し、
前記CPU二重化切換ユニットは、前記二つのCPUモジュールの異常状態を入力するCPU状態入力回路と、異常を検知する異常診断回路と、前記二つのCPUモジュールの制御/待機状態を切換える決定を行う二重系切換回路とを備えたことを特徴とするCPU二重化システム。
In a CPU duplex system having two CPU modules and alternately changing the control / standby state in the two CPU modules as necessary,
One CPU duplication switching unit for the two CPU modules;
The dual CPU switching unit is a CPU state input circuit that inputs an abnormal state of the two CPU modules, an abnormal diagnosis circuit that detects an abnormality, and a dual determination that switches between control / standby states of the two CPU modules. A dual CPU system comprising a system switching circuit.
CPU状態入力回路は、デジタル、LAN通信、シリアル通信等の複数の入力手段を有することを特徴とする請求項1記載のCPU二重化システム。   2. The CPU duplex system according to claim 1, wherein the CPU status input circuit has a plurality of input means such as digital, LAN communication, serial communication and the like.
JP2006133409A 2006-05-12 2006-05-12 Redundant CPU system Expired - Fee Related JP4788469B2 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0375837A (en) * 1989-08-17 1991-03-29 Yokogawa Electric Corp Duplex control system
JP2001060160A (en) * 1999-08-23 2001-03-06 Mitsubishi Heavy Ind Ltd Cpu duplex system for controller
JP2003162460A (en) * 2001-11-22 2003-06-06 Densei Lambda Kk Operational status monitoring system for uninterruptible power supply units

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0375837A (en) * 1989-08-17 1991-03-29 Yokogawa Electric Corp Duplex control system
JP2001060160A (en) * 1999-08-23 2001-03-06 Mitsubishi Heavy Ind Ltd Cpu duplex system for controller
JP2003162460A (en) * 2001-11-22 2003-06-06 Densei Lambda Kk Operational status monitoring system for uninterruptible power supply units

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