JP2007299805A - Calibration method of detected gap value - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform positioning such that the gap between a wafer and a mask has a set value. <P>SOLUTION: Image data of mask marks M1-M3 and adjustment marks WC1-WC3 are subjected to image processing; and positioning is performed such that the center of the longitudinal patterns WC1v-WC3v in the cross pattern of the adjustment marks WC1-WC3 match the center of the first through-hole of the mask marks M1-M3, and the distance between the center of the lateral patterns WC1h-WC3h in the cross pattern and the center line of a partition in the horizontal direction becomes 100 μm. Angle of a CCD camera is set at 30° and the clearance between the mask mark M1, and a wafer mark W1 is set at 86.603 μm. When the clearance between the mask mark M1 and the wafer mark W1 is set at 100 μm on the image; the gap g between adjustment wafer surface and the mask surface is made to become a set value of 50 μm, and the gap inspection value determined from the length of the shadow S of the mask mark M1 is calibrated by using the gap g as a true value. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention irradiates light to a wafer mark for positioning provided on a semiconductor wafer and a mask mark formed on a mask arranged so as to overlap the semiconductor wafer, and enters the reflected light so that the wafer mark and the mask mark are Image capturing, image processing of captured image data is performed, the relative position between the wafer mark and the mask mark is recognized, and positioning for controlling the gap between the wafer mark and the mask mark to a set value based on the recognition result It relates to the device.

  Conventionally, as a positioning device used in, for example, a semiconductor exposure apparatus, an ion implantation apparatus, an assembly / inspection apparatus, a precision machine tool, etc., a positioning object is placed (held) on a table that can be positioned with high accuracy. Done. In a semiconductor exposure apparatus, ion implantation apparatus, etc., a semiconductor wafer as a positioning target is in a state in which a mask having a predetermined pattern is opposed to the wafer through a predetermined minute gap (gap) for each section (one chip). In some cases, predetermined operations such as exposure and ion implantation may be performed.

In such a case, the positioning mark (wafer mark) provided for each section on the semiconductor wafer and the mask mark provided on the mask corresponding to the wafer mark are usually illuminated with light from the light source and optically Based on the result, precise alignment within the pattern surface and gap adjustment between the semiconductor wafer and the mask are performed. (For example, Patent Document 1)
Japanese Patent Laid-Open No. 2005-5402

  In this way, the position adjustment is performed based on the result of optically detecting the positioning mark, so that the measured value obtained from the detection result matches the actual positional deviation amount and the gap value (true value) as much as possible. It is desirable to perform calibration in advance. For example, as a calibration operation for detecting a gap between a mask and a semiconductor wafer, an accurate measurement device such as a capacitance displacement meter or a laser displacement meter is used to measure the gap value, and the result is obtained. It is conceivable to calibrate the optical detection result as a reference. However, if a capacitance-type displacement meter (ADE), laser displacement meter, or the like is used to actually measure the gap between the semiconductor wafer and the wafer mark, depending on the space and material, a semiconductor exposure device, an ion implantation device, etc. May be difficult to incorporate into Also, when using a high-resolution sensor as a displacement meter, it is necessary to bring it close to the semiconductor wafer or mask, and if the high-resolution sensor is placed away from the semiconductor wafer or mask due to space problems, the resolution will be reduced. Become.

  Further, if the high resolution sensor is simply brought close to the semiconductor wafer or mask, the high resolution sensor may collide with the semiconductor wafer or mask. Furthermore, when the actual measurement value is not calibrated, the gap between the semiconductor wafer and the mask is different, and there is a risk of distortion occurring at the ion implantation position.

  The present invention has been made in view of the above-described problems of the prior art, and its purpose is to perform calibration without using a separate dedicated measuring instrument so that the gap between the semiconductor wafer and the mask becomes a set value. There is in positioning.

  In order to achieve the above object, the present invention provides a semiconductor wafer, an illuminating means for irradiating light to an imaging region of a mask arranged to overlap the semiconductor wafer, and the semiconductor wafer and the mask from the illuminating means. An imaging means for imaging a positioning wafer mark formed on the semiconductor wafer and a mask mark formed on the mask by inputting reflected light of the irradiated light on the semiconductor wafer, and imaging data obtained by imaging by the imaging means Recognition means for performing image processing to recognize a relative position of the wafer mark to the mask mark, and position control means for controlling a relative position between the wafer mark and the mask mark based on a recognition result of the recognition means. When the relative position with respect to the mask is aligned, the adjustment mark is moved by the illumination means with respect to a reference position of the mask mark. An adjustment wafer is prepared that is designed to have a portion that is separated by a predetermined distance L when viewed from a direction orthogonal to the mask upper surface in the direction in which the shadow of the mask mark extends, and the mask mark viewed from the imaging means The gap detection value is calibrated based on a recognition result by the recognition means, with a gap value between the mask and the adjustment wafer determined from a distance between the reference position and the portion of the adjustment wafer as a true value. And

  According to the above configuration, the relative position between the adjustment mark and the mask mark so that the position of the image of the adjustment mark and the image of the mask mark in the image recognized by the recognition unit has a predetermined relationship on the image. By adjusting the gap value obtained from the mask mark and its shadow and the gap value obtained from the mask mark and the adjustment mark as a reference, the semiconductor wafer and the mask can be controlled without using a separate measuring instrument. Can be maintained at the set value. For example, when the angle of the image pickup means is 30 degrees and the positional relationship between the mask mark and the adjustment mark is 86.603 μm and both are arranged, when the distance between both is 100 μm on the image, the adjustment wafer (adjustment mark) ) And the mask (mask mark) has a set value = 50 μm (86.603 μm is the base of the right triangle, 100 μm is the hypotenuse of the right triangle, and the gap is the opposite side with an angle of 30 degrees, and the gap = 100/2 μm = 50 μm. ). Accordingly, it is possible to improve the absolute position accuracy of the gap between the semiconductor wafer and the mask.

  In the present invention, the position control means calculates a pixel resolution in a gap direction between the wafer mark and the mask mark on a piezo basis, and calculates a gap between the wafer mark and the mask mark from the calculation result. It can be set as the structure formed. The mask may be a stencil mask used for an exposure machine or an ion implanter.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to contribute to the improvement of the absolute position accuracy of the gap of a semiconductor wafer and a mask, generation | occurrence | production of inferior goods can be reduced by preventing the collision with a semiconductor wafer and a mask. .

    FIG. 1 shows a semiconductor positioning device (hereinafter simply referred to as a positioning device) 10 according to the present embodiment.

  In the positioning device 10, a support column 14 is erected with respect to the surface plate 12, and a top plate 16 is attached to the upper end of the support column 14 to constitute a housing of the positioning device 10.

  The positioning device 10 serves to position the semiconductor wafer 18 with respect to the semiconductor wafer 18.

  A workpiece positioning stage unit 20 and a mask stage unit 22 are installed on the surface plate 12 of the positioning apparatus 10.

  The workpiece positioning stage unit 20 includes a base 24, an X-axis direction sliding device 28 provided on the base 24 and supporting the first slider 26 so as to be slidable in the X-axis direction, and the first slider 26 as the X-axis. And an X-axis direction driving device 29 for driving in the direction. A second slider 30 is provided on the first slider 26, and the second slider 30 is supported by a Y-axis direction sliding device 32 so as to be slidable in the Y-axis direction. Driven in the Y-axis direction by an axial drive device.

  Further, the second slider 30 supports a work stage 34 as a sample base such as the semiconductor wafer 18 positioned in the X-axis direction and the Y-axis direction.

  A wafer chuck 36 that holds the semiconductor wafer 18 is attached to the work stage 34.

  The semiconductor wafer 18 is fixed while being supported by the wafer chuck 36. The wafer chuck 36 has a mechanism capable of fine adjustment of the six degrees of freedom (X, Y, Z axis directions and rotations about the respective axes) of the chucked semiconductor wafer 18.

  With the workpiece positioning stage unit 20 having the above-described configuration, the wafer chuck 36 can perform step feed in the XY plane and fine position and posture adjustment with six degrees of freedom.

  Above the work stage 34, a mask chuck 38 that constitutes a part of the mask stage unit 22 is disposed opposite to the second stage 30. The mask chuck 38 holds the mask 40 on the surface facing the wafer chuck 36. The mask chuck 38 is supported by the mask θ-axis base 42 and can be adjusted in the θ-axis direction (the rotational direction in the XY plane).

  The mask θ-axis base 42 is supported by the mask Z-axis direction moving mechanism 44. Further, the mask Z-axis direction moving mechanism 44 is supported by a mask XY table 46. The mask XY table 46 has the same configuration as that of the workpiece positioning stage unit 20, and thus the description of the configuration is omitted.

  With this mask stage portion 22, the mask 40 can be adjusted in the respective axial directions of XYZ-θ.

  The top plate 16 constituting the casing of the positioning device 10 is provided with an opening 16A at the center (around the reference axis on which the semiconductor wafer 18 is positioned). An alignment unit 50 for detecting the positioning wafer marks W1 to W3 (see FIG. 2) provided on the semiconductor wafer 18 and adjusting the position of the semiconductor wafer 18 on the work stage 34 is attached to the top plate 16. ing. Although only one set is shown in FIG. 1, a total of three sets of alignment units 50 are arranged corresponding to each of the wafer marks W1 to W3.

  As shown in FIG. 2, on the surface of a semiconductor wafer 18 that is a silicon substrate, for example, a large number of pattern areas 18A of about 30 mm × 30 mm are arranged in a matrix. For example, isolation regions 18B having a width of several tens of microns are formed in a lattice shape between the pattern regions 18A for subsequent chip cutting. Three wafer marks W1 to W3 are preliminarily formed of silicon oxide films per region at appropriate locations in the isolation region 18B. In the illustrated example, the wafer marks W1 and W2 are generated in a linear pattern along the Y-axis direction, and the wafer mark W3 is generated in a linear pattern along the X-axis direction. The orientation in which the alignment unit 50 is installed is determined according to the orientation of these patterns. In FIG. 2, only the wafer marks W1 to W3 corresponding to the hatched central pattern area 18A are shown, but the wafer marks W1 to W3 are similarly arranged around all the patterns.

  Since the silicon oxide film portion has a lower reflectivity than the surrounding silicon portion and is dark, the wafer marks W1 to W3 can be observed. Further, the pattern of the wafer marks W1 to W3 is not limited to the above, and any pattern may be used as long as the mask 40 and the semiconductor wafer 18 can be aligned based on the wafer marks W1 to W3. For example, when using a linear pattern similar to the above, one is a linear pattern along the X-axis direction, one is a linear pattern along the Y-axis direction, and the rest is along the X-axis direction and the Y-axis direction. Alternatively, the direction may be set to be inclined by 45 degrees.

  The wafer marks W1, W2, and W3 can be obtained by making the silicon oxide film of the pattern portion flush with the surrounding portion or slightly raised, but instead, the silicon oxide film on the semiconductor wafer 18 is oxidized. It is good also as a linear pattern which makes the linear pattern of a film | membrane project. Or, conversely, the wafer marks W1, W2, and W3 may be made of silicon and surrounded by a silicon oxide film.

  The alignment unit 50 detects the wafer marks W1, W2, and W3, thereby recognizing the position of the semiconductor wafer 18 and generating data for executing positioning correction.

  FIG. 3 is an explanatory diagram for explaining the mask 40. 3A is a plan view, and FIG. 3B is a cross-sectional view in the AA direction of FIG. 3A.

  The mask 40 is, for example, a stencil mask used in an exposure machine, an ion implanter, and the like, and has a circular outer shape and a relatively thick peripheral part 40A, a relatively thin membrane part 40B in this inner region, a membrane Mask pattern 40C having a pattern corresponding to the pattern to be formed in the central portion of the portion 40B, and mask marks (penetrations) formed at positions corresponding to the wafer marks W1 to W3 of the semiconductor wafer 18 around the mask pattern portion 40C. Holes M1 to M3, a pre-alignment cutout 40D formed on the peripheral edge 40A, and a global alignment mark 40E for coarse adjustment.

  The mask 40 is made of, for example, silicon and has a diameter of 4 inches, a peripheral portion 40A having a thickness of 0.5 mm, and a membrane portion 40B in the central region having a thickness of 10 μm.

  Further, the mask marks M1 to M3 of the mask 40 of the present embodiment are constituted by an assembly of a plurality of through holes as shown in FIG. Each of the mask marks M1 to M3 is provided in an orientation such that the pattern of the corresponding wafer marks W1 to W3 is substantially parallel to partition portions 70 and 71 described later. The orientation of the alignment unit 50 is set so that the plane including the optical axis is parallel to the partition portions 70 and 71 in design.

  FIG. 4 shows one mask mark (here, a mask mark for a visual field area (area surrounded by a square outside FIG. 4) 54A in which a large number of pixels constituting the CCD camera 54 (see FIG. 1) are arranged in a matrix. An enlarged view of the mask mark M1 is shown.

  The visual field area 54 </ b> A of the CCD camera 54 is irradiated with uniform light by illumination from the illumination light source unit 52.

  The first through hole 60 is an area where the wafer mark W1 is positioned by rough adjustment, and the longitudinal dimension is the same as the dimension (vertical dimension) of the left side along the left side of the first through hole 60. A vertically long second through hole 62 is provided.

  Further, third and fourth through holes 64 and 66 are provided on the right side of the first through hole 60, and these are arranged in a column. The dimension obtained by adding the vertical dimension of the third and fourth through holes 64 and 66 and the dimension of these gaps is the same as the dimension (vertical dimension) of the first right side.

  Thereby, the area | region surrounding the 1st thru | or 4th through-holes 60, 62, 64, 66 becomes a rectangular shape (refer the dashed-dotted line area | region M1 (M2, M3) of FIG. 4).

  Here, the second to fourth through holes 62, 64, and 66 are each formed with a partition portion having a line width between the adjacent through holes.

  As shown in FIG. 4, the partition 72 between the through holes 64 and 66 is set so as to overlap the shadow S portion of the mask 40 in the exposed portion of the semiconductor wafer 18 as viewed from the CCD camera 54.

  The partition part 70 between the first through hole 60 and the second through hole 62 and the partition part 71 between the first through hole 60 and the third through hole 64 are formed on the wafer mark W1 with respect to the mask mark M1. In FIG. 4, it is used to determine the amount of lateral displacement. On the other hand, the gap between the upper surface of the mask 40 and the upper surface of the semiconductor wafer 18 is obtained from the shadow length of the mask mark M1 (distance G in FIG. 4). That is, when the gap is g and the mounting angle α of the CCD camera 54 and the illumination light source unit 52 (see FIG. 5 described later), there is a relationship of G = 2g · sin α with the shadow length G. For example, when the attachment angle α is 30 degrees, g = G.

  Further, by detecting the dimension A and the dimension B in FIG. 4, the relative positional relationship between the visual field area 54A of the CCD camera 54 and the mask mark M1 can be recognized, and according to a difference from a predetermined reference dimension. By performing fine adjustment, the relative positional relationship can always be kept constant.

  Note that this relative positional adjustment is performed by moving the CCD camera 54. Therefore, as shown in FIG. 1, the imaging unit 56 on the top plate 16 is supported by a camera XY table 74. The camera XY table 74 has the same configuration as that of the positioning stage unit 20 (see FIG. 1) described above, and a description of the configuration is omitted.

  As shown in FIG. 1, the alignment unit 50 includes an illumination light source unit 52 using a light emitting diode (LED) LD as a light source, an imaging optical system 53 including a plurality of lenses, and an imaging unit 56 including a CCD camera 54. Composed.

  Note that the sensor is not limited to the CCD, and may be replaced by any camera provided with a sensor that can obtain imaging data capable of performing known image processing. Illumination light emitted from the illumination light source unit 52 by arranging the optical axis of the illumination light source unit 52 and the optical axis of the CCD camera 54 of the imaging unit 56 so as to be symmetric with respect to the normal of the surface of the wafer mark W1. Is reflected by the wafer mark W1 and becomes incident light of the CCD camera 54 of the imaging unit 56. Since wafer marks W2 and W3 have the same configuration as described above (that is, a total of three alignment units 50 are arranged on top plate 16), description of the configuration is omitted.

  The position of the mask 40 is coarsely adjusted in advance by observing the global alignment mark 40E (see FIG. 3), and the position of the work stage 34 is coarsely adjusted using a predetermined reference on the semiconductor wafer 18. Accordingly, when the mask pattern portion 40C is positioned so as to face the position where the pattern of the semiconductor wafer 18 is transferred by step feed, the wafer mark W1 of the semiconductor wafer 18 is positioned in the through hole 60 of the mask pattern M1. Adjust as follows. Further, the image data of the mask mark M1 of the mask 40 and the wafer mark W1 are simultaneously captured by the CCD camera 54 with the pattern portion 40C of the mask 40 facing one pattern region 18A on the semiconductor wafer 18. Similarly, image data of mask mask M2 (M3) and wafer mark W2 (W3) is acquired at the same time for the other two locations. Based on the obtained image data at three locations, alignment of the mask 40 and the semiconductor wafer 18 (gap adjustment between the mask 40 and the semiconductor wafer 18 and alignment within the XY plane) is performed by the 6-degree-of-freedom fine movement mechanism. .

  As shown in FIG. 1, the illumination light source unit 52 that constitutes a part of the alignment unit 50 is housed in a casing 76 and fixedly arranged on the top plate 16. The housing 76 is provided with a holder (not shown) that holds the light emitting diode LD, and as described above, the optical axis to the mask 40 is kept constant.

  As shown in FIGS. 1 and 5, light (usually diffused light) emitted from the light emitting diode LD is wider as a plurality of lenses arranged in the irradiation direction or with uniform brightness. An area including the mask mark M1 (illumination area in FIG. 4) is illuminated almost uniformly via an illumination optical system 78 including a glass rod for illuminating the range.

  Further, in the present embodiment, a dedicated adjustment wafer for calibrating gap detection between the mask 40 and the semiconductor wafer 18 is used. This adjustment wafer has the same material and size as the semiconductor wafer 18 to be processed, and has adjustment marks WC1, WC2, and WC3 for exclusive use at positions corresponding to the wafer marks W1, W2, and W3 of the semiconductor wafer 18. It is. This adjustment mark WC1 (WC2, WC3) has a cross-shaped pattern. Among the cross-shaped patterns, the first linear pattern WC1v (WC2v, WC3v) in the substantially vertical direction corresponds to the wafer mark W1 (W2, W3) of the semiconductor wafer 18 in FIG. Thus, the alignment wafer and the mask 40 are used for alignment in the XY plane. Using the first linear pattern WC1v (WC2v, WC3v), the adjustment wafer is aligned with respect to the mask 40 in the XY plane in the same manner as in the case of the semiconductor wafer 18. In the present embodiment, when the three first linear patterns WC1v (WC2v, WC3v) are adjusted so as to be positioned at the exact center of the partition portions 70 and 71 of the corresponding mask marks M1, M2, and M3, the mask 40 and the adjustment wafer are set so as to be aligned. In this alignment state, the first linear pattern WC1v (WC2v, WC3v) is parallel to a plane including the optical axis of the illumination light source unit 52 and the optical axis of the CCD camera 54 by design. As shown in FIG. 4, the mask mark partitioning portions 70 and 71 are set to be parallel to each other.

  Of the cross-shaped patterns, the second linear pattern WC1h (WC2h, WC3h) orthogonal to the first linear pattern WC1v (WC2v, WC3v) is used for calibration of the gap detection value. When the mask 40 and the adjustment wafer are aligned as described above, the second linear pattern WC1h (WC2h, WC3h) has a predetermined position with respect to the corresponding mask marks M1, M2, M3. It is set to be a relationship. Specifically, in the present embodiment, when the mask 40 and the adjustment wafer are aligned in the XY plane, the second linear pattern WC1h (WC2h, WC3h) is the first through hole 60. The center distance (predetermined distance L) from the partition 72 when viewed from the direction perpendicular to the surface of the mask 40 and located in the second through-hole 62 and the fourth through-hole 66 is The gap is set so as to satisfy the relationship of g = L · tan α between the upper surface of the mask 40 and the upper surface of the semiconductor wafer 18 (see FIG. 7). In the present embodiment, the gap set value g is set to 50 μm and α is set to 30 degrees, and therefore L is approximately 86.603 μm. Under such conditions, when the distance (center-to-center distance) between the second linear pattern WC1h (WC2h, WC3h) and the partition 72 when viewed from the direction of the CCD camera 54 is 100 μm, the upper surface of the mask 40 And the adjustment wafer upper surface is set to 50 μm. The adjustment marks WC1 (WC2, WC3) may be provided corresponding to all the pattern areas 18A, or may be provided corresponding to one place or a part of the pattern areas 18A. The procedure and operation of the gap detection value calibration work in the present embodiment will be described below.

(Positioning of adjustment wafer)
First, as in the case of the semiconductor wafer 18 subjected to exposure and ion implantation, the adjustment wafer is held on the wafer chuck 36, and the adjustment marks WC1, WC2, The adjustment wafer is roughly positioned so that WC3 is positioned within the field of view of the CCD camera 54.

  Next, as in the case of the semiconductor wafer 18, the adjustment wafer is aligned in the XY plane. That is, the image data of the mask mark M1 (M2, M3) and the corresponding adjustment mark W1 (W2, W3) imaged by the CCD camera 54 is taken in, and based on the result, three first linear patterns WC1v are obtained. As shown in FIG. 6, the position of the wafer chuck 36 is adjusted by the 6-degree-of-freedom fine movement mechanism so that (WC2v, WC3v) are positioned at the exact center of the partitions 70 and 71, respectively. In the state adjusted in this way, the distance (center-to-center distance) between the partition portion 72 and the second linear pattern WC1h (WC2h, WC3h) when viewed from the direction perpendicular to the surface of the mask 40, In this embodiment, as shown in FIG. 7, the predetermined distance L is 86.603 μm.

(Calculation of pixel resolution)
The pixel resolution constituting the CCD camera 54 is obtained in advance. Specifically, the second linear pattern WC1h (WC2h) in the field of view of the CCD camera 54 when the wafer chuck 36 is moved away (or moved closer) by a predetermined amount, for example, 1 μm, in the Z-axis direction by the six-degree-of-freedom fine movement mechanism. , WC3h), the number of pixels moved vertically in FIG. 6 is examined. Thereby, a distance per pixel when viewed from the direction of the CCD camera 54 is obtained. As a premise, it is necessary to ensure that the amount of movement in the Z-axis direction by the 6-DOF fine movement mechanism is accurate. As an example, when a piezoelectric actuator is used as an actuator in the Z-axis direction, the expansion / contraction amount of the piezoelectric actuator (= actual movement amount of the wafer chuck 36 in the Z-axis direction) is set as, for example, a high-resolution strain gauge. And a method of guaranteeing by the measured value.

(Calibration of gap detection value)
If the pixel resolution is obtained, the exact distance between the partition 72 and the second linear pattern WC1h (WC2h, WC3h) when viewed from the direction of the CCD camera 54 can be known. For example, in the present embodiment, since the mounting angle α of the CCD camera 54 and the illumination light source unit 52 is 30 degrees, as shown in FIG. When the distance from the linear pattern WC1h (WC2h, WC3h) is 100 μm, the distance between the upper surface of the mask 40 and the upper surface of the adjustment wafer is a set value of 50 μm. The length of the shadow S (G in FIG. 4) when viewed from the direction of the CCD camera 54 at this time is, as described above, between the upper surface of the mask 40 and the semiconductor wafer 18 if the mounting angle α is 30 degrees. It should be equal to the gap setting g. Therefore, the Z-axis of the wafer chuck 36 is set such that the distance between the partition portion 72 and the second linear pattern WC1h (WC2h, WC3h) when viewed from the direction of the CCD camera 54 is 100 μm by the 6-degree-of-freedom fine movement mechanism. If the direction position is adjusted and the length of the shadow S obtained from the image data at this time is 50 μm, the gap measurement value using the shadow S is accurate. When the length of the shadow S obtained from the image data does not match 50 μm, the true value of the gap g at this time is 50 μm, and calibration is performed based on this. Since the detected value of the gap g is calibrated as described above, a dedicated measuring device such as a capacitance displacement meter and an extra space for installing the same are not required for calibration. Further, since the calibration can be performed only by holding a dedicated adjustment wafer on the wafer chuck 36 in the same manner as the semiconductor wafer 18 instead of the semiconductor wafer 18, the vacuum state of the entire apparatus can be maintained even during calibration. ; Therefore, calibration can be easily performed whenever necessary.

  Below, the effect | action of the positioning device 10 of this Embodiment is demonstrated.

(Positioning of semiconductor wafer 18)
When the semiconductor wafer 18 as a sample is subjected to processing such as exposure and ion implantation, it is often performed in a vacuum because it dislikes dust. For this reason, the positioning device 10 of the present embodiment is also premised on work in a vacuum.

  First, the semiconductor wafer 18 is placed on the work stage 34 while being held by the wafer chuck 36. The work stage 34 performs planar positioning of the semiconductor wafer 18 by moving the first slider 26 in the X-axis direction and moving the second slider 30 in the Y-axis direction.

  Next, since the wafer chuck 36 itself can be finely adjusted with six degrees of freedom, the semiconductor wafer 18 can be accurately positioned.

  When processing the semiconductor wafer 18, the mask 40 is required. Therefore, a mask chuck 38 is disposed above the work stage 34 so as to face the work stage 34.

  The mask 40 can be applied to the semiconductor wafer 18 by holding the mask 40 on the mask chuck 38.

  Since the mask chuck 38 is supported by the mask θ-axis base 42 and can be adjusted in the θ-axis direction and is supported by the mask Z-axis direction moving mechanism 44, the mask 40 is moved in the Z-axis direction. Can do.

  Further, since the mask Z-axis direction moving mechanism 44 is supported by the mask XY table 46, the mask 40 can be adjusted in the XY axis direction.

  That is, the mask 40 can be adjusted in the respective XYZ-θ directions, and the global alignment is performed in advance using these.

(Fine adjustment between the semiconductor wafer 18 and the mask 40)
As shown in FIG. 6, when the imaging data of the mask mark M1 (M2, M3) and the wafer mark W1 (W2, W3) is obtained by the alignment unit 50 and the imaging data is subjected to image processing, the mask mark M1 (M2, M3) is obtained. ), An image of the center portion of the cross pattern of the wafer mark W1 (W2, W3) is projected into the first through hole 60, and the wafer mark W1 (W2, W3) is based on the shadow length G of the image. And a gap (interval) g between the mask mark M1 (M2, M3) and a lateral shift amount of the wafer mark W1 (W2, W3) with respect to the mask mark M1 (M2, M3).

  Based on each measurement result, the position of the wafer chuck 36 is finely adjusted by a 6-degree-of-freedom fine movement mechanism, and the distance between the semiconductor wafer 18 and the mask 40 is made uniform along with the alignment of the mask 40 and the semiconductor wafer 18 in the XY plane. A predetermined value is set (gap adjustment), and the pattern positions of the semiconductor wafer 18 and the mask 40 are accurately aligned. At this time, the semiconductor wafer 18 and the mask 40 have been subjected to the above-described calibration work (corrected as necessary) so that an accurate gap can be obtained from the measured value of the length of the shadow S. The accuracy of the absolute position of the gap g can be improved.

  Thereafter, the exposure apparatus is operated to form an exposure latent image on the semiconductor wafer 18 (coated with a photosensitive material). After the step feed, the above alignment, and exposure are performed on all the pattern regions 18A on the semiconductor wafer 18, the semiconductor wafer 18 is unloaded from the exposure apparatus, and development, etching, and the like are performed on the semiconductor wafer 18 as desired. The pattern is formed. Also in the case of ion implantation, alignment adjustment between the semiconductor wafer 18 and the mask 40 can be performed by a similar process.

  According to the present embodiment, when the angle of the CCD camera 54 is set to 30 degrees, the alignment wafer is aligned and the positional relationship between the mask mark M1 (M2, M3) and the wafer mark W1 (W2, W3) ( Based on the length of the shadow S in a state where the distance between the mask mark M1 (M2, M3) and the wafer mark W1 (M2, M3) is 100 μm on the image. Since the gap inspection value obtained in this way is calibrated, the gap g between the wafer surface 18a of the semiconductor wafer 18 and the mask surface 40a of the mask 40 can be maintained at the set value = 50 μm. This can contribute to the improvement of the absolute position accuracy of the gap g. As a result, in the ion implantation apparatus, the in-chip gap g of the semiconductor wafer 18 is uniform, and implantation position distortion caused by gap variation can be reduced. Furthermore, the gap g can be made smaller, and the implantation position distortion caused by beam variations can be reduced.

  Further, according to the present embodiment, since the collision accident between the semiconductor wafer 18 and the mask 40 is eliminated, the generation of defective products can be reduced and the damage of the mask 40 due to the collision can be prevented.

  Furthermore, the gap can be calibrated on the basis of the customer's scale (step accuracy). Further, since the alignment system is used, it is not necessary to use a special sensor.

  In the above embodiment, the partition portion 72 of the mask mark M1 (M2, M3) is used as the reference position of the mask mark, and the second linear pattern WC1h (WCh2, WCh3) is used as described above. Although it is used for calibrating the gap detection value between the upper surface of the mask 40 and the upper surface of the semiconductor wafer 18, it is not limited to this. For example, instead of this, the upper side of the through-hole 60 is set as a reference position, and this and the second linear pattern WC1h (WCh2, WCh3) are used to detect the gap detection value between the upper surface of the mask 40 and the upper surface of the semiconductor wafer 18. It may be used for calibration.

  Further, the WC1h (WCh2, WCh3) of the adjustment wafer is a cross-shaped pattern, but is not limited to this, and the adjustment pattern is provided at a position corresponding to the wafer mark W1 (W2, W3) of the semiconductor wafer 18. If the pattern can be aligned with the mask in the XY plane and can be used as a reference for performing the calibration based on the distance from the reference position of the mask mark, the pattern can be used. It is not limited.

  Furthermore, in the above embodiment, the mounting angle α of the CCD camera and the illumination light source is set to 30 degrees, but is not limited thereto.

It is an illumination figure which shows the positioning device which concerns on embodiment of this invention. It is a top view of a semiconductor wafer, and is a top view which shows the position of the division for every chip, and the wafer mark for every chip. (A) is a top view of a mask, (b) is the sectional view on the AA line of Fig.3 (a). It is an enlarged plan view of a mask mark showing a relative relationship between the illumination area and the visual field area of the CCD camera. It is a front view of an alignment unit. It is a top view which shows the detection state of the mask mark by the alignment unit, and the adjustment mark of the adjustment wafer. It is a figure which shows the positional relationship of the mask mark and the adjustment mark of an adjustment wafer.

Explanation of symbols

W1 to W3 Wafer mark WC1 to WC3 Adjustment mark WC1v to WC3v First linear pattern WC1h to WC3h Second linear pattern M1 to M3 Mask mark LD Light emitting diode 10 Semiconductor positioning device 12 Surface plate 14 Support column 16 Top plate 16A Opening 18 Semiconductor wafer 20 Moving stage 22 Work stage 24 Base 26 First slider 28 X-axis sliding device 30 Second slider 32 Y-axis sliding device 34 Work stage 36 Wafer chuck 38 Mask chuck 40 Mask 40A Peripheral part 40B Membrane part 40C Mask pattern part 40D Notch part 40E Global alignment mark 42 Mask θ axis base 44 Mask Z axis direction moving mechanism 46 XY table for mask 50 Alignment unit Second illumination light source unit 54 CCD camera 54A viewing area 60 the first through-hole (main through-hole)
62 Second through hole (sub through hole)
64 Third through hole (sub through hole)
66 Fourth through hole (sub through hole)
70 partition (first partition)
72 Partition (second partition)
74 XY table for camera (table for image sensor)
76 Housing 78 Illumination optical system 80 Condensing lens

Claims (5)

  Illumination means for irradiating a semiconductor wafer and an imaging region of a mask arranged so as to overlap the semiconductor wafer with a predetermined angle α, and reflection of light emitted from the illumination means to the semiconductor wafer and the mask Incidence of light, an imaging means for imaging a wafer mark for positioning formed on the semiconductor wafer and a mask mark formed on the mask, and image processing of imaging data obtained by imaging of the imaging means, and the wafer mark The semiconductor by the alignment apparatus comprising: a recognition unit that recognizes a relative position of the wafer mark to the mask mark; and a position control unit that controls a relative position of the wafer mark and the mask mark based on a recognition result of the recognition unit Corresponding to a wafer mark of the semiconductor wafer in a method of calibrating a gap detection value between a wafer upper surface and the mask upper surface Provided with an adjustment mark, and when the relative position with the mask is aligned, the adjustment mark is in a direction in which the shadow of the mask mark by the illumination means extends with respect to a reference position of the mask mark. An adjustment wafer prepared so as to have a portion separated by a predetermined distance L when viewed from a direction orthogonal to the upper surface of the mask is prepared, and the reference position of the mask mark viewed from the imaging means and the adjustment wafer A gap detection value calibration method, comprising: calibrating the gap detection value based on a recognition result by the recognition means with a true gap value between the mask and the adjustment wafer determined from a distance to a part.   The adjustment mark of the adjustment wafer is parallel to a plane including the optical axis of light irradiated by the illumination unit and the optical axis of the imaging unit when the mask and the adjustment wafer are aligned. A cross-shaped pattern including a first linear pattern set to be and a second linear pattern set to be orthogonal to the first linear pattern, the adjustment The gap detection value calibration method according to claim 1, wherein the portion of the wafer is set on the second linear pattern.   When the set value of the gap between the upper surface of the semiconductor wafer and the upper surface of the mask is g, the predetermined distance L when the mask is in alignment with the adjustment wafer is set to the set value g of the gap. G = L · tan α is established in the meantime, and the calibration is performed in a state where the gap value between the upper surface of the wafer for adjustment and the upper surface of the mask is the set value g. The gap detection value calibration method according to claim 1 or 2. The position control means calculates a pixel resolution in the gap direction between the wafer mark and the mask mark on a piezoelectric basis, and calculates a gap between the wafer mark and the mask mark from the calculation result. The positioning device according to any one of claims 1 to 3. The positioning apparatus according to claim 1, wherein the mask is configured by a stencil mask used for an exposure machine or an ion implantation machine.

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