JP2007295364A - Pll circuit and semiconductor device provided with pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily generate a clock including a jitter component having frequency characteristics adjusted, in a small circuit scale. <P>SOLUTION: A phase comparator 11a compares the phase of an input reference clock signal CKR with the phase of a signal fed back from a frequency divider 14 to output an output signal corresponding to the phase difference to a charge pump 16. A low pass filter 12a detects a low frequency component of an output signal of the charge pump 16 and outputs the detected component to a voltage controlled oscillator 13. The voltage controlled oscillator 13 outputs an output signal CKF of an oscillation frequency controlled on the basis of an output voltage of the charge pump 16, and the frequency divider 14 divides the frequency of the output signal CKF to output it to the phase comparator 11a. A wiring part 15 induces noise from the outside, and a low band component of the noise is caused to pass an LPF 31 with a switch and is added to the output signal of the charge pump 16 through a switch part 32, whereby the oscillation frequency of the output signal CKF is fluctuated by the noise. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit and a semiconductor device including the PLL circuit, and more particularly to a PLL circuit for generating jitter and a semiconductor device including the PLL circuit.

  In recent years, the transfer rate of data between devices has been increased, and transmission at a high data rate has been realized. In such a high data rate transmission, in parallel transmission, it becomes difficult to secure a skew between parallel signals as the speed increases, and thus the limit of the transfer speed has become apparent. For this reason, serial transmission is gradually being used for high-speed transmission. Jitter characteristics are important in high-speed serial transmission. The fluctuation of the signal, which was not a problem in the low-speed transmission, becomes obvious as the transmission error increases as the speed increases. When this jitter increases to some extent, data transmission cannot be performed normally.

  When a certain amount of jitter is present in the transmitter, the jitter generated by the signal line frequency characteristics and ISI (Inter Symbol Interference) is superposed along with the signal transmission. In the receiver, it is necessary to receive a signal in which jitter generated in the transmitter and jitter superimposed during transmission are added, and to reproduce the original digital signal to be transmitted. Therefore, it is required to measure the jitter tolerance of the receiver in the transmission system.

  One method of measuring jitter tolerance is to add a jitter component to the data. In this case, the data is phase-modulated or FM-modulated and the data is sent to the serial I / F device to test whether the device CDR (Clock and Data Recovery) can receive it normally. In this test, it is necessary to create a measurement environment for applying jitter components by modulating data.

  On the other hand, there is a method of putting a jitter component on the clock side supplied to the CDR. Receiving normal data using a CDR that operates with a clock modulated with jitter is the same as receiving data modulated with jitter with a CDR that operates with a normal clock, and the same test is possible. It becomes. Even in this test method, a measurement environment must be established.

  By the way, in a transmission system, a PLL circuit is often used to generate a transmission / reception timing clock. The PLL circuit is a circuit that inputs a reference clock and outputs a clock having a frequency multiplied by the reference clock. In such a PLL circuit, it is common to generate a clock having a frequency multiplied by a voltage controlled oscillator (VCO). A technique is known in which a signal generator is attached immediately before the voltage controlled oscillator, the frequency of the output signal output from the voltage controlled oscillator is fluctuated, and a clock including a jitter component is generated (for example, Patent Documents). 1 and 2).

  In the PLL circuit described in Patent Document 1, a signal output at a frequency corresponding to the voltage of the control signal from the voltage controlled oscillator is frequency-divided by a frequency divider, and this frequency-divided signal and the reference signal output from the reference signal generator The signal is input to a phase frequency comparator. An error signal corresponding to the phase difference between the divided signal and the reference signal is extracted from the output signal of the phase frequency comparator by a low-pass filter, and the error signal and the modulation signal output from the modulation signal generator are added by an adder. to add. The added signal is input to the voltage controlled oscillator as a control signal. The modulation signal generator outputs to the adder a modulation signal having a frequency corresponding to the specified jitter frequency and having an amplitude corresponding to the specified jitter amount. Thus, the output signal output from the voltage controlled oscillator has a fluctuation in frequency, and a clock including a jitter component is generated.

  Further, the PLL circuit described in Patent Document 2 includes an adder that adds signals from a signal generator in a phase locked loop including a phase comparator, a low-pass filter, and a voltage controlled oscillator. According to the PLL circuit having such a configuration, various jitter simulations can be performed according to signal patterns such as a sine wave, a triangular wave, and a frequency modulation wave from the signal generator.

JP 2000-230953 A (FIG. 2) JP-A-2-252316 (FIG. 1)

  Conventionally, a device reception test is performed by putting a jitter component on data or a clock, but a device corresponding to a measuring instrument for performing jitter modulation on the clock generator or the data generator is required. For example, according to the technique described in Patent Document 1, a controllable modulation signal generator is required. Further, according to the technique described in Patent Document 2, an adder for adding signals from the signal generator is required, and it is necessary to incorporate a signal generator or to provide an input terminal from the signal generator. It was. However, with such a configuration, there is a concern that the circuit scale may increase, especially considering that a clock with jitter is easily generated by being incorporated in an LSI or the like.

  A PLL circuit according to an aspect of the present invention includes a phase comparator that compares the phase of an input reference signal and the output signal of a divider to be fed back and outputs an output signal corresponding to the phase difference, and the phase comparison A filter unit that passes a low-frequency component of the output signal of the filter, a voltage-controlled oscillator that generates an oscillation signal having an oscillation frequency controlled based on the output voltage of the filter unit, and the phase obtained by dividing the oscillation signal A PLL circuit including the frequency divider that outputs to a comparator, comprising: a wiring unit that induces noise from outside; and a low-pass filter (LPF) that is connected to the wiring unit, and noise induced in the wiring unit The signal is configured to be added to the output signal of the filter unit through the LPF.

  According to the present invention, by adding a wiring section for inducing noise from the outside and an LPF to a conventional PLL circuit, a clock including a jitter component whose frequency characteristics are adjusted can be easily generated with a small circuit scale. Can do.

  FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention. In FIG. 1, the PLL circuit includes a phase comparator 11, a filter unit 12, a voltage controlled oscillator 13, a frequency divider 14, and a wiring unit 15. The phase comparator 11 compares the phase of the input reference clock signal CKR and the signal fed back from the frequency divider 14 and outputs an output signal corresponding to the phase difference to the filter unit 12. The filter unit 12 detects a low frequency component of the output signal of the phase comparator 11 and outputs it to the voltage controlled oscillator 13. The voltage controlled oscillator 13 generates an oscillation signal having an oscillation frequency controlled based on the output voltage of the filter unit 12 as an output signal CKF. The frequency divider 14 divides the output signal CKF and outputs it to the phase comparator 11. The wiring unit 15 connects one end Q of the wiring of the wiring unit 15 to the output P of the filter unit 12 so as to induce noise from the outside and add it to the output signal of the filter unit 12.

  In the PLL circuit configured as described above, noise induced from the outside is added to the output signal of the filter unit 12 and input to the voltage controlled oscillator 13, so that the oscillation frequency of the output signal CKF generated by the voltage controlled oscillator 13 Fluctuates due to noise. That is, a jitter component due to noise is added to the output signal CKF.

  According to such a PLL circuit, the jitter tolerance test is performed by supplying the output signal CKF, which is a clock subjected to jitter modulation, to the CDR or the like without creating a measurement environment in which jitter is applied to the data and the clock. It can be done easily. At this time, it is possible to generate a clock with jitter with a simple circuit configuration without the need for a modulation signal generator in the prior art. Since the circuit configuration is extremely simple, it is particularly suitable for incorporation in a semiconductor device.

  FIG. 2 is a block diagram showing the configuration of the PLL circuit according to the first exemplary embodiment of the present invention. The PLL circuit of FIG. 2 includes a phase comparator 11a, a voltage controlled oscillator 13, a frequency divider 14, a wiring unit 15, a charge pump 16, and a low-pass filter 12a. The basic operation is the same as that of the PLL circuit of FIG. is there. 2, the same reference numerals as those in FIG. 1 represent the same items, and the description thereof is omitted. The output of the phase comparator 11 a is input to the charge pump 16, and the output of the charge pump 16 is connected to one end P of the low-pass filter 12 a, the input of the voltage controlled oscillator 13, and one end Q of the wiring unit 15. The phase comparator 11a compares the phases of the input reference clock signal CKR and the signal fed back from the frequency divider 14, and outputs an up signal or a down signal with a pulse width corresponding to the comparison result. The charge pump 16 outputs a positive or negative current pulse according to the up signal or the down signal. These current pulses are integrated by the low-pass filter 12a and output to the voltage controlled oscillator 13 as a control signal from which the high frequency component has been cut. This control signal includes fluctuations due to the noise signal induced by the wiring section 15. become. The voltage controlled oscillator 13 generates an oscillation signal having an oscillation frequency based on the control signal as an output signal CKF. Since the control signal includes fluctuation due to the noise signal, the output signal CKF includes a jitter component.

  Next, details of the wiring section 15 will be described. The wiring unit 15 is disposed in the vicinity of the wiring 21 that generates noise. The wiring 21 that generates noise is preferably a power line 22 as shown in FIG. 3 or a GND line 23 as shown in FIG. The power supply line 22 or the GND line 23 is, for example, a power supply line or a GND line in a semiconductor device in which a PLL circuit is built, and is a wiring that generates noise in accordance with the operation of the semiconductor device. Further, as shown in FIG. 5, the wiring part may be branched into a wiring part 15 a and a wiring part 15 b, and each may be arranged close to the power supply line 22 and the GND line 23.

  As described above, by arranging the wiring portion 15 in the vicinity of the wiring 21 that generates noise (the power supply line 22, the GND line 23, etc.), noise is not generated in the wiring portion 15 by capacitive coupling and / or electromagnetic induction. Inductively connected. The induced noise becomes a jitter component at the oscillation frequency of the output signal CKF of the voltage controlled oscillator 13. In addition, if it is set as a structure as shown in FIG. 5, a bigger noise can be induced | guided | derived.

  The wiring unit 15 includes switch units 20a to 20n. The wiring in the wiring section 15 is divided according to the number of switch sections, and the switch section 20a is arranged between the divided wirings so that the effective length of the wiring (the length of the wiring that induces noise) can be adjusted. ~ 20n are inserted respectively. And opening / closing of the switch parts 20a-20n is each controlled by a control signal not shown. If the switch portions 20a, 20b,... 20n are arranged from the side closer to one end Q of the wiring of the wiring portion 15, the length of the wiring is the shortest when all the switch portions are opened, and the switch portions 20a, 20b,. By closing 20n in order, the length of the wiring is sequentially increased. In this way, the length of the wiring is changed by opening and closing the switch units 20a to 20n, and the amplitude of the induced noise is controlled. By controlling the amplitude of noise, the jitter amount of the output signal output from the voltage controlled oscillator 13 can be made variable.

  Next, the configuration of the switch unit will be described. FIG. 6 is a diagram illustrating a configuration of the switch unit 20i (i = a to n). The switch unit 20i includes switch elements SW1, SW2, and SW3. The switch elements SW1 and SW2 are inserted in cascade between one end N1 of the wiring and one end N2 of the other wiring. The switch element SW3 is connected between the connection point of the switch elements SW1 and SW2 and the ground or the power supply (in FIG. 6, it is connected to the ground). The switch elements SW1 and SW2 and the switch element SW3 perform reverse opening / closing operations. That is, when the switch elements SW1 and SW2 are “ON” as shown in FIG. 6A, the switch element SW3 is “OFF”, and as shown in FIG. 6B, the switch elements SW1 and SW2 are “OFF”. ", The switch element SW3 is controlled to be" ON ".

  When the switch unit is shown in FIG. 6B, the switch element SW3 is turned on so as to cope with the case where the switch elements SW1 and SW2 are not completely cut off due to capacitive coupling or the like. Thereby, the connection point of the switch elements SW1 and SW2 is connected to the GND potential, and noise transmitted by capacitive coupling of the open switch elements SW1 and SW2 can be cut off.

  Next, a specific circuit configuration of the switch unit will be described. FIG. 7 is a diagram illustrating a specific circuit configuration of the switch unit 20i (i = a to n). The switch elements SW1, SW2, and SW3 in FIG. 6 are configured by NMOS transistors MN1, MN2, and MN3, respectively. Further, a control signal CNT for controlling opening / closing of the switch unit is applied to the gates of the NMOS transistors MN1 and MN2, and a signal obtained by inverting the control signal CNT by the inverter INV is applied to the gate of the NMOS transistor MN3. The NMOS transistors MN1 and MN2 and the NMOS transistor MN3 are controlled to open and close by the control signal CNT. Since this switch section can be easily configured with three NMOS transistors and one inverter, the circuit scale can be reduced.

  Further, as shown in FIG. 8, the switch elements SW1, SW2, and SW3 in FIG. 6 may be configured by PMOS transistors MP1, MP2, and MP3, respectively. In this case, the connection point of the PMOS transistors MP1, MP2, and MP3 is connected to the power supply VDD. A control signal CNT for controlling opening / closing of the switch unit is applied to the gate of the PMOS transistor MP3, and a signal obtained by inverting the control signal CNT by the inverter INV is applied to the gates of the PMOS transistors MP1 and MP2. The PMOS transistors MP1 and MP2 and the PMOS transistor MP3 are controlled to be opened and closed by the control signal CNT. Since this switch section can be easily configured with three PMOS transistors and one inverter, the circuit scale can be reduced.

  Further, as shown in FIG. 9, the switch elements SW1, SW2, and SW3 in FIG. 6 are transferred by respective transfer gates including the NMOS transistor MN4 and the PMOS transistor MP4, the NMOS transistor MN5 and the PMOS transistor MP5, and the NMOS transistor MN6 and the PMOS transistor MP6. It may be configured. The gates of the NMOS transistors MN4, MN5, and the PMOS transistor MP6 are supplied with a control signal CNT that controls the opening and closing of the switch unit. The gates of the NMOS transistors MN6, PMOS transistors MP4, and MP5 are inverted by the inverter INV. Signal is given. The NMOS transistors MN4 and MN5, the PMOS transistors MP4 and MP5, and the NMOS transistor MN6 and the PMOS transistor MP6 are controlled to open and close by the control signal CNT. By adopting a transfer gate configuration, it is possible to reliably perform on / off control over a wide input range.

  FIG. 10 is a block diagram showing the configuration of the PLL circuit according to the second exemplary embodiment of the present invention. 10, the same reference numerals as those in FIG. 2 represent the same items, and the description thereof is omitted. The PLL circuit of FIG. 10 has an LPF with a switch (low-pass filter) 31 connected to one end of the wiring unit 15 and a switch unit 32 disposed between the LPF 31 with switch and one end (node) P of the low-pass filter 12a. It is the structure which added. Further, the noise generation circuit 50 is configured by the wiring unit 15 and the LPF 31 with switch. As in FIG. 2, the basic operation is that the charge pump 16 outputs a positive or negative current pulse according to the up signal or the down signal input from the phase comparator 11a, and these current pulses are integrated by the low-pass filter 12a. Then, it is output to the voltage controlled oscillator 13 as a control signal from which the high frequency component has been cut. Further, the control signal includes fluctuation due to the noise signal induced by the noise generation circuit 50. The LPF 31 with a switch extracts only a desired frequency component from the noise input from the wiring unit 15 to the node P1 and outputs it to the node P that is the output terminal of the low-pass filter 12a via the switch unit 32. The switch unit 32 is provided to separate the LPF 31 with switch and completely block noise injection during the actual operation of the PLL circuit. Therefore, the switch unit 32 can be replaced with only the switch of the LPF 31 with switch. Note that the wiring unit 15 is preferably provided in the vicinity of a power supply, a ground, or a circuit that generates noise, such as a CPU or RAM, for the purpose of picking up noise.

  Next, details of the LPF 31 with switch will be described. FIG. 11 is a circuit diagram showing a configuration example of the LPF with switch. In FIG. 11, the LPF 31 with switch receives the noise input from the wiring unit 15 at the node P1, and outputs it to the node P2 according to the control of the control signal CT1. The LPF 31 with a switch includes a variable resistor section 40, a capacitor C1, an inverter INV1, and NMOS transistors MN11, MN12, and MN13 that form a switch. The resistance of the variable resistance unit 40 and the capacitor C1 constitute an LPF (low pass filter). As will be described later, the cutoff frequency of the LPF can be changed by changing the resistance value in the variable resistor section 40. By changing the cutoff frequency, it is possible to inject noise having a desired frequency component into the node P. Further, when outputting noise to the node P2, by giving “1” (High level) to the control signal CT1, the NMOS transistors MN11 and MN12 are turned ON, and a signal obtained by inverting the control signal CT1 by the inverter INV1 is supplied to the gate. The given NMOS transistor MN13 is turned off. Therefore, the noise input to the node P1 of the LPF 31 with switch is output to the node P2. On the other hand, when noise injection is unnecessary, by setting the control signal CT1 to “0” (Low level), the NMOS transistors MN11 and MN12 are turned off and the NMOS transistor MN13 is turned on to drop the noise to the ground ( Can escape).

  FIG. 12 is a circuit diagram showing another configuration example of the LPF 31 with switch. In FIG. 12, the LPF 31 with a switch includes a variable resistor section 40, a capacitor C1, an inverter INV1, and PMOS transistors MP11, MP12, and MP13 that form a switch. The LPF with switch of FIG. 12 is different in that the NMOS transistor in the LPF with switch of FIG. 11 is replaced with a PMOS transistor and noise is dropped to the power supply VDD. The operation is the same as that of the LPF with a switch in FIG. Although not shown, it is also possible to inject noise at an intermediate potential other than the power supply VDD and ground by using a transfer gate in which the MOS transistor of the LPF with switch is a CMOS.

  Next, the variable resistance unit 40 will be described. As shown in FIG. 13, the variable resistor section 40 includes a plurality of MOS switches SWR1, SWR2,..., SWRm and a plurality of resistance elements R1-1, R1-2, R2,. . .., 4m with switches composed of MOS switches and resistance elements connected in series are arranged in parallel. In FIG. 13, resistance elements R1-1 and R1-2 are connected in series, and constitute a resistor 41 with a switch together with the MOS switch SWR1. Further, the resistor element Ri (i = 2 to m) and the MOS switch SWRi constitute a switch-attached resistor 4i. One or a plurality of MOS switches can be turned on and off by the selection signal SEL. Therefore, the noise input from the node P1 is output to the node A through one or a plurality of switched resistors selected by the selection signal SEL. That is, the cut-off frequency of the LPF can be changed by changing the combined resistance between the node P1 and the node A by the selection signal SEL.

  With the noise generation circuit 50 configured as described above, it is possible to extract only a desired frequency component from the noise induced in the wiring section 15 provided in the vicinity of the noise generation source and inject it into the node P. The desired frequency component can be selected by setting the selection signal SEL. Further, noise injection can be controlled by the control signal CT1. If it is desired to always inject noise, the LPF 31 with a switch may be a simple LPF having no switching function. Further, if a cutoff frequency for obtaining a desired frequency component can be determined in advance, the variable resistor section 40 can be configured by a fixed resistor, and the configuration in which the resistance value can be varied by the selection signal SEL can be omitted. .

  FIG. 14 is a block diagram showing a configuration of a PLL circuit according to the third example of the present invention. The PLL circuit of FIG. 14 is configured to include a plurality of noise generation circuits of the PLL circuit of the second embodiment, and the plurality of noise generation circuits are represented as 51, 52,. 14, the same reference numerals as those in FIG. 10 represent the same items, and the description thereof is omitted. The basic operation is the same as that of the PLL circuit of FIG. By providing a plurality of noise generation circuits, the wiring sections 15 constituting the noise generation circuits 51, 52,..., 5n are arranged near the power supply, the ground, or near the circuits that generate noise such as CPU and RAM. It can be deployed in various places. The outputs of the plurality of noise generation circuits 51, 52,... 5n are collected in the switch unit 32. The switch unit 32 performs ON / OFF control of the connection between the outputs of the plurality of noise generation circuits 51, 52,. That is, the LPF 31 with a switch in each of the noise generating circuits 51, 52,... 5n is separated in the same manner as in the second embodiment, and is provided to completely block noise injection during the actual operation of the PLL circuit.

  By providing a plurality of noise generation circuits as shown in FIG. 14, various noises can be injected into the node P, and noise having a desired frequency component can be easily injected into the contact P. In addition, if a plurality of noise generation circuits having the same noise source are provided, the magnitude of noise can be controlled.

  Note that the noise generation circuit 5j (j = 1 to n) may include a decoder 30 as shown in FIG. 15, and may generate a selection signal SEL by decoding data (not shown) given from the outside. .

  As described above, in the second and third embodiments, noise having a desired frequency component can be injected into the voltage controlled oscillator 13 as necessary, and the output signal output from the voltage controlled oscillator 13 The amount of jitter is controlled variable.

  The present invention has been described with reference to the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and those skilled in the art within the scope of the invention of each claim of the present application claims. It goes without saying that various modifications and corrections that can be made are included.

It is a block diagram which shows the structure of the PLL circuit which concerns on embodiment of this invention. 1 is a block diagram showing a configuration of a PLL circuit according to a first exemplary embodiment of the present invention. It is a figure which shows the example of arrangement | positioning of a wiring part. It is a figure which shows the other example of arrangement | positioning of a wiring part. It is a figure which shows the further another example of arrangement | positioning of a wiring part. It is a figure which shows the structure of a switch part. It is a circuit diagram of the switch part comprised by the NMOS transistor. It is a circuit diagram of the switch part comprised by the PMOS transistor. It is a circuit diagram of the switch part comprised by the transfer gate. It is a block diagram which shows the structure of the PLL circuit which concerns on the 2nd Example of this invention. It is a circuit diagram of LPF with a switch comprised with the NMOS transistor. It is a circuit diagram of LPF with a switch comprised with the PMOS transistor. It is a circuit diagram of a variable resistance part. It is a block diagram which shows the structure of the PLL circuit which concerns on the 3rd Example of this invention. It is a circuit diagram which shows the structural example of a noise generation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 11a Phase comparator 12 Filter part 12a Low pass filter 13 Voltage control oscillator 14 Frequency divider 15, 15a, 15b Wiring part 16 Charge pump 20a-20n 32 Switch part 21 Wiring 22 Power supply line 23 GND line 30 Decoder 31 LPF with switch
32 Switch unit 40 Variable resistor unit 41 to 4m Switched resistor 50, 51 to 5n Noise generation circuit INV, INV1 Inverters MN1 to MN6, MN11 to MN13 NMOS transistors MP1 to MP6, MP11 to MP13 PMOS transistors SW1 to SWn, SWR1 to SWRm Switch element C1 Capacitors R1-1, R1-2, R2 to Rm Resistor SEL selection signal CNT Control signals P, P1, P2, A node

Claims (9)

A phase comparator that compares the phase of the input reference signal and the output signal of the divider to be fed back and outputs an output signal corresponding to the phase difference, and a filter that passes the low-frequency component of the output signal of the phase comparator A voltage controlled oscillator that generates an oscillation signal having an oscillation frequency controlled based on an output voltage of the filter unit, and the frequency divider that divides the oscillation signal and outputs the divided signal to the phase comparator. In the PLL circuit provided,
A wiring section for inducing noise from the outside,
A low-pass filter (hereinafter referred to as LPF) connected to the wiring section,
A PLL circuit configured to add a noise signal induced in the wiring unit to an output signal of the filter unit through the LPF.   The PLL circuit according to claim 1, wherein the LPF is configured such that a cutoff frequency of the LPF can be controlled.   The PLL circuit according to claim 2, wherein the LPF includes a switch for intermittently outputting an output signal of the LPF.   The PLL circuit according to claim 3, comprising a plurality of sets of the wiring section and the LPF.   The PLL circuit according to claim 1, wherein the wiring portion includes a wiring that is wired close to a noise generation source.   The PLL circuit according to claim 5, wherein the wiring unit includes one or more switch units that can adjust an effective length of the wiring.   The switch unit is connected between the first and second switch elements connected in cascade between the wirings, and a connection point between the first and second switch elements and a ground or a power source. The PLL circuit according to claim 6, further comprising a third switch element that performs an opening / closing operation opposite to the first and second switch elements.   8. The PLL circuit according to claim 7, wherein the first, second and third switch elements are MOS transistors whose opening and closing are controlled by a control signal applied to a gate.   A semiconductor device comprising the PLL circuit according to claim 1.

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