JP2007293857A - Pc card controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PC card controller capable of recognizing new kinds of expansion cards. <P>SOLUTION: The PC card controller has an acquiring part for acquiring the ID information of a connected card using a technique compliant with standards; a first recording part for recording the card information and the ID information of one or more kinds of PC cards compliant with standards; and a second recording part for recording the card information and the ID information of one or more kinds of expansion cards not compliant with the standards. The PC card controller includes a PC card identifying part for identifying the kind of the connected card based on the ID information of the connected card and at least the ID information recorded in the second recording part, of the ID information recorded in the first and second recording parts, then outputting the result of the identification, and outputting the card information of the connected card; and a signal conversion part for establishing, based on the result of the identification, a line for communicating signals to the connected card using a format compliant with the standards. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to identification of a PC card conforming to PCMCIA.

  2. Description of the Related Art Conventionally, personal computers, particularly notebook personal computers, are known that include a PC card identification device (so-called PC card slot) compliant with PCMCIA.

  The female connector provided on the side of the short side of the PC card conforming to PCMCIA includes first and second card detection signals (in PCMCIA) among the plurality of pins of the male connector provided in the PC card control device. The first and second connection holes corresponding to the pins through which CD1 # and CD2 # flow, and hereinafter simply referred to as CD1 # and CD2 #, and the first and second voltage selection signals (VS1 in PCMCIA). The third and fourth connection holes corresponding to VS1 # and VS2 #) are prepared.

  Inside the PC card, the wiring connected to the first and second connection holes is grounded or connected to at least one of the third and fourth connection holes. In the PC card control device, both the CD1 # and CD2 # are pulled up to the high level. When the PC card is connected to the PC card controller, the potentials of the CD1 # and CD2 # are lowered to the low level. The PC card control device detects the connection of the PC card from this potential change.

  When the PC card controller detects that the PC card is connected, the state of CD2 #, CD1 #, VS2 # and VS1 # when the potential of VS1 # flowing through the third connection hole is set to the high level, and The state of CD2 #, CD1 #, VS2 # and VS1 # when the potential of VS2 # flowing through the fourth connection hole is set to the high level is detected, and the state of these signal lines is used as identification information to identify the type of PC card (use The signal level to be used and the bit width of the bus).

  For example, as a PC card controller for recognizing a new PC card, CD2 # and CD1 # when the potentials of VS1 # and VS2 # flowing in the third and fourth connection holes are selectively set to the high level as described above. , VS2 # and VS1 # when the potential state of the spare card determined by PCMCIA matches and the signal state of a specific terminal other than the above satisfies a predetermined condition, A device that recognizes an expansion card (smart card) whose width and drive voltage are specified has been proposed (see Patent Document 1).

JP 2001-75746 A

  However, the PC card control device disclosed in Patent Document 1 requires a special identification algorithm for an expansion card in order to investigate the signal state of a specific terminal in addition to the normal identification information acquisition process. Increase.

  An object of this invention is to provide the PC card control apparatus which recognizes an expansion card more easily.

  The PC card control device according to the present invention includes an identification information acquisition unit that acquires identification information from a connected card in accordance with a standard, and card information about one or more types of PC cards that conform to the standard, and each card. A first recording unit in which identification information corresponding to the information is recorded, and a second information in which identification information corresponding to the card information is recorded together with card information about one or more types of expansion cards that do not comply with the standard. At least a second recording unit among the identification information acquired by the identification information acquisition unit for the connected card and the identification information recorded in the first recording unit and the second recording unit. PC card identification that identifies the type of card connected from the identification information recorded on the card, and outputs card information about the connected card together with the identification result. Characterized in that a part.

  The first PC card control device of the present invention can recognize an expansion card based on identification information obtained by a technique based on a standard without adding a special identification algorithm.

(1) Embodiment 1
The PC card control apparatus 100 according to Embodiment 1 identifies an expansion card by the same identification method as that of a PC card conforming to PCMCIA (which means that no other special processing is required). The identification information not used for the PC card conforming to the PCMCIA is used as the identification information for the expansion card. As a result, the expansion card is identified without adding a special expansion card identification algorithm.

  Further, in the PC card control device 100, for example, when the signal level used by the expansion card is changed from 5V to 3.3V and the bit width of the bus is changed from 16 bits to 32 bits, the expanded expansion card is changed. For the purpose of enabling correct recognition, a configuration that can update externally the identification information for identifying the expansion card and the card information for specifying the type of the expansion card such as the drive voltage and bus bit width is adopted. To do. As a result, various types of expansion cards are identified easily and flexibly.

  FIG. 1 is a diagram illustrating a configuration of a computer system 1 including a PC card control device 100 according to the first embodiment. The computer system 1 includes a CPU 10, a ROM 11, a RAM 12 in which an OS program is stored, an operation unit 13 including a keyboard and a mouse, a display 14, a PC card controller 100 for a PC card compliant with PCMCIA, and the PC card In addition to the first control program (see FIG. 10) and the second control program (see FIG. 12) for the control device 100, a hard disk (denoted as HD in the figure) 15 in which various application programs and data are stored. Are connected via the PCI bus 50.

  Connected to the PC card control device 100 is a flash ROM 200 that stores the identification information and card information of the expansion card registered by executing the control program of the PC card control device 100. In FIG. 1, the flash ROM 200 is externally attached, but may be built in the PC card control device 100.

  When the computer system 1 is started up, the CPU 10 reads out and executes an OS program stored in the ROM 11 to the RAM 12 and initializes each unit including the PC card control device 100.

  The flash ROM I / F 150 also includes identification information for identifying an expansion card stored in the flash ROM 200 and the expansion card such as a drive voltage and a bus bit width when the computer system 1 is turned on. The card information for specifying the type is written into the expansion card register 182.

  The PC card control apparatus 100 recognizes not only the PC card 250 conforming to PCMCIA but also the smart card 310 connected to the connector 190 via the adapter 300 (see (a) and (b) of FIG. 2). Can do.

  The PC card control device 100 is roughly divided into a PC card identification unit 160 that identifies the type of card connected to the connector 190, and a card connected to the connector 190 based on the identification result in the PC card identification unit 160. And a signal conversion unit 105 that establishes a line so as to exchange signals in a format compliant with PCMCIA.

  The function of each part constituting the signal conversion unit 105 is as follows. The PCI interface 110 connects the PCI bus 50 and an internal bus (not shown in detail) of the PC card control device 100. The PCMCIA controller 120 exchanges data with the PC card 250 connected to the connector 190 via the selector 140 as shown in FIG. As an expansion card, the smart card controller 130 exchanges data between the PCMCIA controller 120 and the smart card 310 when the smart card 310 is connected via the adapter 300 as shown in FIG. . The selector 140 connects the PCMCIA controller 120 and the connector 190 based on the value of the 1-bit select signal SEL output from the PCMCIA controller 120, or connects the PCMCIA controller 120 to the connector 190 via the smart card controller 130.

  As described above, the flash ROM • I / F 150 receives the identification information (the first register (4-bit data) and the identification information of the smart card 310 that is the expansion card from the flash ROM 200 when the computer system 1 including the PC card control device 100 is started. Information on the second register (4-bit data)) and the card type (6-bit data) is read and written into the expansion card register 182 in the PC card identification unit 160.

  The PC card identification unit 160 identifies which of the 12 types of PC cards specified in PCMCIA and the newly registered expansion card the card inserted into the connector 190 is, and the identification result Is output to the PCMCIA controller 120, and 6-bit card information specifying the type of card (such as drive voltage and bus bit width) specified based on the result is output to the PCMCIA controller 120. The configuration and operation of the PC card identification unit 160 will be described in detail later.

  3A is a diagram showing a state in which a PC card 250 conforming to PCMCIA is inserted into the connector 190, and FIG. 4A is a diagram illustrating a state in which the smart card 310 is connected to the connector 190 via the adapter 300 as an expansion card. It is a figure which shows the state inserted in. The female connector provided on the side of the short side of the PC card 250 and the adapter 300 includes the first and second card detection signals (CD1 # and CD2 in the PCMCIA) provided in the male connector 190 of the PC card control device 100. The first connection hole 251 and the second connection hole 252 that accept pins through which CD1 # and CD2 # flow, and the first and second voltage selection signals (VS1 # in PCMCIA) are defined below. VS2 # and VS2 #, and hereinafter, a third connection hole 253 and a fourth connection hole 254 for receiving pins through which VS1 # and VS2 # flow are prepared.

  The PC card 250 and the adapter 300 are actually provided with connection holes for receiving many pins provided in the connector 190 as shown in FIGS. 2A and 2B. 4 (a) and FIG. 4 (a), in order to show the internal wiring of the PC card control device 100, the PC card 250, and the adapter 300 in an easy-to-understand manner, Only the wiring to be connected is shown.

  Inside the PC card 250 and the adapter 300, the wiring connected to the first connection hole 251 and the second connection hole 252 is grounded, or at least of the third connection hole 253 and the fourth connection hole 254. Connected to one side. In addition, among the pins of the male connector 190 provided in the PC card control device 100, the potentials of the pins inserted into the first connection hole 251 and the second connection hole 252 are both pull-up circuits provided on the PC card control device 100 side. Pulled up to High level by C1 and C2. When the PC card 250 or the adapter 300 is connected to the PC card control apparatus 100, the potentials of CD1 # and CD2 # are lowered to the low level. The PC card identification unit 160 detects the connection of the PC card 250 or the adapter 300 from the potential changes of the CD1 # and CD2 #, performs card identification processing, and sends a card detection signal indicating that the card is connected to the PCMCIA. The data is output to the CPU 10 via the controller 120, the PCI interface 110 and the PCI bus 50.

  When the PC card identification unit 160 switches the CD1 # and CD2 # to the low level and detects the connection of the PC card 250 or the adapter 300 to the connector 190, the PC card identification unit 160 changes the potential of the VS1 # to the high level. The state of CD2 #, CD1 #, VS2 # and VS1 #, and the state of CD2 #, CD1 #, VS2 # and VS1 # when the potential of VS2 # is set to the high level are detected, and the state of these signals is determined. 4 bits + 4 bits in total representing 8 bits data (identification information) and No. defined in the card table 183 conforming to PCMCIA shown in FIG. 1-No. The 8-bit data (identification information) for the 12 types of PC cards up to 12 is compared with the 8-bit data (identification information) stored in the expansion card register 182 to identify the type of the corresponding card.

  FIG. 3B is a time chart showing the states of CD2 #, CD1 #, VS2 #, and CS1 # when the PC card 250 is connected to the PC card control device 100. FIG. 4 is a time chart showing the states of CD2 #, CD1 #, VS2 #, and VS1 # when a smart card 310 is connected to the PC card control apparatus 100 via an adapter 300.

  As shown in the figure, when the PC card 250 or the adapter 300 is connected to the PC card control apparatus 100, the levels of CD1 # and CD2 # are switched to the Low level. The PC card identification unit 160 of the PC card control apparatus 100 detects the insertion of the PC card 250 or the adapter 300 from the change in the levels of CD1 # and CD2 #, and sets the potential of VS1 # to the high level for a period of about 1 ms. . The first register 180 (see FIG. 1) included in the PC card identification unit 160 is in a state of CD2 #, CD1 #, VS2 #, and VS1 # at a timing about 0.8 ms after the potential of VS1 # is set to the high level. Latch.

  Next, the PC card identification unit 160 sets the potential of VS2 # to the high level for a period of about 1 ms. The second register 181 (see FIG. 1) included in the PC card identification unit 160 is in the state of CD2 #, CD1 #, VS2 #, and VS1 # at a timing about 0.8 ms after the potential of VS2 # is set to the high level. Latch.

  In the case of the PC card 250 shown in FIG. 3A, “0000” is latched in the first register 180, and “1010” is latched in the second register 181. As will be described below, the PC card identification unit 160 refers to the card table 183 shown in FIG. 5 (also shown in FIG. 1), and the PC card 250 is a card bus and is 3.3V. Or No. driven by X.XV. It recognizes that it corresponds to the card of 7. Note that the information about the type of card that is the card bus and is driven at 3.3V or X.XV is defined by 6-bit data prepared in advance in the card table. The 6-bit data is, in order from the upper bit, whether it is a 16-bit card, whether it is a 32-bit card, whether the drive voltage is 5V, and whether the drive voltage is 3.3V. , Represents whether or not the drive voltage is X.XV and whether or not the drive voltage is Y.YV. The PC card identification unit 160 displays the No. 7-bit data representing the type of the card 7 is output as card information to the CPU 10 via the PCI bus 50.

  On the other hand, in the case of the smart card adapter 300 shown in FIG. 4A, “0001” is latched in the first register 180 and “1110” is latched in the second register 181. The adapter 300 is not defined in the card table 183 shown in FIG. As will be described below, the PC card identification unit 160 prepares 8-bit data “0011110”, which is a combination of “0001” and “1110”, as identification information in the expansion card register 182, as well as the smart card 310. By preparing 6-bit data (card information) representing the type, the adapter 300 is recognized and 6-bit data specifying the type of card is output to the CPU 10 as card information via the PCI bus 50. .

  FIG. 6 shows possible connection patterns other than the connection patterns of the first connection hole 251 to the fourth connection hole 254 shown in the card table 183 shown in FIG. 5 and VS1 # and VS2 # individually at the connection pattern. 4 is a chart showing data of 8 bits in total, each of 4 bits latched in the first register 180 and the second register 181 when switched to a high level. The expansion card register 182 of the PC card identification unit 160 stores any one of the six patterns shown in FIG. 6 as 4-bit data obtained in the first register 180 and the second register 181. The The expansion card register 182 further stores 6-bit data for specifying the type of the expansion card (bus bit width or drive voltage).

  FIG. 7 is a diagram illustrating a configuration of the PC card identification unit 160. The PC card identification unit 160 is roughly divided into an identification information acquisition unit D that acquires identification information (8-bit data) of a card connected to the connector 190 in the first and second registers 180 and 181, and the identification information acquisition. A comparator 185 that compares the identification information acquired in the section D with the identification information recorded in the card table 183 as the first recording section and the expansion card register 182 as the second recording section, and outputs a comparison result; The card information detection unit 184 detects card information (6-bit data) for specifying the card type based on the comparison result and outputs the card information to the CPU 10.

  In the identification information acquisition unit D, the potential of the terminal 161 to which CD2 # is input is pulled up to a high level by the pull-up circuit C2 including the power source Vcc and the resistor 162, and the potential of the terminal 164 to which CD1 # is input. The potential is pulled up to a high level by a pull-up circuit C1 including a power source Vcc and a resistor 165. CD2 # and CD1 # input to the terminals 161 and 164 are input to the 2-input OR gate 167 via the buffer circuits 163 and 166, respectively.

  The output of the OR gate 167 is input to a DF / F (delay type flip-flop) 168. The output of the DF / F 168 is input to the DF / F 169 of the next stage. The inverted output terminal of the DF / F 169, the output of the DF / F 168, and the TIM signal line that switches to the high level when the timer 171 described below is started are the signals of the 3-input OR gate 170. Connected to the input terminal. The output terminal of the OR gate 170 is connected to the input terminal of the start signal ST # of the timer 171. As described later, when the adapter 300 with the PC card 250 or the smart card 310 is inserted into the connector 190 and the potentials of the CD1 # and CD2 # are switched from the high level to the low level, the OR gate 170 is temporarily A low level signal is output as a start signal ST #. The start signal is also output to the CPU 10 as a card detection signal.

  The timer 171 starts upon receiving the low level start signal ST #, and outputs signals T1, T2, L1 #, and L2 # of predetermined levels at a timing described later.

  A terminal 172 to which VS2 # is input is connected to a power supply Vcc through a resistor 173, and is also connected to a P-channel type MOSFET 175 and a buffer circuit 174 which are semiconductor switches. The T2 signal output from the timer 171 is input to the gate of the MOSFET 175.

  Similarly, a terminal 176 to which VS1 # is input is connected to a power supply Vcc via a resistor 177, and is connected to a P-channel type MOSFET 179 and a buffer circuit 178 which are semiconductor switches. A signal T 1 output from the timer 171 is input to the gate of the MOSFET 179.

  The four signals CD2 #, CD1 #, VS2 #, and VS1 # output from the buffer circuits 163, 166, 174, and 178 are input to the first register 180 and the second register 181, respectively. The signal L1 # output from the timer 171 is input to the latch terminal 180a of the first register 180. The first register 180 records the states of CD2 #, CD1 #, VS2 #, and VS1 # according to the input of the low level signal L1 #. The signal L2 # output from the timer 171 is input to the latch terminal 181a of the second register 181. The second register 181 records the states of CD2 #, CD1 #, VS2 #, and VS1 # in response to the input of the low level signal L2 #.

  FIG. 8 is a time chart showing CD1 #, CD2 #, signal ST # input to timer 171 and signals T1, T2, L1 #, L2 # output from timer 171. The timer 171 starts when the potential of CD1 # and CD2 # falls from the High level to the Low level and the Low level start signal ST # is input from the OR gate 170.

  As the timer 171 starts, the signal TIM switches to a high level. As a result, the signal ST # output from the OR gate 170 is switched to the high level. The timer 171 first switches the signal T1 to High level. As a result, the semiconductor switch 179 is turned off, and a high level signal is output to VS1 #. After about 0.8 ms, the timer 171 outputs a low pulse signal L1 #, and stores the state of the signal output from the buffer circuits 163, 166, 174, and 178 in the first register 180. Thereafter, the timer 171 switches T2 to High level instead of the signal T1. As a result, the semiconductor switch 175 is turned off, and a high level signal is output to VS2 #. After about 0.8 ms, the timer 171 outputs a Low pulse signal L2 #, and stores the state of the signal output from the buffer circuits 163, 166, 173, and 178 in the second register 181.

  Even when a high level signal is output to VS1 # and VS2 #, when VS1 # and VS2 # are grounded in the adapter 300 to which the PC card 250 or smart card 310 inserted into the connector 190 is attached. The apparent potential state of VS1 # and VS2 # is Low.

  When the timer 171 outputs a signal of a predetermined level at the timing described above, the potential states of CD2 #, CD1 #, VS2 #, and VS1 # are stored in the registers 180 and 181, respectively.

  Here, FIG. 7 will be referred to again. The expansion card register 182 includes 8-bit data (identification information) indicating the values of the first register 180 and the second register 181 specified when the adapter 300 in which the smart card 310 is mounted as an expansion card is connected, and the type of the card 6-bit data (card information) for specifying (the bus bit width and drive voltage) is stored. The expansion card register 182 outputs the 8-bit data (identification information) to the comparator 185, and outputs 6-bit data (card information) specifying the type to the card information detection unit 184.

  The card table 183 includes 8-bit data (identification information) indicating the values of the first register 180 and the second register 181 for a total of 12 types of cards defined in the card table 183 shown in FIG. 6-bit data (card information) for specifying the card type is stored. The card table 183 outputs 8-bit data of the 12 PC cards in parallel to the comparator 185 and outputs 6-bit data of the 12 PC cards to the card information detection unit 184.

  The comparator 185 includes a total of 8-bit data of 4 bits + 4 bits stored in the first register 180 and the second register 181 and a total of 13 cards output in parallel from the expansion card register 182 and the card table 183. Comparison is made with 8-bit data, and a comparison result signal for a total of 13 bits of 1 bit at the Low level is output when the card matches for each card. The comparison result signal is output to the PCMCIA controller 120 (see FIG. 1) and also to the card information detection unit 184.

  The card information detection unit 184 includes a selector 184a and a 6-bit register 184b. The selector 184a indicates the type of cards (bus bit width and corresponding driving voltage) for a total of 13 cards, one for the expansion card register 182 and 12 for the card table 183. Bit data is input in parallel. Then, for a card whose comparison result signal output from the comparator 185 is at a high level, 6-bit data representing the type of the card is output to the register 184b. A signal obtained by inverting the signal TIM is input from the timer 171 to the latch terminal of the register 184b. In the register 184b, after the timer 171 outputs the pulsed signal L2 # and the CD2 #, CD1 #, VS2 #, and VS1 # are stored in the second register 181, the signal TIM is switched to the low level at the same time. The 6-bit data output from the selector 184a is latched.

  The 6-bit data latched in the register 184b is, in order from the upper bit, whether it is a 16-bit card, whether it is a 32-bit card, whether the drive voltage is 5V, and whether the drive voltage is 3 .3V, whether the drive voltage is X.XV, and whether the drive voltage is Y.YV. “1” is set if applicable, and “0” is set if not applicable.

  The register 184b outputs the latched 6-bit data to the 3-state buffer 191. The 3-state buffer 191 uses the PCMCIA controller 120, the PCI interface 110, and the PCI as the data representing the type of the card connected to the connector 190 in response to the Low level card information request signal from the CPU 10. The data is output to the CPU 10 via the bus 50. The CPU 10 exchanges data with the card connected to the connector 190 based on the received information about the card type.

  FIG. 9 is a diagram illustrating a partial configuration of the PCMCIA controller 120. As shown in the figure, among the comparison results input from the PC card identification unit 160, the total of 8 bits of data stored in the registers 180 and 181 and 8 bits of data stored in the expansion card register 182 The comparison result is output through a buffer circuit 121 formed by connecting two CMOS inverters in series. That is, when the 8-bit data stored in the first register 180 and the second register 181 matches the 8-bit data stored in the expansion card register 182, a high level signal is output as the select signal SEL. The On the other hand, if they do not match, a low level signal is output as the select signal SEL.

  Here, FIG. 1 will be referred to again. Upon receiving the high level select signal SEL from the PCMCIA controller 120, the selector 140 determines that the connected card is a smart card and connects the smart card controller 130 and the connector 190. The PCMCIA controller 120 can recognize the smart card 310 via the smart card controller 130.

  When the selector 140 receives a low level select signal SEL from the PCMCIA controller 120, the selector 140 determines that the connected card is a PC card, and directly connects the PCMCIA controller 120 and the connector 190.

  FIG. 10 is a flowchart of the first control program of the PC card control device 100 executed by the CPU 10. First, the PC card control screen 400 shown in FIG. 11A is displayed on the display 14 by operating the predetermined operation unit 13 (step S1). When the new card setting button 401 displayed on the control screen is selected by the user by operating the operation unit 13 including a numeric keypad and a mouse (YES in step S2), the input screen shown in FIG. 410 is displayed (step S3).

  Here, the user selects an unused combination of data in the first register and the second register from the table shown in FIG. 6, and selects the selected data in the 4-bit data input box 411 in the first register. Then, after inputting necessary data into the input box 413 of 6-bit data (card information) for specifying the card type, the completion button 414 is clicked. select. Note that the 6-bit data specifying the type of the card is, in order from the highest bit, whether the expansion card is a 16-bit card, whether it is a 32-bit card, and whether the drive voltage is 5V. It represents whether the drive voltage is 3.3V, whether the drive voltage is X.XV, and whether the drive voltage is Y.YV, and is set to “1” when applicable. Is done.

  When the completion button 414 is selected by the operation of the operation unit 13 by the user (YES in step S4), the CPU 10 via the PCI bus 50, the PCI interface 110 in the PC card control device 100, and the flash ROM / I / F 150. A total of 14 bits of data of 4 bits + 4 bits + 6 bits input to the three input boxes 411, 412, 413 are written in the flash ROM 200 (step S5). If 14-bit data has already been written, the 14-bit data input this time is updated. If selection of the new card setting button 401 is not detected (NO in step S2), the processes in steps S3 to S5 are skipped. After performing other processing (step S6), the process returns to step S1.

  FIG. 12 is a flowchart of the second control program that the CPU always executes after the power is turned on. When a card detection signal is sent from the card identification unit 160 of the PC card control device 100 (YES in step S7), a card information request signal is output to the card information detection unit 184 of the card identification unit (step S8). The card type is recognized from the card information output from the card information detection unit 184 in response to the card information request signal (step S9), and other necessary processing is performed (step S10). If a card detection signal has not been sent (NO in step S7), the process waits in step S7 until a card detection signal is sent.

  The PC card control device 100 having the above configuration is prepared by connecting to the PCI bus 50, and by executing the PC card control program, other than the 12 PC cards defined in the card table 183 shown in FIG. The new type of expansion card can be recognized by the CPU 10.

(2) Modified example.
Hereinafter, a PC card identifying unit 160a that is a modification of the PC card identifying unit 160 included in the PC card control apparatus 100 according to Embodiment 1 will be described.
FIG. 13 is a diagram illustrating a configuration of the PC card identification unit 160a. In the figure, the same components as those of the PC card identification unit 160 are denoted by the same reference numerals, and redundant description is omitted here. The PC card identification unit 160 is entirely implemented by a hardware circuit, whereas the PC card identification unit 160a is characterized by detecting a PC card and an expansion card by software processing. More specifically, in the PC card identification unit 160a, the PC card identification unit 160 detects the connection of the card to the connector 190 based on the decrease in the potential of CD1 # and CD2 #, outputs the card detection signal to the CPU 10, and the timer. 17, the control unit 186 performs processing executed by the comparator 185 and the card information detection unit 184 by arithmetic processing. As a result, the PC card identification unit 160a does not include the card information detection unit 184 and the comparator 185, but includes a card information memory 189 instead.

  FIG. 14 is a flowchart of calculation processing executed by the control unit 186. Waiting for CD2 # and CD1 # output from the buffers 163 and 166 to become low level (NO in step S20), and when becoming low level (YES in step S201), the card is connected to the connector 190. After judging and transmitting the card detection signal to the CPU 10 (step S21), the following processing is executed. That is, a high level signal T1 is output to the P-channel MOSFET 179, and a high level signal is output to VS1 # for 1 ms. The latch signal L1 # is output to the latch terminal 180a of the first register 180 about 0.8 ms after the start of the output of the high level signal. At this time, the CD2 # and CD1 # output from the buffers 163, 166, 174, and 178 , VS2 #, VS1 # are held (step S22).

  Next, a high-level signal T2 is output to the P-channel MOSFET 175, and a high-level signal is output to VS2 # for 1 ms. The latch signal L2 # is output to the latch terminal 181a of the second register 181 approximately 0.8 ms after the start of the output of the High level signal, and is output from the buffers 163, 166, 174, and 178 at this time. Data of CD2 #, CD1 #, VS2 #, VS1 # is held (step S23).

  A total of 8 bits of data held in the first register 180 and the second register 181, 8 bits of data stored in the expansion card register 182, and 8 of 12 sheets stored in the card table 183. The bit data is compared (step S24). The comparison result with the data for 13 sheets in total is output to the PCMCIA controller 120 (step S25). Further, information (6-bit data) about the matched card is read from the card information memory 189 and specified (step S26), and a card information request signal is waited from the CPU 10 (NO in step S27). If a card information request signal is received (YES in step S27), the card information specified in step S26 is output to the CPU 10 (step S28), and the process is terminated.

  By preparing the PC card identification unit 160a having the above configuration, the circuit configuration can be simplified, and the apparatus can be downsized.

(3) Embodiment 2.
Hereinafter, the PC card control device 500 according to the second embodiment will be described. The PC card control apparatus 100 according to the first embodiment can add only one expansion card, whereas the PC card control apparatus 500 can add up to three expansion cards. FIG. 15 is a diagram showing a configuration of the PC card control device 500. In the figure, the same components as those of the PC card control apparatus 100 according to the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  More specifically, as apparent from comparison with the PC card control device 100 shown in FIG. 1, in the signal conversion unit 505 corresponding to the signal conversion unit 105, the first card controller is placed between the PCMCIA controller 510 and the selector 550. 520, a second card controller 530, and a third card controller 540. Here, the first to third cards refer to, for example, smart media (registered trademark of Toshiba Corporation), SD card, and memory stick (registered trademark of Sony Corporation). As will be described later, the PICMCIA controller 510 generates a 2-bit select signal SEL based on the comparison result of the PC card identification unit 560. The selector 550 is configured to connect the PCMCIA controller 510 and the connector 190 directly based on the 2-bit select signal, connect via the first card controller 520, connect via the second card controller, One is selected from the four cases of connection through the card controller.

The PC card identification unit 560 has a total of 8-bit data (identification information) in the first and second registers obtained from the card connected to the connector 190 in the same manner as the PC card control device 100 of the first embodiment. Compare the 8-bit data (identification information) of the three cards stored in the expansion card register 570 with the 8-bit data (identification information) of the 12 cards stored in the card memory 183, and compare The result is output to the PCMCIA controller 510, 6-bit data (card information) representing the type of the corresponding card is specified, and the 6-bit data (card information) is transmitted via the PCMCIA controller 510, the PCI interface 110, and the PCI bus 50. Output to the CPU 10.

  The CPU 10 executes processing having the same contents as the first and second control programs (see FIGS. 10 and 12) of the PC card control apparatus 100 described in the above-described first embodiment. In the first control program shown in FIG. 10, the part to be changed corresponding to the second embodiment is the expansion of three sheets in the input acceptance process (step S3) of the new first and second registers and the card information register. It is only a point that accepts the card data. On the other hand, there is no change in the second control program shown in FIG. That is, when a card detection signal is received from the PC card identification unit 560 (YES in step S7), the processing in steps S8 and S9 is executed to recognize the type of card connected to the connector 190.

  FIG. 16 is a diagram illustrating a configuration of the PC card identification unit 560. The same components as those of the PC card identification unit 160 included in the PC card control device 100 of the first embodiment are denoted by the same reference numerals, and redundant description is omitted. The comparator 590 includes a total of 8 bits of data (identification information) stored in the first register 180 and the second register 181, and 8 bits of data (identification information) of three cards stored in the expansion card register 570. And the 8-bit data (identification information) of 12 cards stored in the card table 183 are simultaneously compared in parallel, and the comparison result is output to the PCMCIA controller 510 and also to the card information detection unit 580.

  The card information detection unit 580 includes a selector 580a and a 6-bit register 580b. The selector 580a identifies the card types (bus bit width and corresponding drive voltage) for a total of 15 cards stored in the expansion card register 570 and 3 cards in the card table 183. 6-bit data (card information) is input in parallel. Then, for the card whose comparison result signal output from the comparator 590 is High level, 6-bit data indicating the type of the card is output to the register 580b. A signal obtained by inverting the signal TIM is input from the timer 171 to the enable terminal of the register 580b. In the register 580b, the timer 171 outputs the pulsed signal L2 #, and after the CD2 #, CD1 #, VS1 #, and VS2 # are stored in the second register 181, the signal TIM switches to the low level. The 6-bit data output from the selector 580a is stored as card information of the card connected to the connector 190.

  The 6-bit data latched in the register 580b is, in order from the upper bit, whether it is a 16-bit card, a 32-bit card, whether the drive voltage is 5V, Whether the voltage is 3.3V, whether the drive voltage is X.XV, and whether the drive voltage is Y.YV is represented by “1”, respectively.

  The register 580b outputs the latched 6-bit data to the 3-state buffer 191. In response to a low level card information request signal from the CPU 10, the 3-state buffer 191 uses the PCMCIA controller 510, the PCI interface 110, the 6-bit data as data (card information) indicating the type of card connected to the connector 190, And it outputs to CPU10 via the PCI bus 50. FIG. The CPU 10 exchanges data with the card connected to the connector 190 based on the content of the received 6-bit data (card information).

  FIG. 17 is a diagram showing a partial configuration of the PCMCIA controller 510. As shown in FIG. As shown in the figure, among the comparison results input from the PC card identification unit 560, each of the 4 bits stored in the registers 180 and 181 has a total of 8 bits of data (identification information) and 3 stored in the expansion card register 570. The comparison result with the 8-bit data (identification information) for the number of sheets is output as a 2-bit select signal SEL using the two OR gates 511 and 512. Specifically, the OR gate 512 obtains the logical sum of the 1-bit data of the first comparison result and the 1-bit data of the third comparison result, and outputs the OR gate 512 to the 2-bit select signal. Output as lower bit data. The OR gate 511 obtains the logical sum of the 1-bit data of the second comparison result and the 1-bit data of the third comparison result, and uses the output of the OR gate 511 as the upper bit data of the 2-bit select signal SEL. Output. That is, when the 8-bit data stored in the first register 180 and the second register 181 matches the 8-bit data stored in the expansion card register 182, a high level signal is output as the select signal SEL. The On the other hand, if they do not match, a low level signal is output as the select signal SEL.

  Here, FIG. 15 will be referred to again. Upon receiving the “00” select signal SEL from the PCMCIA controller 510, the selector 550 determines that the connected card is a PC card compliant with PCMCIA, and directly connects the PCMCIA controller 510 and the connector 190. When the select signal SEL of “01” is received, it is determined that the card is the first card, and the first card controller 520 and the connector 190 are connected. The PCMCIA controller 510 can recognize the first card via the first card controller 520. Similarly, when a select signal SEL of “10” or “11” is received, it is determined that the card is the second or third card, and the second card controller 520 or the third card controller 530 and the connector 190 are connected. . The PCMCIA controller 510 can recognize the second card or the third card via the second card controller 530 or the third card controller 540.

  As described above, according to the PC card control apparatuses 100 and 500, a new type of card identification method is used without using a special card identification algorithm and using a conventionally known card identification method based on PCMCIA. The expansion card can be recognized. Furthermore, when the type of the expansion card that has already been recognized is changed or corrected (for example, when the drive voltage is improved from 5 V to 3.3 V), the flash ROM 200 can be flexibly handled simply by rewriting the contents. be able to.

  In the PC card control device 100 of the first embodiment and the PC card control device 500 of the second embodiment, the total 8-bit data values of the first register and the second register set in the expansion card register are shown in FIG. In the PCMCIA as shown in FIG. 6, an undefined combination is used. For example, No. 6 in the card table shown in FIG. 5 and no. For the spare combination in which the card type is undefined as in 9, this may be used. Furthermore, it may be possible to redefine combinations already defined other than the above. In these cases, cards corresponding to both the card table and the expansion card register are detected. For example, the expansion card is executed so that the PCMCIA controller 120 included in the PC card control device 100 of the first embodiment executes. The select signal SEL may be generated based only on the comparison result for the register.

1 is a diagram illustrating a configuration of a computer system including a PC card control device according to Embodiment 1. FIG. (A) shows a state where a PC card is connected to a connector compliant with PCMCIA, and (b) shows a state where a smart card is connected via an adapter. (A) shows the example of wiring for the card identification of a PC card, (b) is a figure which shows the state of the signal of each part at the time of card detection. (A) shows an example of wiring for card identification of an expansion card, and (b) is a diagram showing a signal state of each part at the time of card detection. It is a figure which shows the card table based on PCMCIA. It is a figure which shows the card table of the unused combination in PCMCIA. It is a figure which shows the structure of a PC card identification part. It is a time chart which shows each signal output from CD1 #, CD2 #, VS1 #, VS2 # and a timer. It is a figure which shows the structure of a part of PCMCIA controller. It is a flowchart which shows the processing content of the 1st control program which CPU performs. (A) And (b) is a figure which shows the screen displayed on a display at the time of PC card control program execution. It is a flowchart which shows the processing content of the 2nd control program which CPU performs. It is a figure which shows the structure of the modification of a PC card identification part. It is a flowchart which shows the processing content which the control part which comprises the modification of the said PC card identification part performs. It is a figure which shows the structure of a computer system provided with the PC card control apparatus concerning Embodiment 2. FIG. It is a figure which shows the structure of a PC card identification part. It is a figure which shows the structure of a part of PCMCIA controller.

Explanation of symbols

  1 computer system, 10 CPU, 11 ROM, 12 RAM, 13 operation unit, 14 display, 15 HD, 100,500 PC card control device, 130 smart card controller, 150 flash ROM / I / F, 160, 160a, 560 PC Card identification unit, 180 first register, 181 second register, 182,570 expansion card register, 183 card table, 184,580 card information detection unit, 190 PC card connector, 200 flash ROM, 250 PC card, 300 smart card Adapter, 310 smart card, 520 first card controller, 530 second card controller, 540 third card controller Controller.

Claims (1)

An identification information acquisition unit for acquiring identification information from a connected card in accordance with a standard,
A first recording unit in which identification information corresponding to each card information is recorded together with card information about one or more types of PC cards conforming to the above-mentioned standard;
A second recording unit in which identification information corresponding to the card information is recorded together with card information about one or more types of expansion cards that do not comply with the standard,
The identification information acquired by the identification information acquisition unit for the connected card and the identification information recorded in at least the second recording unit among the identification information recorded in the first recording unit and the second recording unit A PC card control device comprising: a PC card identifying unit that identifies a type of a card connected to the card and outputs card information about the connected card together with the identification result.

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