JP2007288154A - Multilayer electronic component and its manufacturing process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable multilayer electronic component in which flat side crack occurring from the flat surface to the side face is prevented effectively even when a dielectric layer is thinned and multilayered. <P>SOLUTION: The multilayer electronic component comprises an element body consisting of an inner layer where an inner electrode layer and an interlayer dielectric layer are laminated alternately, and upper and lower outer layers arranged on the upper and lower end faces of the inner layer in the laminating direction and composed of an outer dielectric layer. The inner electrode layers are formed on a pair of opposing end faces of the element body parallel with the laminating direction to be exposed alternately, and a pair of terminal electrodes are formed on the pair of end faces where the inner electrode layer is exposed. On the cross-section appearing when the element body is cut by a plane parallel with the end face where the pair of terminal electrodes are formed, the number of air gaps (electrode air gap portions) existing in the vicinity of the electrode end of the inner electrode layer arranged in the vicinity of the outer layer falls within a specific range. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multilayer electronic component such as a multilayer ceramic capacitor and a manufacturing method thereof. More specifically, even when a dielectric layer is thinned or multilayered, a flat crack generated from a plane to a side surface is effective. The present invention relates to a multilayer electronic component that is prevented and a method of manufacturing the same.

  Multilayer ceramic capacitors as multilayer electronic components are widely used as small-sized, large-capacity, high-reliability electronic components, and the number used in one electronic device is large.

  Such a multilayer ceramic capacitor is usually manufactured by the following method. That is, first, a ceramic paint containing a dielectric powder, a binder, and an organic solvent is prepared. Next, this ceramic paint is applied onto a PET film by using a doctor blade method or the like, heated and dried, and then the PET film is peeled off to obtain a ceramic green sheet. Next, the internal electrodes are printed on this ceramic green sheet, dried, and the laminate is cut into chips to form green chips. After firing the green chips, the terminal electrodes are formed. The

  When manufacturing a multilayer ceramic capacitor, the interlayer thickness of the sheet on which the internal electrode is formed is set in a range of about 1 μm to 100 μm based on a desired capacitance required for the capacitor. Further, in the multilayer ceramic capacitor, an outer layer portion where no internal electrode is formed is formed on the outer portion in the stacking direction of the capacitor chip. The thickness of the dielectric layer corresponding to the portion where the internal electrode is not formed is about several tens μm to several hundreds μm, and is usually formed to protect the inside of the capacitor element.

  On the other hand, Pd or a Pd alloy is generally used as a conductive material for the internal electrode. However, since Pd is expensive, a relatively inexpensive base metal such as Ni or a Ni alloy has been used. When a base metal is used as the conductive material for the internal electrode, there is a problem that the internal electrode oxidizes when fired in the atmosphere. Therefore, simultaneous firing of the dielectric layer and the internal electrode is required in a reducing atmosphere. There is. However, when firing in a reducing atmosphere, the dielectric layer is reduced and the specific resistance is lowered. For this reason, non-reducing dielectric materials have been developed.

  However, even when a non-reducing dielectric material is used, due to the influence of Ni constituting the internal electrode, a portion (inner layer portion) where a large number of sheets on which the internal electrode is formed is laminated and the internal electrode is not formed. The shrinkage behavior during firing differs between the portion (outer layer portion) and, as a result, there is a problem that cracks occur inside the capacitor element body.

  On the other hand, for example, in Patent Documents 1 to 4, various proposals have been made by paying attention to the shrinkage behavior of the outer layer portion and the inner layer portion during firing when manufacturing a multilayer ceramic electronic component. For example, Patent Documents 1 and 2 propose a method in which the shrinkage start temperature due to firing of the outer layer portion is set lower than the shrinkage start temperature of the inner layer portion.

  Patent Document 3 proposes a method of using ceramic particles having a smaller particle diameter than ceramic particles that constitute the inner layer portion as ceramic particles that constitute the outer layer portion. Patent Document 4 proposes a method in which the density of the ceramic green sheet that constitutes the outer layer portion is set lower than the density of the ceramic green sheet that constitutes the inner layer portion.

  However, for example, when the dielectric layer is set to 3 μm or less and further thinning and multi-layering are promoted, the relationship between the outer layer portion and the inner layer portion is set to a predetermined relationship as described in these documents. There was a problem like this. In other words, when thinning and multilayering are advanced, the distortion of the structure based on the difference in shrinkage behavior during firing between the inner layer portion and the outer layer portion increases, and FIG. 5 (A) and FIG. 5 (B). There was a problem that cracks (flat cracks) occurred from the flat surface (upper surface or bottom surface) to the side surface as shown. 5A and 5B are diagrams showing a cut surface in the length direction of the multilayer ceramic capacitor (that is, a surface parallel to the end surface on which the terminal electrodes are formed).

  Moreover, in patent document 5, among the internal electrode layers which comprise an inner layer part, the method of using the thing with a comparatively big particle diameter as Ni powder which comprises the internal electrode layer located in the outer layer part side is used. Proposed. According to this document, the sintering start temperature of the internal electrode layer located on the outer layer side can be made higher than the sintering start temperature of the internal electrode layer arranged in the other part, thereby By reducing the difference in shrinkage behavior between the outer layer portion and the outer layer portion, the occurrence of cracks in the capacitor element body is prevented. However, in Patent Document 5, Ni powder having a relatively large particle diameter is used for the internal electrode layer located on the outer layer side, so that there is a limit to thinning of the internal electrode layer located on the outer layer side. Therefore, there is a limit to the size and thickness of the obtained multilayer ceramic capacitor.

JP-A-9-97733 JP 2004-221268 A Japanese Patent Laid-Open No. 11-354370 Japanese Patent Laid-Open No. 2002-141243 JP 2005-209721 A

  The present invention has been made in view of such a situation, and even when the dielectric layer is thin and multilayered, a flat crack generated from the flat surface to the side surface is effectively prevented, and a highly reliable multilayer electronic component And it aims at providing the manufacturing method.

  As a result of intensive studies to achieve the above object, the present inventors have determined that a void portion (electrode void portion) existing in the vicinity of the electrode end portion of the internal electrode layer disposed in the vicinity of the outer layer portion is within a predetermined range. As a result of the control, the inventors have found that the above object can be achieved, and have completed the present invention.

That is, the multilayer electronic component according to the present invention is
An inner layer portion in which internal electrode layers and interlayer dielectric layers are alternately stacked;
A multilayer electronic component having an element body composed of an upper outer layer portion and a lower outer layer portion, which are arranged on an upper end surface and a lower end surface in the stacking direction of the inner layer portion and are composed of an outer dielectric layer,
The internal electrode layers are alternately formed on a pair of opposing end faces parallel to the stacking direction of the element body, and a pair of terminal electrodes is formed on the pair of end faces where the internal electrode layers are exposed. Formed,
The number of laminated interlayer dielectric layers is 100 or more,
In the cut surface when cutting the element body in a plane parallel to the end surface where the pair of terminal electrodes are formed,
The average length of the internal electrode layers in the length direction of the plurality of internal electrode layers in the cut surface is 0.15 mm or more,
One end in the length direction of the plurality of internal electrode layers in the cut surface is a first end, the other end is a second end,
Of the internal electrode layers, each internal electrode layer from the upper outer layer side to the fifteenth layer is an upper electrode layer, and each internal electrode layer from the lower outer layer part side to the fifteenth layer is a lower electrode layer,
In the upper electrode layer, a portion having a length of 40 μm from the first end portion and the second end portion toward the center side of the internal electrode layer is divided into an upper electrode layer first corner portion, an upper electrode layer second corner portion, and
In the lower electrode layer, a portion having a length of 40 μm from the first end portion and the second end portion toward the center side of the internal electrode layer is divided into a lower electrode layer first corner portion and a lower electrode layer second corner, respectively. Part
Regarding the electrode gap that is present in the formation portion of the internal electrode layer and is substantially void,
The number N1 of electrode gaps in the first corner of the upper electrode layer, the number N2 of electrode gaps in the second corner of the upper electrode layer, the number of electrode gaps in the first corner of the lower electrode layer An average value [(N1 + N2 + N3 + N4) / 4] of N3 and the number N4 of electrode gaps in the second corner portion of the lower electrode layer is 1 or more and 20 or less.

In the multilayer electronic component of the present invention, preferably,
From the upper outer layer side and the lower outer layer side, an average crystal grain size Rfo [μm] of dielectric particles constituting each of the interlayer dielectric layers of a total of 30 layers up to the 15th layer,
The average crystal grain size Rfc [μm] of the dielectric particles constituting the interlayer dielectric layer located in the other part is 0.55 ≦ Rfo / Rfc ≦ 0.95.

In the multilayer electronic component of the present invention, preferably, the average thickness of the interlayer dielectric layer is 3 μm or less.
In the present invention, the average thickness of the interlayer dielectric layers is defined as the upper outer layer portion side and the lower outer layer portion when n is the number of all interlayer dielectric layers constituting the multilayer electronic component. From the side, the thickness can be obtained by averaging the thicknesses of the interlayer dielectric layers excluding the 0.05 × n interlayer dielectric layers.

  In the multilayer electronic component of the present invention, preferably, the thickness of the internal electrode layer is 2 μm or less.

  In the multilayer electronic component of the present invention, preferably, the conductive material included in the internal electrode layer is Ni or a Ni alloy.

A method for manufacturing a multilayer electronic component according to the present invention includes:
An inner layer portion in which internal electrode layers and interlayer dielectric layers are alternately stacked;
A method of manufacturing a multilayer electronic component having an element body comprising an upper outer layer portion and a lower outer layer portion which are disposed on the upper end surface and the lower end surface in the stacking direction of the inner layer portion and are composed of outer dielectric layers. And
A step of forming an interlayer green sheet containing the dielectric material after becoming the interlayer dielectric layer after firing;
The outer dielectric layer after firing, forming an outer green sheet containing a dielectric material; and
Forming an electrode paste film to be an internal electrode layer after firing on the surface of the interlayer green sheet;
Laminating the interlayer green sheet having the electrode paste film so that the total number of laminated layers of the interlayer green sheets is 100 or more, and obtaining a laminate for an inner layer part;
Laminating the outer green sheet on the upper end surface and the lower end surface in the stacking direction of the inner layer laminate, to obtain a green chip;
Firing the green chip,
With respect to the interlayer green sheet that becomes the interlayer dielectric layer after firing, it is located from the upper end surface and the lower end surface in the stacking direction of the inner layer laminate to the mth layer (where m is 1 or more and 30 or less). When the interlayer green sheet to be used is the outer interlayer green sheet, and the interlayer green sheet to be positioned in the other part is the inner interlayer green sheet,
A dielectric material having the same sintering start temperature is used as the dielectric material contained in the outer green sheet and the dielectric material contained in the outer interlayer green sheet, and the outer green sheet and the outer interlayer are used. The relationship between the sintering start temperature Tgo [° C.] of the dielectric material contained in the green sheet and the sintering start temperature Tgc [° C.] of the dielectric material contained in the inner interlayer green sheet is Tgo <Tgc. It is characterized by that.

  Note that the dielectric raw material contained in the outer green sheet and the dielectric raw material contained in the outer interlayer green sheet need only have substantially the same sintering start temperature. The temperature may be slightly different.

  In the production method of the present invention, preferably, the relationship between Tgo and Tgc is set to −100 ° C. ≦ Tgo−Tgc ≦ −5 ° C.

  In the production method of the present invention, preferably, a dielectric material having the same average particle diameter is used as the dielectric material contained in the outer green sheet and the dielectric material contained in the outer interlayer green sheet. The average particle size of the dielectric material contained in the outer green sheet and the outer interlayer green sheet is Rgo [μm], and the average particle size of the dielectric material contained in the inner interlayer green sheet is Rgc [μm]. In this case, the relationship between Rgo and Rgc is Rgo <Rgc. Similarly to the above, the average particle diameter of the dielectric raw material contained in the outer green sheet and the dielectric raw material contained in the outer interlayer green sheet should be substantially the same. .

  In the production method of the present invention, preferably, the relationship between Rgo and Rgc is 0.50 ≦ Rgo / Rgc ≦ 0.95.

  The multilayer electronic component according to the present invention is not particularly limited, and examples thereof include multilayer ceramic capacitors, piezoelectric elements, chip inductors, chip varistors, chip thermistors, chip resistors, and other surface mount chip electronic components (SMD). The

  In the multilayer electronic component of the present invention, the number of void portions (electrode void portions) existing in the vicinity of the electrode end portion of the internal electrode layer disposed in the vicinity of the outer layer portion is set within a predetermined range. Therefore, even when the average thickness of the interlayer dielectric layer is set to 3 μm or less and the number of stacked layers is set to 100 or more, it is possible to effectively prevent a flat crack generated from the plane to the side surface and to provide a highly reliable stack. Mold electronic components can be provided.

  Furthermore, in the manufacturing method of the present invention, the dielectric material contained in the outer green sheet that becomes the outer dielectric layer after firing and the interlayer green sheet that becomes the interlayer dielectric layer after firing are positioned near the outer layer portion. As the dielectric material contained in the outer interlayer green sheet, the dielectric material having the same sintering start temperature is used, and the sintering start temperature of the dielectric material contained in the outer green sheet and the outer interlayer green sheet The relationship between Tgo [° C.] and the sintering start temperature Tgc [° C.] of the dielectric material contained in the inner interlayer green sheet is Tgo <Tgc. Therefore, the difference in thermal expansion at the interface between the inner layer portion and the outer layer portion can be reduced during firing. As a result, it is possible to effectively prevent a flat crack generated from the flat surface to the side surface, and to provide a highly reliable multilayer electronic component.

Hereinafter, the present invention will be described based on embodiments shown in the drawings.
FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention.
2 is a schematic cross-sectional view of the multilayer ceramic capacitor taken along line II-II shown in FIG.
FIG. 3 is a cross-sectional view of a main part of a multilayer ceramic capacitor according to an embodiment of the present invention.
4A is a cross-sectional photograph of the main part of the multilayer ceramic capacitor according to the example of the present invention, FIG. 4B is a cross-sectional photograph of the main part of the multilayer ceramic capacitor according to the comparative example,
FIG. 5A and FIG. 5B are diagrams for explaining a flat crack in the multilayer ceramic capacitor.

Multilayer Ceramic Capacitor As shown in FIG. 1, a multilayer ceramic capacitor 1 according to an embodiment of the present invention includes a capacitor element body 10 having a configuration in which interlayer dielectric layers 2 and internal electrode layers 3 are alternately stacked. A pair of terminal electrodes 4, 4 are formed on both end portions of the capacitor element body 10, respectively, and are electrically connected to the internal electrode layers 3 arranged alternately in the element body 10. The internal electrode layers 3 are laminated such that the side end faces are alternately exposed on the surfaces of the two opposite ends of the capacitor element body 10. The pair of terminal electrodes 4, 4 are formed at both ends of the capacitor element body 10 and are connected to the exposed end surfaces of the alternately arranged internal electrode layers 3 to constitute a capacitor circuit.

  In the capacitor element body 10, outer dielectric layers 20 are respectively disposed at the upper end portion and the lower end portion in the stacking direction of the internal electrode layer 3 and the interlayer dielectric layer 2 to protect the inside of the element body 10. ing. That is, the capacitor element body 10 is located on the inner layer portion 100 in which the plurality of internal electrode layers 3 and the interlayer dielectric layer 2 are laminated, and on the upper and lower surfaces of the inner layer portion 100 and is formed from the outer dielectric layer 20. It consists of an outer layer part 200 and a lower outer layer part 300.

  The shape of the capacitor element body 10 is not particularly limited, but is usually a rectangular parallelepiped shape. Also, there is no particular limitation on the dimensions, and it may be an appropriate dimension depending on the application. Usually, length L (0.6 to 5.6 mm, preferably 0.6 to 3.2 mm) × width It is about W (0.3-5.0 mm, preferably 0.3-1.6 mm) × thickness T (0.1-1.9 mm, preferably 0.3-1.6 mm).

Dielectric layers 2 and 20
Interlayer dielectric layer 2 and outer dielectric layer 20 are made of a dielectric ceramic composition. Composition of the dielectric ceramic composition forming the dielectric layers 2 and 20 is not particularly limited, for _{example, {(Ba (1-x} -y) Ca x Sr y) O} A (Ti (1-z) And Zr _z ) having a main component including a dielectric oxide represented by _{B 2} O ₂ . Note that A, B, x, y, and z are all in an arbitrary range. The subcomponents included in the dielectric ceramic composition together with the main component include Sr, Y, Gd, Tb, Dy, V, Mo, Ho, Yb, Zn, Cd, Ti, Sn, W, Ba, Ca, Mn. , Mg, Cr, Si, and a subcomponent containing one or more kinds selected from oxides of P are exemplified.

  By adding subcomponents, low-temperature firing is possible without deteriorating the dielectric properties of the main component, reliability defects when the interlayer dielectric layer 2 is thinned can be reduced, and a longer life is achieved. Can be planned. However, in the present invention, the composition of the ceramic particles constituting each of the dielectric layers 2 and 20 is not limited to the above.

Various conditions such as the number of layers and thickness of the interlayer dielectric layer 2 may be appropriately determined according to the purpose and application. In the present embodiment, the average thickness of the interlayer dielectric layer 2 is 3 μm or less, preferably 0. The thickness is 5 to 2.8 μm, more preferably 1.0 to 2.5 μm. The number of interlayer dielectric layers 2 sandwiched between the internal electrode layers 3 is 100 or more, preferably 150 or more. The thickness of the outer dielectric layer 20 is, for example, about 30 μm to several hundred μm.
In the present embodiment, the average thickness of the interlayer dielectric layers is the upper outer layer portion side and the lower outer layer when n is the number of all interlayer dielectric layers constituting the multilayer electronic component. From the part side, the thickness can be obtained by averaging the thicknesses of the interlayer dielectric layers excluding the 0.05 × n interlayer dielectric layers.

  Further, in the present embodiment, the average crystal grain size of the dielectric particles constituting each of the interlayer dielectric layers 2 of 30 layers in total from the upper outer layer portion 200 side and the lower outer layer portion 300 side to the fifteenth layer is set. When the average crystal grain size of the dielectric particles constituting the interlayer dielectric layer 2 located in the other part is Rfc [μm], the ratio of these Rfo and Rfc is preferably 0.55 ≦ Rfo / Rfc ≦ 0.95, more preferably 0.60 ≦ Rfo / Rfc ≦ 0.90. By setting the ratio of Rfo and Rfc to such a relationship, the microstructure of the internal electrode layer 3 to be described later can be set to a predetermined configuration.

Internal electrode layer 3
The conductive material contained in the internal electrode layer 3 is not particularly limited, but a base metal can be used when a material having reduction resistance is used as the constituent material of the dielectric layers 2 and 20. As the base metal used as the conductive material, Ni, Cu, Ni alloy or Cu alloy is preferable. When the main component of the internal electrode layer 3 is a base metal such as Ni, a method of firing at a low oxygen partial pressure (reducing atmosphere) is employed so that the dielectric is not reduced.

Next, the fine structure of the internal electrode layer 3 will be described with reference to FIGS. FIG. 2 is a schematic cross-sectional view (cross-sectional view in the length direction) taken along the line II-II shown in FIG. 1, and FIG. 3 is a main-part cross-sectional view showing the fine structure of the internal electrode layer 3. In FIG. 2, the internal structure of the element body 10 is simplified as compared with FIG. In the cross section shown in FIG. 2, the internal electrode layer 3 is protected by the side margins 22 arranged on both side surfaces without being exposed at the side end surfaces. The side margins 22 are made of a dielectric ceramic composition, like the interlayer dielectric layer 2 and the outer dielectric layer 20. In the cross section shown in FIG. 2, the length in the width direction (W direction) of the internal electrode layer 3 is an average value of the plurality of internal electrode layers 3 contained in the inner layer portion 100, and is 0.15 to 4.0 mm. Yes, preferably 0.2 to 1.4 mm.

  In the present embodiment, among the plurality of internal electrode layers 3, the internal electrode layers at specific locations, that is, the upper electrode layer first and second corner portions and the lower electrode layer first and second corner portions shown in FIG. The microstructure is configured as described below.

  The upper electrode layer first and second corner portions and the lower electrode layer first and second corner portions are the upper electrode layer and the lower electrode layer located in the upper electrode layer forming portion and the lower electrode layer forming portion shown in FIG. Each side electrode layer has a length of 40 μm from the first end as one electrode end in the width direction (W direction) and the second end as the other electrode end toward the center of each electrode layer. This is the part. In the present embodiment, the upper electrode layer and the lower electrode layer mean the internal electrode layers from the upper outer layer portion 200 side and the lower outer layer portion 300 side to the fifteenth layer. That is, the upper electrode layer and the lower electrode layer are each composed of 15 internal electrode layers.

  Next, the fine structure of the internal electrode layer in the first and second corner portions of the upper electrode layer and the first and second corner portions of the lower electrode layer will be specifically described with reference to FIG. FIG. 3 is an enlarged cross-sectional view of a principal part of the first corner portion of the lower electrode layer shown in FIG. As shown in FIG. 3, the lower electrode layer first corner portion is an electrode discontinuity portion of the internal electrode layer 3 in a portion having a length of 40 μm from the first end portion which is one electrode end portion, There is an electrode gap 30 that is substantially a gap. In the present embodiment, the upper electrode layer first corner portion, the second corner portion, and the lower electrode layer second corner portion other than the lower electrode layer first corner portion and the lower electrode layer first corner portion are present. The number of electrode gaps 30 is in a specific range.

  That is, N1 is the number of electrode gaps 30 in the first corner of the upper electrode layer, N2 is the number of electrode gaps 30 in the second corner of the upper electrode layer, and electrode gaps in the first corner of the lower electrode layer The average value [(N1 + N2 + N3 + N4) / 4] is 1 or more and 20 or less, where N3 is the number of existence of 30 and N4 is the number of electrode gaps 30 in the second electrode corner of the lower electrode layer. Preferably they are 2 or more and 19 or less, More preferably, they are 3 or more and 18 or less.

  By making the number of electrode gaps 30 present at each corner within the above range, even when the interlayer dielectric layer 2 is thin or multilayered, it is possible to effectively prevent flat cracks that occur from the plane to the side. Can do. If the number of electrode gaps 30 present at each corner is too large, the effect of preventing flat side cracks tends to be insufficient. On the other hand, if the number of existing voids 30 is too small, the interlayer dielectric layer 2 and the internal electrode layer 3 are present. There is a risk of delamination at the interface.

  In the present embodiment, the electrode gap portion 30 is a portion that is substantially a gap among the electrode breakage portions of the internal electrode layer 3, such as the electrode breakage portion indicated by reference numeral “32” in FIG. 3. The portion where the dielectric is present in the portion where the internal electrode layer 3 is formed is not included. In the present embodiment, the electrode gap 30 has a size of 0.5 μm × 0.5 μm or more.

  The first end portion which is one electrode end portion in the width direction (W direction) and the second end portion which is the other electrode end portion are electrode end portion positions of a plurality of internal electrode layers contained in the inner layer portion 100. For example, when the end positions of the internal electrode layers are different from each other in the direction along the width direction (W direction), the positions are averaged. Can be sought.

  In the present embodiment, only the first corner portion of the lower electrode layer is illustrated, but the upper electrode layer first and second corner portions and the lower electrode layer second corner other than the lower electrode layer first corner portion are illustrated. The parts have substantially the same configuration. The average value of the electrode gap 30 is preferably in the above range in a cross section at a depth of 15 to 85% in the length direction (L direction) when the length of the element body is 100%. .

  In the present embodiment, the average thickness of the internal electrode layer 3 is preferably 2 μm or less, and particularly preferably 1.5 μm or less.

Terminal electrode 4
The conductive material contained in the terminal electrode 4 is not particularly limited, but usually Cu, Cu alloy, Ni, Ni alloy or the like is used. Of course, Ag, an Ag—Pd alloy, or the like can also be used. In the present embodiment, inexpensive Ni, Cu, and alloys thereof can be used.
Although the thickness of the terminal electrode 4 should just be determined suitably according to a use etc., it is preferable normally that it is about 10-50 micrometers.

Next, a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention will be described.
(1) First, in order to manufacture a ceramic green sheet (interlayer green sheet, outer green sheet) that will constitute the interlayer dielectric layer 2 and the outer dielectric layer 20 shown in FIG. Prepare the paste.
The green sheet paste is prepared by converting a dielectric material into a paint. The green sheet paste may be an organic paint obtained by kneading a dielectric material and an organic vehicle, or may be a water-based paint.

  As the dielectric material, various compounds to be complex oxides and oxides, for example, carbonates, nitrates, hydroxides, organometallic compounds, and the like are appropriately selected and used by mixing. The dielectric material is usually used as a powder having an average particle size of 0.4 μm or less, preferably about 0.1 to 0.3 μm.

  An organic vehicle is obtained by dissolving a binder in an organic solvent. The binder used for the organic vehicle is not particularly limited, and may be appropriately selected from usual various binders such as ethyl cellulose and polyvinyl butyral. Moreover, the organic solvent to be used is not particularly limited, and may be appropriately selected from various organic solvents such as terpineol, butyl carbitol, acetone, toluene, and the like, depending on a method to be used such as a printing method or a sheet method.

  When the green sheet paste is used as a water-based paint, a water-based vehicle in which a water-soluble binder or a dispersant is dissolved in water and a dielectric material may be kneaded. The water-soluble binder used for the water-based vehicle is not particularly limited, and for example, polyvinyl alcohol, cellulose, water-soluble acrylic resin, etc. may be used.

  In the present embodiment, the following three types of paste are prepared as the green sheet paste. That is, an outer green sheet paste for manufacturing an outer green sheet that will form the outer dielectric layer 20 after firing, and an interlayer green sheet 2 for manufacturing the interlayer dielectric layer 2. A total of three types of pastes for green sheets of different types are prepared.

  That is, as an interlayer green sheet paste, from the upper end surface and the lower end surface in the stacking direction of the inner layer portion laminate that becomes the inner layer portion 100 after firing, m layers (however, m is 1 or more, 30 or less, The lower limit of m is preferably 2 or more, more preferably 5 or more, and the upper limit of m is preferably 25 or less, more preferably 20 or less). An outer interlayer green sheet paste for forming an “interlayer green sheet”) and an interlayer green sheet (hereinafter referred to as an “inner interlayer green sheet”) to be located in other portions are formed. Each inner interlayer green sheet paste is prepared.

  In the present embodiment, among the above three types of green sheet pastes, the same sintering start is performed with the dielectric material contained in the outer green sheet paste and the dielectric material contained in the outer interlayer green sheet paste. The dielectric material having a temperature is used, the sintering start temperature of the dielectric material to be contained in these pastes is Tgo [° C.], and the sintering start temperature of the dielectric material to be included in the inner interlayer green sheet paste is When Tgc [° C.] is used, a dielectric material in which Tgo and Tgc have a relationship of Tgo <Tgc is used. That is, a dielectric material having a sintering start temperature lower than that of the dielectric material contained in the inner interlayer green sheet paste is used as the dielectric material contained in the outer green sheet paste and the outer interlayer green sheet paste.

  By adopting such a configuration, the stress applied to the interface between the inner layer portion 100 and the outer layer portions 200 and 300 during firing is alleviated, and the number of the electrode gap portions 30 existing in each corner portion described above is specified. Range. As a result, even when the interlayer dielectric layer 2 is thin or multilayered, it is possible to effectively prevent a flat crack generated from the flat surface to the side surface, and to improve the reliability of the obtained multilayer ceramic capacitor. Can be planned.

  The relationship between Tgo and Tgc is preferably −100 ° C. ≦ Tgo-Tgc ≦ −5 ° C., more preferably −90 ° C. ≦ Tgo-Tgc ≦ −10 ° C. If the difference between Tgo and Tgc (Tgo−Tgc) is too large, delamination may occur at the interface between the interlayer dielectric layer 2 and the internal electrode layer 3. In this embodiment, the sintering start temperature of the dielectric material means a temperature at which shrinkage starts when the temperature rises in the TMA analysis.

  The method for setting the sintering start temperature of the dielectric material contained in each green sheet paste to the above relationship is not particularly limited, and various methods can be adopted. Examples of such a method include a method of using dielectric raw materials having different average particle diameters for the outer green sheet paste and the outer interlayer green sheet paste and the inner interlayer green sheet paste. Specifically, the average particle size of the dielectric material contained in the outer green sheet paste and the outer interlayer green sheet is Rgo [μm], and the average particle size of the dielectric material contained in the inner interlayer green sheet is Rgc. In the case of [μm], Rgo and Rgc are preferably Rgo <Rgc, more preferably 0.50 ≦ Rgo / Rgc ≦ 0.95, and still more preferably 0.6 ≦ Rgo / Rgc ≦ 0.9. It is related. By setting Rgo and Rgc to the above relationship, the sintering start temperature of the dielectric material contained in each paste can be set to the relationship described above.

  (2) Next, an electrode layer paste for forming the internal electrode layer 3 shown in FIG. 1 is prepared. The electrode layer paste is prepared by kneading the above-mentioned organic vehicle with various conductive metals and alloys as described above, or various oxides, organometallic compounds, resinates and the like that become the above-mentioned conductive materials after firing. To do. The electrode layer paste may contain a ceramic powder as a co-material as required. The common material has an effect of suppressing the sintering of the conductive powder in the firing process.

  (3) Using each of the above prepared interlayer interlayer green sheet paste, inner interlayer green sheet paste, and electrode layer paste, each interlayer green sheet that becomes the interlayer dielectric layer 2 after firing; An electrode paste film that becomes the internal electrode layer 3 after firing is alternately laminated, and a laminate for an inner layer portion that becomes the inner layer portion 100 after firing is manufactured.

Specifically, first, an outer interlayer green sheet and an inner interlayer green sheet are formed on a carrier sheet as a support by a doctor blade method or the like. Each interlayer green sheet is dried after being formed on the carrier sheet. The drying temperature of each interlayer green sheet is preferably 50 to 100 ° C., and the drying time is preferably 1 to 20 minutes. The thickness of each interlayer green sheet after drying shrinks to a thickness of 5 to 25% as compared with that before drying.
In the present embodiment, the outer interlayer green sheet and the inner interlayer green sheet may have the same thickness or different thicknesses. When these thicknesses are different, either the outer interlayer green sheet or the inner interlayer green sheet may be a thick sheet.

  Next, an electrode paste film is formed in a predetermined pattern on the surfaces of the outer interlayer green sheet and the inner interlayer green sheet formed as described above, and an interlayer green sheet having the electrode paste film is obtained. And the interlayer green sheet which has the obtained electrode paste film | membrane is laminated | stacked alternately, and the laminated body for inner layer parts is obtained. The method for forming the electrode paste film is not particularly limited, and examples thereof include a printing method and a transfer method. Further, if necessary, a blank pattern film may be formed in a portion where the electrode paste film is not formed. The blank pattern film may be formed by the printing method or the transfer method using the above-described interlayer green sheet paste.

  (4) Next, an outer green sheet that becomes the outer dielectric layer 20 after firing is laminated in a single layer or a plurality of layers on the upper end portion and the lower end portion in the lamination direction of the laminate for the inner layer portion obtained above. The outer green sheet is produced by peeling the carrier sheet after forming the outer green sheet on the carrier sheet as a support using the outer green sheet paste prepared above. The outer green sheet is preferably formed with a thickness of about 5 to 100 μm, more preferably about 5 to 30 μm.

  The laminated body thus obtained is cut into a predetermined size to obtain a green chip, and then the binder removal treatment and firing are performed, and the interlayer dielectric layer 2 and the outer dielectric layer 20 are reoxidized. Therefore, the capacitor element body 10 shown in FIG. 1 is obtained by heat treatment.

The binder removal treatment may be appropriately determined according to the type of the conductive material in the electrode layer paste for forming the internal electrode layer 3, but when a base metal such as Ni or Ni alloy is used as the conductive material, the binder removal is performed. The oxygen partial pressure in the atmosphere is preferably 10 ⁻⁴⁵ to 10 ⁵ Pa. When the oxygen partial pressure is less than the above range, the binder removal effect is lowered. If the oxygen partial pressure exceeds the above range, the internal electrode layer tends to oxidize.

As other binder removal conditions, the temperature rising rate is preferably 5 to 300 ° C./hour, more preferably 10 to 100 ° C./hour, and the holding temperature is preferably 180 to 400 ° C., more preferably 200 to 350. The temperature holding time is preferably 0.5 to 24 hours, more preferably 2 to 20 hours. The firing atmosphere is preferably air or a reducing atmosphere, and as an atmosphere gas in the reducing atmosphere, for example, a mixed gas of N ₂ and H ₂ is preferably used after being humidified.

The atmosphere at the time of green chip firing may be appropriately determined according to the type of the conductive material in the electrode layer paste, but when a base metal such as Ni or Ni alloy is used as the conductive material, the oxygen partial pressure in the firing atmosphere Is preferably 10 ⁻⁷ to 10 ⁻³ Pa. When the oxygen partial pressure is less than the above range, the conductive material of the internal electrode layer may be abnormally sintered and may be interrupted. Further, when the oxygen partial pressure exceeds the above range, the internal electrode layer tends to be oxidized.

  Moreover, the holding temperature at the time of baking becomes like this. Preferably it is 1100-1400 degreeC, More preferably, it is 1150-1380 degreeC, More preferably, it is 1200-1350 degreeC. If the holding temperature is lower than the above range, the densification becomes insufficient. Reduction of the body porcelain composition is likely to occur.

As other firing conditions, the rate of temperature rise is preferably 50 to 500 ° C./hour, more preferably 200 to 300 ° C./hour, and the temperature holding time is preferably 0.5 to 8 hours, more preferably 1 to 3 hours. The time and cooling rate are preferably 50 to 500 ° C./hour, more preferably 200 to 300 ° C./hour. Further, the firing atmosphere is preferably a reducing atmosphere, and as the atmosphere gas, for example, a mixed gas of N ₂ and H ₂ is preferably used by humidification.

  When firing in a reducing atmosphere, it is preferable to anneal the capacitor element body. Annealing is a process for re-oxidizing the dielectric layer, and this can significantly increase the IR lifetime, thereby improving the reliability.

  The oxygen partial pressure in the annealing atmosphere is preferably 0.1 Pa or more, particularly 0.1 to 10 Pa. When the oxygen partial pressure is less than the above range, it is difficult to reoxidize the dielectric layer, and when it exceeds the above range, the internal electrode layer tends to be oxidized.

  The holding temperature at the time of annealing is preferably 1100 ° C. or less, particularly 500 to 1100 ° C. When the holding temperature is lower than the above range, the dielectric layer is not sufficiently oxidized, so that the IR is low and the IR life tends to be short. On the other hand, if the holding temperature exceeds the above range, not only the internal electrode layer is oxidized and the capacity is lowered, but the internal electrode layer reacts with the dielectric substrate, the capacity temperature characteristic is deteriorated, the IR is lowered, the IR Life is likely to decrease. Note that annealing may be composed of only a temperature raising process and a temperature lowering process. That is, the temperature holding time may be zero. In this case, the holding temperature is synonymous with the maximum temperature.

As other annealing conditions, the temperature holding time is preferably 0 to 20 hours, more preferably 2 to 10 hours, and the cooling rate is preferably 50 to 500 ° C./hour, more preferably 100 to 300 ° C./hour. . Further, as the annealing atmosphere gas, for example, humidified N ₂ gas or the like is preferably used.

In the above-described binder removal processing, firing and annealing, for example, a wetter or the like may be used to wet the N ₂ gas or mixed gas. In this case, the water temperature is preferably about 5 to 75 ° C.

The binder removal treatment, firing and annealing may be performed continuously or independently. When these are performed continuously, after removing the binder, the atmosphere is changed without cooling, and then the temperature is raised to the holding temperature at the time of baking to perform baking, and then cooled to reach the annealing holding temperature. Sometimes it is preferable to perform annealing by changing the atmosphere. On the other hand, when performing these independently, at the time of firing, after raising the temperature under N ₂ gas atmosphere with N ₂ gas or wet to the holding temperature of the binder removal processing, further continuing the heating to change the atmosphere Preferably, after cooling to the holding temperature at the time of annealing, it is preferable to change to the N ₂ gas or humidified N ₂ gas atmosphere again and continue cooling. In annealing, the temperature may be changed to a holding temperature in an N ₂ gas atmosphere, and then the atmosphere may be changed, or the entire annealing process may be a humidified N ₂ gas atmosphere.

The sintered body (element main body 10) thus obtained is subjected to end surface polishing, for example, by barrel polishing, sand blasting or the like, and then the terminal electrode paste is baked to form the terminal electrode 4. The firing conditions of the terminal electrode paste are preferably, for example, about 10 minutes to 1 hour at 600 to 800 ° C. in a humidified mixed gas of N ₂ and H ₂ . Then, if necessary, a pad layer is formed on the terminal electrode 4 by plating or the like. In addition, what is necessary is just to prepare the paste for terminal electrodes similarly to the above-mentioned paste for electrode layers.
The multilayer ceramic capacitor of the present invention thus manufactured is mounted on a printed circuit board by soldering or the like and used for various electronic devices.

The present invention is not limited to the above-described embodiment, and can be variously modified within the scope of the present invention.
For example, in the above-described embodiment, the multilayer ceramic capacitor is exemplified as the multilayer electronic component according to the present invention. However, the multilayer electronic component according to the present invention is not limited to the multilayer ceramic capacitor and has the above-described configuration. Anything is fine.

  Hereinafter, although this invention is demonstrated based on a more detailed Example, this invention is not limited to these Examples.

Example 1
Preparation of outer green sheet paste and outer interlayer green sheet paste First, as a starting material, BaTiO ₃ powder as a main component raw material, and MgO, MnO, Y ₂ O ₃ , V ₂ O ₅ , SiO as auxiliary component raw materials ₂ and Cr ₂ O ₃ were prepared. Then, these starting materials were wet mixed by a ball mill for 16 hours to prepare a dielectric material. In this example, a raw material having an average particle diameter Rgo of 0.3 μm was used as the dielectric raw material.

  Next, the dielectric material prepared above: 100 parts by weight, acrylic resin: 4.8 parts by weight, ethyl acetate: 100 parts by weight, mineral spirit: 6 parts by weight, toluene: 4 parts by weight Were mixed into a paint to prepare an outer green sheet paste and an outer interlayer green sheet paste.

Preparation of inner interlayer green sheet paste The inner interlayer green sheet paste was the same as the outer green sheet paste and outer interlayer green sheet paste, except that a raw material having an average particle size Rgc of 0.35 μm was used as the dielectric raw material. A paste was prepared.

  That is, in this example, the average particle diameter Rgo of the dielectric material contained in the outer green sheet paste and the outer interlayer green sheet paste, and the average particle diameter Rgc of the dielectric material contained in the inner interlayer green sheet paste The ratio (Rgo / Rgc) was set to Rgo / Rgc = 0.85.

Preparation of electrode layer paste Ni particles: 44.6 parts by weight, BaTiO ₃ powder having an average particle size of 0.1 μm: 8 parts by weight, terpineol: 52 parts by weight, ethyl cellulose: 3 parts by weight, benzotriazole: 0 .4 parts by weight were kneaded with three rolls and slurried to prepare an electrode layer paste.

Formation of Green Chip Next, using each paste prepared above, a green chip was formed by the following method.
First, using an outer interlayer green sheet paste and an inner interlayer green sheet paste, an interlayer green sheet was formed on a PET film so that the thickness after drying was 2.5 μm. That is, in this example, the outer interlayer green sheet and the inner interlayer green sheet were both set to the same thickness of 2.5 μm.
And after using the electrode layer paste to print the electrode paste film in a predetermined pattern, the interlayer green sheet having the electrode paste film was obtained by peeling the sheet from the PET film.
On the other hand, an outer green sheet was formed on the PET film using an outer green sheet paste so that the thickness after drying was 10 μm, and then the sheet was peeled from the PET film.

  Next, a plurality of interlayer green sheets on which the electrode paste film is formed are laminated to form an inner layer portion laminate that will constitute the inner layer portion 100 after firing, and an upper end surface and a lower end surface in the stacking direction of the laminate A green chip was obtained by laminating a plurality of outer green sheets. In this example, the number of outer interlayer green sheets stacked was the mth layer from the upper end surface and the lower end surface in the stacking direction of the inner layer laminate (where m is a value shown in Table 1). ), A plurality of samples (sample numbers 1 to 8 shown in Table 1) having different numbers of laminated outer interlayer green sheets were prepared.

Next, the green chip was cut into a predetermined size and subjected to binder removal processing, firing and annealing under the following conditions to obtain a multilayer ceramic fired body.
The binder removal treatment conditions were temperature rising rate: 30 ° C./hour, holding temperature: 250 ° C., temperature holding time: 8 hours, and atmosphere: in the air.
Firing conditions were: temperature rising rate: 200 ° C./hour, holding temperature: 1250 ° C., temperature holding time: 2 hours, cooling rate: 300 ° C./hour, atmospheric gas: humidified N ₂ + H ₂ mixed gas (oxygen partial pressure: 10 ⁻² Pa).
The annealing conditions were as follows: temperature rising rate: 200 ° C./hour, holding temperature: 1000 ° C., temperature holding time: 2 hours, cooling rate: 300 ° C./hour, atmospheric gas: humidified N ₂ gas (oxygen partial pressure: 10 ⁻¹ Pa).
Note that a wetter with a water temperature of 5 to 75 ° C. was used for humidifying the atmospheric gas during firing and annealing.

  Next, after polishing the end face of the obtained multilayer ceramic fired body by sand blasting, a Cu paste is applied as a terminal electrode, then baking is performed, and a plating treatment is performed thereon, whereby the multilayer ceramic shown in FIG. A capacitor sample was obtained.

  The size of the obtained capacitor sample is 1.0 mm × 0.5 mm × 0.5 mm, the number of interlayer dielectric layers sandwiched between internal electrode layers is 160, and the thickness of the interlayer dielectric layer per layer Was 1.8 μm.

  Next, for each obtained capacitor sample, the average crystal grain size ratio (Rfo / Rfc) of the dielectric particles after firing, the number of electrode voids present at each corner, the number of occurrence of flat cracks, and Each occurrence of delamination was measured.

Average grain size ratio of dielectric particles after firing (Rfo / Rfc)
The obtained capacitor sample was cut so that the cut surface had a cross section shown in FIG. 2 (a surface parallel to the end surface on which the terminal electrode 4 was formed), and the cut surface was polished. Then, the polished surface is observed with a microscope, and the dielectric particles constituting each of the interlayer dielectric layers 2 of the total 30 layers from the upper outer layer portion 200 side and the lower outer layer portion 300 side to the fifteenth layer, respectively. The average crystal grain size Rfo [μm] and the average crystal grain size Rfc [μm] of the dielectric particles constituting the interlayer dielectric layer 2 located in the other part were measured. The average crystal grain size of each dielectric layer was measured by the code method on the assumption that the shape of the dielectric particle was a sphere by the code method. The average crystal grain size was an average value of 250 measurement points. And from the obtained result, the average crystal grain size ratio (Rfo / Rfc) of the dielectric particles after firing was determined. The results are shown in Table 1.

Capacitor samples obtained for the number of electrode gaps in each corner are cut so that the cut surface is the cross section shown in FIG. 2 (a surface parallel to the end surface on which the terminal electrode 4 is formed). Polished. Then, the polished surface is observed with a microscope, and the number N1 and N2 of electrode gap portions in the first and second corner portions of the upper electrode layer, the number of electrode gap portions in the first and second corner portions of the lower electrode layer. The existence numbers N3 and N4 were obtained, and the average value [(N1 + N2 + N3 + N4) / 4] was calculated and used as the number of electrode gap portions. In this example, the average value of five measurement samples was used. The results are shown in Table 1.

  4A shows a micrograph of the lower electrode layer first corner portion of the sample number 5 and FIG. 4B shows a first corner portion of the lower electrode layer of the sample number 9 according to Example 2 described later in FIG. The micrographs of are shown respectively. 4A and 4B, sample No. 5, which is an example of the present invention, has a small number of electrode gaps (black portions in the figure), whereas comparison is made. In sample No. 9 as an example, it can be confirmed that a large number of electrode gaps exist.

For each capacitor sample from which the number of occurrences of flat cracks was obtained, the capacitor sample that had been subjected to baking and plating of the terminal electrode was polished, and the cross section shown in FIG. 2 (the plane parallel to the end surface on which the terminal electrode 4 was formed) was The presence or absence of occurrence of flat cracks was confirmed by observation. In the present embodiment, as shown in FIG. 5 (A) or FIG. 5 (B), it occurred from the plane (upper surface or lower surface) to the side surface (end surface where the terminal electrode 4 was not formed) through the inside of the element body. The crack was regarded as a flat crack, and the presence or absence of the crack was confirmed. The confirmation of the presence or absence of a flat crack was performed on 100 capacitor samples. As a result of the cross-sectional inspection, the number of samples having flat side cracks with respect to 100 capacitor samples was obtained. The results are shown in Table 1.

For each capacitor sample from which the number of occurrences of delamination was obtained, the baked substrate was polished, and the laminated state in the cross section (surface parallel to the end surface on which the terminal electrode 4 was formed) shown in FIG. The presence or absence of delamination at the interface between the internal electrode layer 3 and the interlayer dielectric layer 2 was confirmed. The presence or absence of delamination was confirmed for 100 capacitor samples. As a result of the cross-sectional inspection, the number of samples in which delamination occurred was obtained for 100 capacitor samples. The results are shown in Table 1.

In Table 1, sample number 1 is a sample in which all interlayer green sheets were formed using the inner interlayer green sheet paste. Moreover, the number of layers of the outer interlayer green sheet formed using the outer interlayer green sheet paste was set to the numbers shown in Table 1 from the upper end surface and the lower end surface. That is, in Sample No. 5, for example, the number of layers from the upper end surface is 15 and the number of layers from the lower end surface is 15, for a total of 30 layers.

  As shown in Table 1, as a dielectric material to be included in the outer interlayer green sheet paste, a dielectric material having the same average particle diameter as that of the outer green sheet paste that constitutes the outer dielectric layer 20 after firing. In sample numbers 2 to 7 which were used and the number of outer interlayer green sheets was 1 layer, 2 layers, 5 layers, 15 layers, 20 layers and 30 layers, respectively, the following results were obtained. . That is, in these samples, the average crystal grain size ratio (Rfo / Rfc) of the dielectric particles after firing is in the range of 0.55 ≦ Rfo / Rfc ≦ 0.95, and the number of electrode voids present in each corner portion. However, it became the range of 1 or more and 20 or less, neither a flat side crack nor delamination was confirmed, and it became a favorable result.

  In these sample numbers 2 to 7, the sintering start temperature Tgo [° C.] of the dielectric raw material contained in the outer green sheet paste and the dielectric raw material contained in the outer interlayer green sheet paste, the inner interlayer The difference (Tgo−Tgc) from the sintering start temperature Tgc [° C.] of the dielectric material contained in the green sheet paste was Tgo−Tgc = −20 ° C.

  On the other hand, in Sample No. 1 which is a sample in which all the interlayer green sheets are formed using the inner interlayer green sheet paste (that is, a sample in which the outer interlayer green sheet is not formed), the electrode at each corner portion As a result, the number of voids was excessive, flat cracks were generated, and the reliability was poor. Further, in Sample No. 8 in which the number of outer interlayer green sheets was 45, the number of electrode gaps at each corner was too small, resulting in delamination and poor reliability. .

Example 2
The same as in Example 1 except that the same dielectric material (average particle size 0.35 μm) was used as the dielectric material contained in the outer green sheet paste and the dielectric material contained in the inner interlayer green sheet paste. Thus, a multilayer ceramic capacitor sample (Sample No. 9) was produced. That is, Rgo / Rgc = 1.00. The obtained capacitor sample was evaluated in the same manner as in Example 1. The results are shown in Table 2.

Example 3
Ratio (Rgo / Rgc) of the average particle diameter Rgo of the dielectric material contained in the outer green sheet paste and the outer interlayer green sheet paste and the average particle diameter Rgc of the dielectric material contained in the inner interlayer green sheet paste ) Was changed as shown in Table 2, and samples of multilayer ceramic capacitors (Sample Nos. 10 to 15) were produced in the same manner as Sample No. 5 of Example 1. The obtained capacitor sample was evaluated in the same manner as in Example 1. The results are shown in Table 2.

  In Example 3, the dielectric material contained in the outer green sheet paste and the outer interlayer green sheet paste was fixed at an average particle diameter Rgc of the dielectric material contained in the inner interlayer green sheet paste at 0.35 μm. Rgo / Rgc was adjusted by changing the average particle diameter Rgo of the raw material.

In Table 2, Sample No. 5 is the same sample as Sample No. 5 of Example 1.

  From Table 2, in Sample Nos. 9 and 10 in which the average particle diameter ratio (Rgo / Rgc) of the dielectric material is Rgo / Rgc> 0.95, the number of electrode gaps at each corner is too large. As a result, flat cracks occurred, resulting in poor reliability. Further, in the sample number 15 in which the average particle diameter ratio (Rgo / Rgc) of the dielectric material is Rgo / Rgc <0.50, the number of electrode voids existing at each corner is too small, and delamination is caused. Occurred, resulting in poor reliability.

Example 4
Multilayer ceramic capacitor samples (Sample Nos. 16 to 18) were produced in the same manner as Sample No. 3 in Example 1 except that the thickness of the outer interlayer green sheet was changed as shown in Table 3. The obtained capacitor sample was evaluated in the same manner as in Example 1. The results are shown in Table 3.
That is, in Example 4, the number of layers of the outer interlayer green sheet was fixed to two, and a plurality of samples were produced in which the thickness of the outer interlayer green sheet was changed.

In Table 3, Sample No. 3 is the same sample as Sample No. 3 in Example 1.

  From Table 3, it can be confirmed that even when the thickness of the outer interlayer green sheet is changed and the thickness of the outer interlayer green sheet is different from the thickness of the inner interlayer green sheet, the same good results can be obtained. .

FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a schematic sectional view of the multilayer ceramic capacitor taken along line II-II shown in FIG. FIG. 3 is a cross-sectional view of a main part of the multilayer ceramic capacitor according to one embodiment of the present invention. 4A is a cross-sectional photograph of the main part of the multilayer ceramic capacitor according to the embodiment of the present invention, and FIG. 4B is a cross-sectional photograph of the main part of the multilayer ceramic capacitor according to the comparative example. FIG. 5A and FIG. 5B are diagrams for explaining a flat crack in the multilayer ceramic capacitor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multilayer ceramic capacitor 10 ... Capacitor element body 2 ... Interlayer dielectric layer 20 ... Outer dielectric layer 22 ... Side margin 3 ... Internal electrode layer 30 ... Electrode gap part 4 ... Terminal electrode 100 ... Inner layer part 200 ... Upper outer layer part

Claims (9)

An inner layer portion in which internal electrode layers and interlayer dielectric layers are alternately stacked;
A multilayer electronic component having an element body composed of an upper outer layer portion and a lower outer layer portion, which are arranged on an upper end surface and a lower end surface in the stacking direction of the inner layer portion and are composed of an outer dielectric layer,
The internal electrode layers are alternately formed on a pair of opposing end faces parallel to the stacking direction of the element body, and a pair of terminal electrodes is formed on the pair of end faces where the internal electrode layers are exposed. Formed,
The number of laminated interlayer dielectric layers is 100 or more,
In the cut surface when cutting the element body in a plane parallel to the end surface where the pair of terminal electrodes are formed,
The average length of the internal electrode layers in the length direction of the plurality of internal electrode layers in the cut surface is 0.15 mm or more,
One end in the length direction of the plurality of internal electrode layers in the cut surface is a first end, the other end is a second end,
Of the internal electrode layers, each internal electrode layer from the upper outer layer side to the fifteenth layer is an upper electrode layer, and each internal electrode layer from the lower outer layer part side to the fifteenth layer is a lower electrode layer,
In the upper electrode layer, a portion having a length of 40 μm from the first end portion and the second end portion toward the center side of the internal electrode layer is divided into an upper electrode layer first corner portion, an upper electrode layer second corner portion, and
In the lower electrode layer, a portion having a length of 40 μm from the first end portion and the second end portion toward the center side of the internal electrode layer is divided into a lower electrode layer first corner portion and a lower electrode layer second corner, respectively. Part
Regarding the electrode gap that is present in the formation portion of the internal electrode layer and is substantially void,
The number N1 of electrode gaps in the first corner of the upper electrode layer, the number N2 of electrode gaps in the second corner of the upper electrode layer, the number of electrode gaps in the first corner of the lower electrode layer The multilayer electronic component, wherein an average value [(N1 + N2 + N3 + N4) / 4] of N3 and the number N4 of electrode gaps in the second corner portion of the lower electrode layer is 1 or more and 20 or less. From the upper outer layer side and the lower outer layer side, an average crystal grain size Rfo [μm] of dielectric particles constituting each of the interlayer dielectric layers of a total of 30 layers up to the 15th layer,
2. The multilayer type according to claim 1, wherein the average crystal grain size Rfc [μm] of the dielectric particles constituting the interlayer dielectric layer located in the other part is 0.55 ≦ Rfo / Rfc ≦ 0.95. Electronic components.   3. The multilayer electronic component according to claim 1, wherein an average thickness of the interlayer dielectric layer is 3 μm or less.   The multilayer electronic component according to claim 1, wherein the internal electrode layer has a thickness of 2 μm or less.   The multilayer electronic component according to claim 1, wherein the conductive material included in the internal electrode layer is Ni or a Ni alloy. An inner layer portion in which internal electrode layers and interlayer dielectric layers are alternately stacked;
A method of manufacturing a multilayer electronic component having an element body comprising an upper outer layer portion and a lower outer layer portion which are disposed on the upper end surface and the lower end surface in the stacking direction of the inner layer portion and are composed of outer dielectric layers. And
A step of forming an interlayer green sheet containing the dielectric material after becoming the interlayer dielectric layer after firing;
The outer dielectric layer after firing, forming an outer green sheet containing a dielectric material; and
Forming an electrode paste film to be an internal electrode layer after firing on the surface of the interlayer green sheet;
Laminating the interlayer green sheet having the electrode paste film so that the total number of laminated layers of the interlayer green sheets is 100 or more, and obtaining a laminate for an inner layer part;
Laminating the outer green sheet on the upper end surface and the lower end surface in the stacking direction of the inner layer laminate, to obtain a green chip;
Firing the green chip,
With respect to the interlayer green sheet that becomes the interlayer dielectric layer after firing, it is located from the upper end surface and the lower end surface in the stacking direction of the inner layer laminate to the mth layer (where m is 1 or more and 30 or less). When the interlayer green sheet to be used is the outer interlayer green sheet, and the interlayer green sheet to be positioned in the other part is the inner interlayer green sheet,
A dielectric material having the same sintering start temperature is used as the dielectric material contained in the outer green sheet and the dielectric material contained in the outer interlayer green sheet, and the outer green sheet and the outer interlayer are used. The relationship between the sintering start temperature Tgo [° C.] of the dielectric material contained in the green sheet and the sintering start temperature Tgc [° C.] of the dielectric material contained in the inner interlayer green sheet is Tgo <Tgc. A method for producing a multilayer electronic component, comprising:   The method of manufacturing a multilayer electronic component according to claim 6, wherein a relationship between the Tgo and Tgc is set to −100 ° C. ≦ Tgo−Tgc ≦ −5 ° C.   As the dielectric material contained in the outer green sheet and the dielectric material contained in the outer interlayer green sheet, a dielectric material having the same average particle diameter is used, and the outer green sheet and the outer interlayer green are used. When the average particle size of the dielectric material contained in the sheet is Rgo [μm] and the average particle size of the dielectric material contained in the inner interlayer green sheet is Rgc [μm], the Rgo and Rgc The method of manufacturing a multilayer electronic component according to claim 6, wherein the relationship is Rgo <Rgc.   The method for manufacturing a multilayer electronic component according to claim 8, wherein a relationship between the Rgo and Rgc is 0.50 ≦ Rgo / Rgc ≦ 0.95.