JP2007281422A - 薄膜半導体装置および薄膜半導体装置の製造方法 - Google Patents
薄膜半導体装置および薄膜半導体装置の製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
【解決手段】レーザ光Lhの照射によって多結晶化した活性領域5aを有する半導体薄膜5と、活性領域5aを横切るように設けられたゲート電極9とを備えた薄膜半導体装置において、ゲート電極9と重なる活性領域5aのチャネル部Cには、ゲート電極9に沿って一連の結晶粒界aが延設されている。この結晶粒界aは、チャネル部Cを横切ると共に、チャネル長L方向に周期的に設けられている。
【選択図】図1
Description
図1(a)は、実施形態の薄膜半導体装置の構成を示す平面図であり、図1(b)は図1(a)におけるA部の拡大平面図である。これらの図に示す薄膜半導体装置1は、同一の基板3上に複数の薄膜トランジスタTFTを設けてなる。尚、図面においては、1つの薄膜トランジスタTFTのみを図示している。
以下、図1および図2に示した構成の薄膜半導体装置1の製造方法を図3に基づいて、他の図面を参照しつつ説明する。
図5(a)を用いて説明した結晶化工程を適用して複数の薄膜トランジスタを形成した(図1参照)。
図5(b)を用いて説明した結晶化工程を適用して複数の薄膜トランジスタを形成した(図1参照)。
実施例2と同様に、図5(b)を用いて説明した結晶化工程を適用して複数の薄膜トランジスタを形成した。
従来構成のエキシマレーザーを用いた結晶化工程を適用して複数の薄膜トランジスタを形成した。
Claims (10)
- エネルギービームの照射によって多結晶化した活性領域を有する半導体薄膜と、当該活性領域を横切るように設けられたゲート電極とを備えた薄膜半導体装置において、
前記ゲート電極と重なる前記活性領域のチャネル部には、当該ゲート電極に沿って一連の結晶粒界が延設されており、
前記結晶粒界は、前記チャネル部を横切ると共に、チャネル長方向に周期的に設けられている
ことを特徴とする薄膜半導体装置。 - 請求項1記載の薄膜半導体装置において、
前記チャネル部には、前記結晶粒界が2本以上の所定数で設けられている
ことを特徴とする薄膜半導体装置。 - 請求項1記載の薄膜半導体装置において、
前記活性領域は、少なくとも前記チャネル部の全面が多結晶化された領域である
ことを特徴とする薄膜半導体装置。 - 請求項1記載の薄膜半導体装置において、
前結晶粒界は、所定ピッチを保って前記エネルギービームを平行に走査させることによって生じる走査方向と平行な結晶粒界である
ことを特徴とする薄膜半導体装置。 - 請求項1記載の半導体薄膜装置において、
前記結晶粒界の間には、当該結晶粒界の延設方向に凸となる三日月形状の結晶粒が、当該結晶粒界の延設方向に沿って配列されている
ことを特徴とする薄膜半導体装置。 - 半導体薄膜にエネルギービームを照射することにより当該半導体薄膜の活性領域を結晶化する工程と、前記活性領域を横切る形状にゲート電極を形成する工程とを備えた薄膜半導体装置の製造方法において、
前記活性領域を結晶化する工程では、前記エネルギービームが重なりを持つ範囲内で当該エネルギービームの照射位置を所定の移動方向に所定ピッチで移動させることにより、当該移動方向と異なる方向に結晶粒界を延設しながら当該活性領域を多結晶化し、
前記ゲート電極を形成する工程では、前記結晶粒界の延設方向に沿って当該ゲート電極を形成する
ことを特徴とする薄膜半導体装置の製造方法。 - 請求項6記載の薄膜半導体装置の製造方法において、
前記活性領域を結晶化する工程では、前記エネルギービームの各照射位置において前記移動方向と異なる走査方向に当該エネルギービームを走査させながら照射することにより、当該走査方向と平行な前記結晶粒界を前記所定ピッチで形成する
ことを特徴とする薄膜半導体装置の製造方法。 - 請求項7記載の薄膜半導体装置の製造方法において、
前記活性領域を結晶化する工程では、爆発的結晶化が生じるように前記エネルギービームの照射を行う
ことを特徴とする薄膜半導体装置の製造方法。 - 請求項7記載の薄膜半導体装置の製造方法において、
前記活性領域を結晶化する工程では、
前記半導体薄膜を完全溶融させると共に、
前記エネルギービームの走査中心が当該エネルギービームの走査に伴って最後に結晶化されるように当該エネルギービームの照射条件を設定することによって、当該走査中心に前記結晶粒界を形成する
ことを特徴とする薄膜半導体装置の製造方法。 - 請求項6記載の薄膜半導体装置の製造方法において、
前記活性領域を結晶化する工程では、前記エネルギービームのビームプロファイルをガウシアンカーブにする
ことを特徴とする薄膜半導体装置の製造方法。
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JP2006347052A JP4169072B2 (ja) | 2006-03-13 | 2006-12-25 | 薄膜半導体装置および薄膜半導体装置の製造方法 |
TW096107732A TW200805669A (en) | 2006-03-13 | 2007-03-06 | Thin-film semiconductor device and manufacturing method thereof |
US11/683,272 US8089071B2 (en) | 2006-03-13 | 2007-03-07 | Thin film semiconductor device having crystal grain boundaries cyclically traversing a channel part and method for manufacturing same |
KR1020070022974A KR20070093339A (ko) | 2006-03-13 | 2007-03-08 | 박막 반도체 장치 및 박막 반도체 장치의 제조 방법 |
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Cited By (2)
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JP2011082545A (ja) * | 2010-11-24 | 2011-04-21 | Sony Corp | 熱処理装置、熱処理方法、半導体装置の製造方法および表示装置の製造方法 |
US8278163B2 (en) | 2008-07-30 | 2012-10-02 | Sony Corporation | Semiconductor processing apparatus and semiconductor processing method |
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KR20100036624A (ko) * | 2008-09-30 | 2010-04-08 | 삼성전자주식회사 | 박막트랜지스터 기판 및 이를 갖는 유기발광 표시장치 |
JP6471379B2 (ja) * | 2014-11-25 | 2019-02-20 | 株式会社ブイ・テクノロジー | 薄膜トランジスタ、薄膜トランジスタの製造方法及びレーザアニール装置 |
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JPH07249591A (ja) * | 1994-03-14 | 1995-09-26 | Matsushita Electric Ind Co Ltd | 半導体薄膜のレーザーアニール方法及び薄膜半導体素子 |
KR100296109B1 (ko) * | 1998-06-09 | 2001-10-26 | 구본준, 론 위라하디락사 | 박막트랜지스터제조방법 |
TW445545B (en) * | 1999-03-10 | 2001-07-11 | Mitsubishi Electric Corp | Laser heat treatment method, laser heat treatment apparatus and semiconductor device |
WO2003018882A1 (en) * | 2001-08-27 | 2003-03-06 | The Trustees Of Columbia University In The City Of New York | Improved polycrystalline tft uniformity through microstructure mis-alignment |
JP2003077834A (ja) | 2001-09-05 | 2003-03-14 | Matsushita Electric Ind Co Ltd | 結晶化半導体膜の形成方法およびその製造装置と薄膜トランジスタの製造方法およびそれらを用いた表示装置 |
JP4279498B2 (ja) * | 2002-02-28 | 2009-06-17 | 株式会社 液晶先端技術開発センター | 半導体薄膜の形成方法、半導体薄膜の形成装置および結晶化方法 |
JP2003332350A (ja) | 2002-05-17 | 2003-11-21 | Hitachi Ltd | 薄膜半導体装置 |
KR100956947B1 (ko) * | 2003-06-12 | 2010-05-12 | 엘지디스플레이 주식회사 | 실리콘 결정화 방법 |
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- 2007-03-07 US US11/683,272 patent/US8089071B2/en not_active Expired - Fee Related
- 2007-03-08 KR KR1020070022974A patent/KR20070093339A/ko not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8278163B2 (en) | 2008-07-30 | 2012-10-02 | Sony Corporation | Semiconductor processing apparatus and semiconductor processing method |
JP2011082545A (ja) * | 2010-11-24 | 2011-04-21 | Sony Corp | 熱処理装置、熱処理方法、半導体装置の製造方法および表示装置の製造方法 |
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TW200805669A (en) | 2008-01-16 |
US20080054266A1 (en) | 2008-03-06 |
JP4169072B2 (ja) | 2008-10-22 |
KR20070093339A (ko) | 2007-09-18 |
US8089071B2 (en) | 2012-01-03 |
TWI342072B (ja) | 2011-05-11 |
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