JP2007279343A - Lighting display circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact and economical lighting display circuit which performs lighting display of an LED display panel by using a dynamic display control method, and to flexibly cope with differences in LED display panel constitution. <P>SOLUTION: Display information generated by a computer 1 is written to a dual-port RAM 2 from its one port. A display control circuit 3 composed of a PLD reads display information to be displayed on LED elements in one line of the LED display panel out of the dual-port RAM 2 and sets the display information in corresponding registers 34 each time a timing circuit 32 outputs a timing signal tg to apply the display information to cathodes of the LED elements connected to respective register outputs, and also activates common signal lines connecting anodes of the LED elements in a line with an output of a common signal generating circuit 35 at the same time to light the LED elements in a line for display. Here, the LED elements in a line to display the display information are changed in order for every timing signal tg to scan the entire LED display panel, thus performing the dynamic lighting display. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a lighting display circuit of an LED display device, and more particularly, to a lighting display circuit that uses a dual port RAM to simplify and reduce the circuit configuration.

  In an LED display device configured by arranging a large number of LED elements, display information for each LED element generated by the processing device is set in a latch register provided for each LED element, and the set display information is set A lighting display circuit is provided for controlling each LED element to light in response to the above.

  As the lighting display method by the lighting display circuit, there is a method in which a latch register corresponding to all LED elements of the LED display device is provided and static display in which display information corresponding to these registers is set and displayed, and all LED elements are displayed. 1 / P (P: integer) latch registers are provided, and the operation of setting and displaying the display information corresponding to each (total number of LED elements / P) LED elements is repeated to scan all the LED elements. Some of them have dynamic display.

  In the case of the static display method, as many latch registers as the total number of LED elements constituting the display device are necessary, and correspondingly, the address information indicating the display position of the display information output from the processing device is decoded. The decoder for setting the corresponding latch register is also complicated and the circuit scale is increased. Further, when a driver is required for each LED element, the number of drivers is also required for the total number of LED elements.

  On the other hand, in the case of the dynamic display method, when a horizontal M × N LED elements form a display device, a set of M latch registers and an address recorder for setting display information to these are prepared. In addition, display is possible by providing scanning means for repeating M lighting displays N times N times using these, and the circuit configuration as a whole is greatly simplified. Even if a driver is provided, the number is M.

  A known example of a lighting display circuit using a dynamic display method is disclosed in Patent Document 1. FIG. 2 is a circuit block diagram showing a lighting display circuit of this known example. A computer 21 that generates display information, a dual-port RAM 22 that holds the generated display information when the generated display information is input from one of its ports, The LED display panel includes a timing generator unit 23 that generates and outputs various timing signals for display control in synchronization with a clock signal, a shift register 24, a driver 25 with a shift register, a drive side timing generator 26, and a driver 27. 28 display control is performed.

  Now, a total of 768 LED elements are arranged with M = 64 LED display panels 28 in the horizontal direction and N = 12 in the vertical direction, and the shift register 24 has an 8-bit configuration, and the driver 25 with shift register is M. Suppose that it consists of 64 pieces. It is assumed that display information on each LED element is written from the computer 21 to the dual port RAM 22 before it is read for display. When the basic clock signal is input, first, the display information in the top horizontal row (64) of the LED display panel 28 is read and set in the driver 25 under the control of the timing generator unit 23. In this set operation, the address AR for reading the display information displayed on the eight rightmost LED display panels by the timing generator unit 23 is input to the dual port RAM, and the read data DR (8-bit parallel) is input. Is set to the shift register 24 by the set pulse setpulse, and then the shift clock shiftclock is output from the timing generator unit 23 and the set data is serially transferred to the driver 25 with shift register. Next, display information to be displayed on the eight LED elements on the left side of the uppermost rightmost eight LED elements, set to the shift register 24, and serial transfer to the driver 25 with shift register are repeated, and these operations are repeated eight times. Thus, display information for 64 horizontal rows is set in each of the 64 drivers 25.

  When the display information set for one horizontal row is completed, the drive signal Drive is sent from the timing generator unit 23 to the drive-side timing generator 26. In response to this, the timing generator 26 applies the common signal Common first through the driver 27. By outputting to the common line of the upper LED elements, the LED elements in one row are lit up. In the same way, the dynamic lighting display of all the LED elements is performed by repeating the lighting display every second horizontal row from the top in the same manner.

JP 7-319426 A

  According to the known technique described above, the decoding function for setting display information to the corresponding latch register is realized by the control (memory mapping) of the write / read address of the dual port RAM, and reading from the timing generator unit. If the write address AL from the CPU side is set so that the address AR can be generated easily, the decoding process becomes very simple and a complicated decoder IC is not required. In addition, since the latch register is a dynamic display, the number of LED elements may be equal to the number of LED elements for one horizontal row, and the display information is transferred serially to them, so that wiring can be simplified and the device configuration as a whole is small And there is an advantage that can be made economical.

  However, in the technique of the above-described known example, the timing generator unit 23, the driver side timing generator 26, the shift register driver 25 having a latch register function, and the like are configured by individual circuits. It is. Furthermore, since the individual circuit needs to have a configuration corresponding to the number of the LED elements constituting the LED display panel 28 in the horizontal and vertical directions, a circuit corresponding to the structure of the LED display panel is prepared.

  An object of the present invention is to illuminate an inexpensive and configurable LED display device that can further reduce the number of required IC components and easily cope with the difference in the number of LED display panels constituting the LED display panel. It is to provide a display circuit.

In the present invention, N horizontal LED element arrays in which M LED elements are arranged in the horizontal direction are arranged in the vertical direction, and the anode of each LED element in the same horizontal LED element array is used as one common signal line. Further, for each of the M vertical LED element arrays composed of N LED elements arranged in the vertical direction, the cathode of each LED element in the same vertical LED element array is connected to one drive signal line. A lighting display circuit for lighting a configured LED display panel,
Processing means for generating display information for each LED element, dual-port RAM for holding display information generated by this means when input from one of the ports, and held in this dual-port RAM A display control circuit configured by a PLD for controlling the display information read out from the other port and displaying it on the LED display panel;
The PLD periodically generates a timing signal, selects one horizontal LED element row of the LED display panel for each timing signal, and displays display information to be displayed on the LED element row from the dual port RAM. Read, set in N registers in the PLD connected to the N drive signals, and activate the common signal line connected to the selected lateral LED element array to activate the lateral LED Disclosed is a lighting display circuit that is programmed to repeat the operation of performing lighting display of an element row by changing the selected horizontal LED element row for each timing signal.

  By configuring the display control circuit with a PLD, it is possible to significantly reduce the number of components, and further, it is possible to easily cope with changes in the configuration of the LED display panel by changing the programming of the PLD.

  Embodiments of the present invention will be described below. FIG. 3 shows an example of an LED display panel, in which eight 7-segment LEDs containing eight LED elements are arranged in the horizontal direction and twelve in the vertical direction, and the horizontal direction is 8 × 8 = 64. The display panel 5 is composed of a total of 768 LED display panels in the vertical direction. The anodes of the 64 LED display panels in the horizontal row are all connected by one common signal line, and the LED display panel rows in the horizontal row are denoted by # 1 to # 12 in order from the top. Twelve LED elements are arranged at any position in the vertical direction, and the cathodes of the 12 LED elements in one vertical column are connected by the same drive signal line.

  FIG. 1 is a block diagram showing a configuration example of a lighting display circuit according to the present invention, which includes a computer such as a microprocessor 1, a dual port RAM 2, a single PLD (Programmable Logic Device) 3, and a clock source 4. The PLD 3 operates as a display control circuit, and each circuit is realized by programming the PLD 3 so as to realize the functions described below. The register group 34 includes a number of registers in the PLD equal to the number of LED elements for one horizontal row, and is 64 in the case of the LED display panel of FIG. The outputs of these registers are connected as drive signals Drive to the cathodes of the LED elements in a separate vertical column. Further, 12 outputs (common signal C) of the common signal generation circuit 35 (generally the number of LED display panels in the vertical direction of the LED display panel) are connected to each of the drive buffers 6 in FIG.

  In FIG. 1, a computer 1 generates display information for each LED element and writes it to a dual port RAM 2 from one port. This write address is preferably controlled by the computer 1 so as to facilitate generation of a read address at the time of display. The lighting control operation including reading from the dual port RAM 2 for display is performed asynchronously with the writing operation by the computer 1. That is, each circuit in the PLD 3 operates in synchronization with the clock signal from the clock source 4 that is asynchronous with the operation of the computer 1. Hereinafter, the reading and displaying operation will be described with reference to the timing chart of FIG.

  The timing circuit 31 outputs a timing signal tg every period T. When the first timing signal tg1 is input, the read address generation circuit 32 displays display information on the 64 LED elements arranged in the top row (# 1 row) of the LED display panel 5 (FIG. 3). Read addresses for reading are sequentially generated and input to the dual port RAM 2, and the display information thus read is sequentially set by the distribution circuit 33 to the registers (in the register group 34) connected to the drive signal lines. Then, it becomes a drive signal for each LED element in the # 1 column. Meanwhile, at the same time, the common signal generation circuit 35 generates a common signal C1 and supplies it to the anode side of all the LED elements in the # 1 column via the drive buffer 6 corresponding to the # 1 column. By making this common signal active during the period T, each LED element in the # 1 column is lit according to the display information set in the corresponding register.

  In the same manner, the display information to be displayed on the # 2 column LED element is set in the register by the next timing signal tg2, and the display of the # 2 column is turned on by activating the common signal C2 to the # 2 column. The operation is repeated, and when the display lighting of the # 12 column in the bottom row is finished, the operation returns to the # 1 column. By repeating the scanning in the vertical direction in this way, dynamic lighting display is performed.

  As described above, since the display information is distributed and set to each LED element by controlling the write / read address using the dual port RAM, a complicated IC decoder chip is not required, and display control is further performed. Since all the functions on the side are realized by one PLD, the number of parts can be reduced, and the mounting area can be reduced and the cost can be reduced. Furthermore, there is an advantage that it is possible to deal with LED display panels having different numbers of LED elements in the vertical and horizontal directions only by controlling the write address to the dual port RAM by the computer and changing the programming of the PLD.

It is a block diagram which shows the structural example of the lighting display circuit of this invention. It is a block diagram which shows the structural example of the conventional lighting display circuit. It is an example of an LED display panel. It is a time chart which shows operation | movement of the lighting display circuit of FIG.

Explanation of symbols

1 Computer 2 Dual port RAM
3 PLD
5 lighting display circuit 31 timing circuit 32 read address generation circuit 33 distribution circuit 34 register group 35 common signal generation circuit

Claims (1)

N horizontal LED element arrays in which M LED elements are arranged in the horizontal direction are arranged in the vertical direction, the anodes of the LED elements in the same horizontal LED element array are connected to one common signal line, and Each of the M vertical LED element arrays composed of N LED elements arranged in the vertical direction is configured by connecting the cathode of each LED element in the same vertical LED element array to one drive signal line. A lighting display circuit for lighting a display panel,
Processing means for generating display information for each LED element, dual-port RAM for holding display information generated by this means when input from one of the ports, and held in this dual-port RAM A display control circuit configured by a PLD for controlling the display information read out from the other port and displaying it on the LED display panel;
The PLD periodically generates a timing signal, selects one horizontal LED element row of the LED display panel for each timing signal, and displays display information to be displayed on the LED element row from the dual port RAM. Read, set in N registers in the PLD connected to the N drive signals, and activate the common signal line connected to the selected lateral LED element array to activate the lateral LED A lighting display circuit, programmed to repeat the operation of performing lighting display of an element row by changing the selected horizontal LED element row for each timing signal.

Images