JP2007272914A - Voltage generating circuit and reference voltage source circuit employing field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage generating circuit employing field effect transistors stably operated at a high temperature of 80°C or more. <P>SOLUTION: A depression type MOS transistor M2 having a high-concentration n-type polysilicon gate and a depression type MOS transistor M1 having a low-concentration n-type polysilicon gate are connected in series between a VCC and a GND. The gate and source of the MOS transistor M2 are connected (constant current connection: VGS2=0). An n-type channel MOS transistor M3 is provided wherein a gate is connected to a connection part of the gate and source of the MOS transistor M2, a drain is connected to the VCC and the gate is connected to the gate of the MOS transistor M1, respectively. The gate voltage of the MOS transistor M1 is VPTAT=U<SB>T</SB>1n(Ng2/Ng1). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a voltage generation circuit that can be used as a reference voltage, a temperature compensation circuit of a voltage comparator, a temperature sensor, a current source combined with a resistor having a linear temperature characteristic, and particularly, stably operates even at 80 ° C. or higher. The present invention relates to a voltage generation circuit using a field effect transistor (hereinafter, described with an example using a MOS type field effect transistor) that generates a voltage (PTAT: Proportional-To-Absolute-Temperature) proportional to absolute temperature.

  Furthermore, the present invention relates to a reference voltage source circuit used for an analog circuit or the like. In particular, the present invention stably operates even at 80 ° C. or higher and generates a voltage (PTAT: Proportional-To-Absolute-Temperature) proportional to absolute temperature. The present invention relates to a reference voltage source circuit using a field effect transistor having a desired temperature characteristic using a field effect transistor (to be described below using an example using a MOS type field effect transistor).

  Conventionally, a PTAT circuit is known as a voltage generation circuit using a bipolar transistor, and a PTAT circuit using a CMOS transistor in which this technique is realized using a weak inversion region of a MOS transistor has been proposed. As a reference voltage source using CMOS, a voltage source having a positive temperature coefficient is created by operating a field effect transistor in a weak inversion region, and a reference voltage source with little temperature change is realized using this. . Hereinafter, these conventional techniques will be described.

For example, E. Vittoz and J. Fellrath, “CMOS Analog Integrated Circuits Based on Weak Inversion Operation” Vol .. SC-12, No. 3, pp. 224-231, June. 1977 (reference document B). According to this, the drain current Id in the weak inversion region is given by the following formula 1.
I _D = SI _DO exp (VG / nU _T ) {exp (-VS / U _T )-exp (-VD / U _T )}
Here, VG, VS, and VD represent potential differences between the substrate and gate, the substrate and source, and the substrate and drain, respectively, and S is an effective channel width W to channel length L ratio (Weff / Leff), I _D0 is a characteristic current determined by process technology, n is a slope factor (rising characteristic at weak inversion), and U _T is (kT / q). Here, k is a Boltzmann constant, T is an absolute temperature, and q is a charge of a carrier (electron).

In Tsividis and Ulmer, “A CMOS Voltage Reference” IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 6, pp. 774-778, Dec. 1978. (reference A), FIG. As shown in FIG. 5, currents I1 and I2 are passed through n-type channel MOS transistors T1 and T2 which are source-coupled, respectively, and a gate voltage difference (V1−V2) is obtained.
VPTAT = V1-V2 = nU _T ln ((S2I1) / (S1I2))
(See Fig. 4 of Reference A).

In the same figure, if the voltage drop of the base emitter of the bipolar transistor is Vbe and the output Vo,
Vbe + V1 = V2 + Vo
Therefore, the output Vo is
Vo = Vbe + (V1-V2) = Vbe + VPTAT
It becomes. Since the base emitter voltage Vbe of the bipolar transistor of the first term has a negative temperature characteristic with respect to the absolute temperature and the VPTAT of the second term has a positive temperature characteristic, the output voltage Vo obtained by adding them has a flat temperature. Has characteristics.

Also, E. Vittoz and O. Neyroud, “A low-voltage CMOS bandgap reference” IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 3, pp. 573-577, June. 1979. C), as shown in FIG. 2 of the present application, the same current I is supplied to the gate-coupled n-type channel MOS transistors Ta and Tb, and the difference (Vo) between their source voltages is
Vo = VPTAT = U _T ln (1 + Sb / Sa)
(See Fig. 7 in Reference C). Both VPTAT outputs of References A and C are outputs proportional to U _T = (kT / q).

In addition, Oguey et al., “MOS Voltage Reference Based on Polysilicon Gate Work Function Difference” IEEE Journal of Solid--State Circuits, Vol. SC-15, No. 3, Jun. 1980. As shown in FIG. 3, a transistor T1 having a p + polysilicon gate surrounded by a circle and a transistor T2 having an n + polysilicon gate are used as input transistors of the differential amplifier, and the transistors T1 and T2 are used as weak inversion regions. Bias and gate voltage difference VR = VG1-VG2 = ΔVG + U _T ln (ID1S2 / ID2S1)
And the band gap ΔVG of silicon and U _T ln (ID1S2 / ID2S1) of VPTAT.

Furthermore, △ VG = △ VG0−αmT
Because
αmT = U _T ln (ID1S2 / ID2S1)
As a voltage independent of temperature VR = ΔVG0 = 1.20V
(See Fig. 9 of Reference D).

  As described above, in the prior art, PTAT is realized by using a weak inversion region of the gate of a MOS transistor instead of a bipolar transistor. However, when the weak inversion region is used, there are the following problems.

a) In order to make the gate of the MOS transistor a weak inversion region, a minute current bias circuit for weak inversion is required. According to the above reference B (see equation (12) in the document), in order to keep the MOS transistor in the weak inversion region, the drain current is
I ≦ ((n-1) / e 2) SμCoxU T 2
Must be met. Here, n is a slope factor, S is an effective ratio of channel width W to channel length L (Weff / Leff), μ is the mobility of carriers in the channel, and Cox is the electrostatic capacitance of the oxide film per unit area. Capacity.

Specifically, as described in US Patent Specification; USP4327320.4 / 1982 "REFERENCE VOLTAGE SOURCE" Oguey (reference E), n = 1.7; S = 1; μ = 750 cm ² / Vs. Cox = 45 nF / cm ² ; When U _T = 26 mV, the drain current at room temperature must be a very small drain current of ² nA or less.

  b) Problems caused by parasitic diodes. However, when operating with a small drain current of 2 nA or less as described above, it is easily affected by the leakage current of the parasitic diode between the drain and the substrate. For example, on page 268 of Reference D, it is described that a deviation due to leakage current occurs at a temperature of 80 ° C. or higher.

  c) A current bias circuit for correcting the temperature characteristic of the conductivity coefficient is required. As described in Japanese Examined Patent Publication No. 4-65546 (reference G), the difference in threshold voltage between a depletion transistor and an enhancement transistor produced by changing the substrate concentration and channel dope is used, and the conduction coefficients are almost equal. However, RABlauschild et al, "A New NMOS Temperature-Stable Voltage Reference" because pair MOS transistors made by changing the substrate concentration and channel dope have different conductivity coefficients and temperature characteristics. Vol.SC-13, No.6, pp.767-773, Dec.1978. (Reference F) requires a current bias circuit to correct the temperature characteristics of the conductivity coefficient Become.

  An object of the present invention is to solve the above problems and to realize a voltage generation circuit using a field effect transistor that can stably operate even at a high temperature of 80 ° C. or higher and can be used even in strong inversion.

  Another object of the present invention is to provide a reference voltage source circuit using a field effect transistor having a desired temperature characteristic without using a minute current bias circuit or a current bias circuit for correcting the temperature characteristic of a conduction coefficient. Is to provide.

  In more detail, the invention described in claims 1 to 5 is a voltage generator having various circuit configurations using field effect transistors that operate stably even at a high temperature of 80 ° C. or higher and can be used not only for weak inversion but also for strong inversion. The invention according to any one of claims 6 to 8 provides a voltage generation circuit capable of adjusting the impurity concentration by incorporating a resistor. The invention according to claim 10 is to provide a voltage generation circuit provided with a means capable of adjusting the resistance value, and the field effect transistor as a constituent element is constituted by a field effect transistor of a conductivity type different from the above. An object of the present invention is to provide a voltage generation circuit.

  In order to achieve the above object, the invention according to claim 1 (see FIGS. 6 to 16) uses a plurality of field effect transistors having gates partially having the same conductivity type and different impurity concentration differences. The invention according to claim 2 is characterized in that the impurity concentration difference is set to one digit or more.

  According to a third aspect of the present invention (see FIGS. 6 to 7), the gates of the first field effect transistor (M1) and the second field effect transistor (M2) are connected, and the first field effect transistor is connected. A difference between the source voltages of (M1) and the second field effect transistor (M2) is output.

  According to a fourth aspect of the present invention (see FIGS. 8 to 11), the sources of the first field effect transistor (M1) and the second field effect transistor (M2) are connected, and the first field effect transistor is connected. A difference in gate voltage between (M1) and the second field effect transistor (M2) is output.

  In the invention according to claim 5 (see FIGS. 8 to 16), between the gate and the source of one of the first field effect transistor (M1) and the second field effect transistor (M2). The voltage is set to 0 volts and the gate-source voltage of the other field effect transistor is output.

  In the invention according to claim 7 (see FIG. 12A), the second field effect transistor (M2) has a depletion type high concentration n type gate in which the gate and the source are connected. The first field effect transistor (M1) is an n-type channel field effect transistor having a low-concentration n-type gate having a drain connected to the source of the second field effect transistor (M2). And a third n-type channel field effect transistor (M3) and a resistor (R) connected in series, and the third n-type channel field effect transistor (M3) and the resistor (R) A source follower circuit for connecting the gate of one field effect transistor (M1) to give the gate potential of the first field effect transistor (M1), It is characterized in that an output gate potential of the first field effect transistor (M1).

  According to the seventh aspect of the invention (see FIG. 13A), the third n-channel field effect transistor (M3), the first resistor (R1), and the second resistor (R2) connected in series. ), The gate of the first field effect transistor (M1) is connected to the connection point of the third n-type channel field effect transistor (M3) and the first resistor (R1), and the first field effect transistor ( A source follower circuit that provides a gate potential of M1) is provided, and the potential at the connection point of the first resistor (R1) and the second resistor (R2) is output.

  In the invention according to claim 8 (see FIG. 14A), the third n-channel field effect transistor (M3), the first resistor (R1), and the second resistor (R2) connected in series. The gate of the first field effect transistor (M1) is connected to the connection point of the first resistor (R1) and the second resistor (R2), and the gate potential of the first field effect transistor (M1) is A source follower circuit is provided, and a potential at a connection point between the third n-type channel MOS transistor (M3) and the first resistor (R1) is output.

  According to the ninth aspect of the present invention, the values of the first resistance (R1) and the second resistance (R2) can be adjusted by laser trimming or the like after the diffusion and film formation steps in manufacturing. It is a feature.

  The invention according to claim 10 (see FIGS. 12B, 13B, and 14B) includes a first field effect transistor (M1), which is an n-type channel field effect transistor, and a second electric field. The effect transistor (M2) is changed to a p-type channel field effect transistor.

  According to a twelfth aspect of the present invention, there is provided a voltage source circuit having a positive temperature coefficient composed of a plurality of field effect transistors having semiconductor gates having at least a part of the same conductivity type and different impurity concentrations, and at least a part of a different type of conductive A voltage source circuit having a negative temperature coefficient composed of a plurality of field effect transistors having a type semiconductor gate is provided (see FIGS. 18 to 28).

  According to a thirteenth aspect of the present invention, the voltage source circuit having a positive temperature coefficient and the voltage source circuit having a negative temperature coefficient are connected in series having at least some semiconductor gates having different conductivity types or impurity concentrations. The first to third field effect transistors (M1, M2, M3) are characterized (see FIGS. 18 and 19). Furthermore, the invention described in claim 14 is a depletion type of a high concentration n-type gate, an n-type first field effect transistor (M1) in which the gate and the source are connected, and an n-type having a low concentration n-type gate. A channel second field effect transistor (M2) and a p-type gate enhancement type n-channel third field effect transistor (M3) having a gate and a drain connected in series are connected in series. A source follower circuit for providing a gate potential of the field effect transistor (M2) is provided, and the gate voltage of the second field effect transistor is used as a reference voltage output point (see FIG. 18).

  Further, the invention according to claim 15 is the enhancement of the n-type gate, the first field effect transistor (M1) of the p-channel having the gate and the drain connected, and the p-type channel having the low-concentration p-type gate. A second field effect transistor (M2) is connected to a depletion type p-channel third field effect transistor (M3) in which the gate and the source are connected in series, and the second field effect transistor (M2) is connected in series. A source follower circuit for providing a gate potential of the field effect transistor (M2) is provided, and the gate voltage of the second field effect transistor (M2) is used as a reference voltage output point (see FIG. 19).

  According to a sixteenth aspect of the present invention, in the configuration of the twelfth aspect, the voltage source circuit having a positive temperature coefficient and the voltage source circuit having a negative temperature coefficient are at least partially made of semiconductors having different conductivity types or impurity concentrations. It is characterized by comprising first to fourth field effect transistors (M1, M2, M3, M4) having gates (see FIGS. 20 to 25).

  Further, the invention according to claim 17 is the n-type gate depletion type n-channel first field effect transistor (M1) in which the gate and the source are connected and the p-type gate n-type channel second. A high-concentration n that is connected to the field effect transistor (M2) in series, is provided with a source follower circuit that provides the gate potential of the second field effect transistor (M2), and is provided with a gate potential by the source follower circuit A differential amplifier having an n-type channel third field effect transistor (M3) of a n-type gate and a fourth field effect transistor (M4) of a low-concentration n-type gate n-type channel as input transistors, The fourth field effect transistor (M4) has a gate potential as a reference voltage output point (see FIG. 20).

  Further, the invention according to claim 18 is the second field effect transistor (M1) of the p-channel of the n-type gate and the depletion type of the p-type gate and the second of the p-type channel in which the gate and the source are connected. A high-concentration n that is connected to the field effect transistor (M2) in series, is provided with a source follower circuit that applies the gate potential of the second field effect transistor (M2), and is supplied with the gate potential by the source follower circuit A differential amplifier having an n-type channel third field effect transistor (M3) of a n-type gate and a fourth field effect transistor (M4) of a low-concentration n-type gate n-type channel as input transistors, The fourth field effect transistor (M4) has a gate potential as a reference voltage output point (see FIG. 21).

  According to a nineteenth aspect of the present invention, the n-type gate depletion type n-channel first field effect transistor (M1) connected to the gate and the source and the p-type gate n-type channel second A high-concentration n that is connected to the field effect transistor (M2) in series, is provided with a source follower circuit that provides the gate potential of the second field effect transistor (M2), and is provided with a gate potential by the source follower circuit A third field effect transistor (M3) having a n-type channel with a n-type gate and a depletion type n-type gate having a lightly doped n-type gate, and a fourth field effect transistor (M4) having a n-type channel with the gate and source at the GND potential. A connection point of the third field effect transistor (M3) and the fourth field effect transistor (M4) is connected as a reference voltage output point. It is characterized in Rukoto (see FIG. 22).

  According to a twentieth aspect of the present invention, there is provided a second field effect transistor (M1) having a p-type channel having an n-type gate and a depletion type having a p-type gate and a p-type channel having a gate and a source connected to each other. A low-concentration n-type in which a field follower circuit (M2) is connected in series, a source follower circuit for providing the gate potential of the first field effect transistor (M1) is provided, and a gate voltage is applied by the source follower circuit A third p-channel third field effect transistor (M3) of the first gate and a fourth p-channel fourth field effect transistor (M4) in which the gate and drain of the high-concentration n-type gate are connected in series; The connection point between the third field effect transistor (M3) and the fourth field effect transistor (M4) is a reference voltage output point (see FIG. Reference 3).

  The invention according to claim 21 is the n-type gate depletion type n-channel first field effect transistor (M1) in which the gate and the source are connected and the p-type gate n-type channel second. The field effect transistor (M2) is connected in series, and a source follower circuit for providing the gate potential of the second field effect transistor (M2) is provided, and the depletion type of the high-concentration p-type gate is used to connect the gate and the source. A connected p-channel third field effect transistor (M3) and a low-concentration p-type gate p-channel fourth field effect transistor (M4) to which a gate voltage is applied by the source follower circuit are connected in series. The connection point between the third field effect transistor (M3) and the fourth field effect transistor (M4) is used as a reference voltage output point. Is set to characters (see FIG. 24).

  According to a twenty-second aspect of the present invention, a second field effect transistor (M1) having a p-type channel having an n-type gate and a depletion type having a p-type gate and a p-type channel having a gate and a source connected to each other are provided. A high-concentration n-type in which a field follower circuit (M2) is connected in series, a source follower circuit for providing a gate potential of the first field effect transistor (M1) is provided, and a gate voltage is applied by the source follower circuit A depletion-type n-channel third field effect transistor (M3) of the first gate and a fourth n-channel fourth field-effect transistor (M4) in which the gate and the source are connected by a low-concentration n-type gate are connected in series. The connection point between the third field effect transistor (M3) and the fourth field effect transistor (M4) is a reference voltage output point. Are (see Figure 25).

  The invention described in claim 23 is the configuration of claim 12, wherein one or both of a voltage source circuit having a positive temperature coefficient and a voltage source circuit having a negative temperature coefficient are used. (See FIGS. 26 to 28).

  The voltage source circuit having a negative temperature system number is a depletion type of an n-type gate and an n-type channel first field effect transistor (M1) connected to the source and the p A voltage source circuit having a positive temperature system number, comprising a series connection configuration of n-type channel second field effect transistors (M2) in which the gate and drain are connected in the enhancement type of the type gate, the second field effect A n-channel third field effect transistor (M3) having a high-concentration n-type gate to which a gate potential is given by the drain voltage of the transistor and a n-type depletion type having a low-concentration n-type gate and a gate and a source having a GND potential n Type channel fourth field effect transistor (M4) connected in series, third field effect transistor (M3) and fourth field effect transistor A sixth field effect transistor (M5) to which a gate potential is applied by the voltage at the connection point of the transistor (M4) and a depletion type of a lightly doped n-type gate and a sixth n-type channel with the gate and source set at the GND potential. A field-effect transistor (M6) is connected in series, and the connection point between the fifth field-effect transistor (M5) and the sixth field-effect transistor (M6) is a reference voltage output point (FIG. 26). reference).

  According to a twenty-fifth aspect of the present invention, a voltage source circuit having a negative temperature system number is a depletion type of an n-type gate and an n-type channel first field effect transistor (M1) in which the gate and the source are connected and p A voltage source circuit having a positive temperature system number is composed of a series connection configuration of n-type channel second and third field effect transistors (M2, M3) in which the gate and the drain are connected in the enhancement type of the type gate. A fourth field effect transistor (M4) having an n-type channel having an n-type concentration gate and a depletion type having a n-type gate having a low concentration n-type gate and having a GND potential at the gate and the source (M5). ) And a high-concentration n-type in which a gate potential is applied by a voltage at a connection point between the fourth field-effect transistor and the fifth field-effect transistor. A sixth n-channel field effect transistor (M6) of the gate and a depletion type n-type gate having a low concentration n-type gate and a seventh n-type channel field effect transistor (M7) having the gate and the source at the GND potential are connected in series. The connection configuration is such that the connection point between the sixth field effect transistor (M6) and the seventh field effect transistor (M7) is a reference voltage output point (see FIG. 27).

  According to a twenty-sixth aspect of the present invention, in the configuration of the twelfth aspect, the field effect transistor constituting the voltage source circuit having a positive temperature coefficient and the voltage source circuit having a negative temperature coefficient has at least a part of conductivity type or impurity. It is characterized by having gates with different concentrations and not using channel dope (see FIG. 28).

  The reference voltage source circuit of the present invention according to claim 27, wherein the voltage source circuit having a negative temperature system number is an enhancement type of an n-type gate and an n-type channel first electric field in which the gate and the source are connected. An effect transistor (M1) and a p-type gate enhancement type n-channel second field effect transistor (M2) connected in the gate and drain are connected in series, and a voltage source circuit having a positive temperature system number is provided. The third n-channel third field effect transistor (M3) of the high-concentration n-type gate and the n-channel fourth field-effect transistor (enhancement type of the low-concentration n-type gate and the gate and source GND potentials) M4) in series connection configuration, and the gate potential depends on the voltage at the connection point of the third field effect transistor (M3) and the fourth field effect transistor (M4). A high-concentration n-type gate n-channel fifth field effect transistor (M5) and a low-concentration n-type gate enhancement type n-channel sixth field effect with the gate and source at the GND potential The transistor (M6) is connected in series, and the connection point between the fifth field effect transistor (M5) and the sixth field effect transistor (M6) is a reference voltage output point (see FIG. 28). .

  In the present invention, the drain currents of at least some of the field effect transistors are made equal. As a result, VPTAT and VPN are obtained as described below.

  Each gate may be made of single crystal silicon. As a result, VPTAT determined only by the impurity concentration of the gate is obtained as will be described later.

  Alternatively, each gate is made of polycrystalline silicon, and approximately 98% or more of dangling bonds of the polycrystalline silicon are terminated. As a result, VPTAT determined only by the impurity concentration of the gate is obtained as in the case of single crystal silicon.

Alternatively, each gate is made of polycrystalline Si _X Ge _1-X , and the composition ratio of Si _X Ge _1-X is approximately
0.01 <X <0.5
Be in the range. Also in this case, VPTAT determined only by the impurity concentration of the gate is obtained as in the case of single crystal silicon.

  According to the present invention, it is possible to realize a voltage generation circuit using a field effect transistor that can stably operate even at a high temperature of 80 ° C. or higher and can be used even with strong inversion. More specifically, in the inventions described in claims 1 to 5, voltage generation having various circuit configurations using field effect transistors that operate stably even at a high temperature of 80 ° C. or higher and can be used not only for weak inversion but also for strong inversion. In the inventions described in claims 6 to 8, a voltage generation circuit capable of adjusting the impurity concentration by resistance can be realized. In the invention described in claim 9, the resistance value is adjusted after creation. Thus, the concentration can be adjusted, and in the invention according to the tenth aspect, the voltage generation circuit can be configured by field effect transistors of different conductivity types.

  Further, according to the present invention, a voltage source circuit having a desired temperature characteristic can be realized without using a minute current bias circuit or a current bias circuit for correcting the temperature characteristic of the conduction coefficient. In particular, since various circuit configurations as described in claims 12 to 27 can be adopted, the applicable range can be greatly expanded.

  First, the outline of the present invention will be described.

  The present invention realizes a Proportional-To-Absolute-Temperature (PTAT) voltage source in a CMOS process using a field effect transistor that can be used even in strong inversion.

  As a PTAT circuit using a MOS transistor, a circuit using a weak inversion region is known. However, a bias circuit for passing a minute current of 2 nA or less for maintaining the weak inversion region is required, and a characteristic shift due to a leakage current occurs due to the influence of the parasitic diode. Therefore, the present invention proposes a PTAT circuit using a pair MOS transistor that has gates with different Fermi levels and can be used even in strong inversion.

The difference in threshold voltage (Vt) between the pair transistors M1 and M2 having a low concentration (Ng1) n-type gate and a high concentration (Ng2) n-type gate is VPTAT = kt / qln when the carrier concentration is equal to the impurity concentration. (Ng2 / Ng1), which is a voltage source proportional to absolute temperature. For example, the low resistance gate (20Ω / sq; phosphorus concentration about 1 × e ²⁰ / cm ³ ) and the high resistance gate (10KΩ / sq; phosphorus concentration about 2 × e ¹⁶ / cm ³ ) used in the analog CMOS process are PTAT. By using it in a circuit, a PTAT voltage source with VPTAT = 0.221V (room temperature) can be realized.

  Before describing the embodiments of the present invention, first, the principle of the present invention will be described. The present invention proposes a PTAT using a field effect transistor (explained as a MOS transistor in the following embodiment) that can be used in a strong inversion region instead of a weak inversion region that cannot stably operate due to leakage at 80 degrees or more. A voltage generation circuit is realized by using it.

According to the description on page 46 of Ong (ed.) "Modern MOS Technology" McGrawHill 1987 (reference document F), the threshold voltage Vt for strongly inverting the MOS transistor is:
Vt = Φms−Qf / Cox + 2φf−Qb / Cox
It is represented by Where φMS is the difference between the work function φm of the gate and the work function φs of the substrate, Qf is the fixed charge in the oxide film, φf is the Fermi level of the substrate, Qb is the charge in the depletion layer between the inversion layer and the substrate, and Cox is This is the capacitance per unit area of the oxide film.

FIG. 4 is a band diagram of a MOS transistor. further,
φm = φS0 + Eg / 2 ± φf
The sign of the third term φf of φm is positive if the gate is p-type and negative if it is n-type. The difference between the threshold voltages Vt of pair transistors having the same conductivity type and having low concentration (Ng1) and high concentration (Ng2) gates is equal to the difference in work function φm of the gate material. Therefore, when the carrier concentration is equal to the impurity concentration, the following formula (2) is established.

Vt1-Vt2 = φm (Ng1) -φm (Ng2)
= [Eg1 / 2-φ _f (Ng1)]-[Eg1 / 2-φ _f (Ng2)]
= φ _f (Ng2) -φ _f (Ng1)
= -kT / q ln (Ng1 / Ni) + kT / q ln (Ng2 / Ni)
= kT / q ln (Ng2 / Ng1) (2)
Here, k is the Boltzmann constant, q is the charge amount of electrons, T is the absolute temperature, Eg is the band gap of silicon, and Ni is the carrier concentration of the intrinsic semiconductor. Therefore,
VPTAT = (kT / q) ln (Ng2 / Ng1)
Thus, VPTAT determined only by the gate impurity concentration ratio is obtained. For example, as shown in FIG. 5, when a high concentration n + gate having a phosphorus concentration of about 1 × e ²⁰ / cm ^{3 and} a low concentration n + gate having a phosphorus concentration of about 2 × e ¹⁶ / cm ³ are used, VPTAT = 0.221V (room temperature ) Is obtained. Due to process variations, the phosphorus concentration of the high-concentration n + gate is reduced by 10% to about 9 × e ¹⁹ / cm ³ , and the phosphorus concentration of the low-concentration n + gate is increased by 10% to about 2.2 × e ¹⁶ / cm ³ In this case, VPTAT = 0.216V (room temperature) is obtained, and conversely, the phosphorus concentration of the high concentration n + gate is increased by 10%, and the phosphorus concentration of the low concentration n + gate is about 1.1 × e ²⁰ / cm ³ . When it is 10% lower and about 1.8 × e ¹⁶ / cm ³ , VPTAT = 0.227 V (room temperature) is obtained. Thus, even if the phosphorus concentrations Ng1 and Ng2 of the gates of the pair transistors fluctuate by 10% due to process variations, the variation of VPTAT is about several mV.

  As a method of creating such a gate having a different phosphorus concentration, after depositing a non-doped gate, a portion to be a low concentration gate is masked with an oxide film, and then a portion not masked by the phosphorus deposit is heavily doped. The low concentration portion may be doped with phosphorus by ion implantation after etching the mask oxide film. Thus, a pair transistor having gates having the same conductivity type and different Fermi levels φf can be produced. Since the gate is formed in the same process except for doping to the gate, it has the same insulating film thickness, channel doping, channel length and channel width, only the impurity concentration is different, and the difference in threshold voltage Vt is the difference in gate Fermi level φf. It becomes.

  Next, a method for extracting the difference of the Fermi level φf will be described.

The drain current Id of the MOS transistor in the saturation region (VDS> VGS−Vt) is
Id = (β / 2) (VGS−Vt) ²
It is represented by

Therefore, the drain currents Id1 and Id2 of the pair MOS transistors M1 and M2 having different gate concentrations are
Id1 = (β1 / 2) (VGS1-VT1) ²
Id2 = (β2 / 2) (VGS2-VT2) ²
It is.

Here, VGS1 and VGS1, VT1 and VT2 are the gate-source voltage and threshold voltage of the MOS transistors M1 and M2, respectively. Β1 and β2 are the conductivity coefficients of the MOS transistors M1 and M2, respectively.
β = μ (εOX / TOX) (Weff / Leff)
It is expressed in the form of Here, μ is carrier mobility, ε OX is dielectric constant of oxide film, T OX is oxide film thickness, W eff is effective channel width, L eff is effective channel length.

The pair MOS transistor has the same carrier mobility μ, oxide dielectric constant ε OX, oxide film thickness T OX, effective channel width W eff, and effective channel length L eff, so β 1 = β 2 and I d 1 = Id 2 ( The term of β / 2) dropped,
(VGS1-VT1) ² = (VGS2-VT2) ²
It becomes. VGS is appropriately biased to take out the difference in threshold voltage Vt, that is, the difference in φf.

  As described above, the principle of the PTAT voltage source has been described by taking the case where the carrier concentration n is equal to the impurity concentration Ng as an example. However, in reality, they often do not always match. Such a case will be described below.

First, the case where the gate is a single crystal will be described. In that case, the carrier concentration is
n = A × Ng
It is expressed. Here, A is an activation rate and is a constant of 1 or less. Since A is not affected by absolute temperature, the above formula (2) is
Vt1-Vt2 = kT / q ln (A ₂ × Ng2) / (A ₁ × Ng1)
Thus, VPTAT determined only by the concentration ratio of the impurity concentration of the gate is obtained.

Next, the case where the gate is polycrystalline silicon (polysilicon) will be described. In this case, the carrier concentration n is n = A × Ng−B
It is expressed. Here, A is the activation rate, and B is a value proportional to the reciprocal of the absolute temperature, such as B∝ (1 / T). Therefore, Equation (2) is
Vt1-Vt2 = kT / q ln (A ₂ × Ng2-B ₂ ) / (A ₁ × Ng1-B ₁ )
Thus, VPTAT determined only by the impurity concentration ratio of the gate cannot be obtained.

The value of B depends on the amount of dangling bonds. Therefore, in order to obtain VPTAT using polysilicon, it is necessary to terminate the dangling bonds with hydrogen or the like so that the value of Vt1-Vt2 is not affected by the amount of dangling bonds. By doing so, the terms B ₁ and B ₂ in the above formula are effectively made small enough to be ignored. As a result, VPTAT is obtained.

  Specifically, 98% or more of dangling bonds must be terminated with hydrogen or fluorine. The solid line shown in FIG. 29 indicates the case where termination with hydrogen or the like is not performed, and the broken line indicates the case where 98% or more of dangling bonds are terminated. In the broken line, since there is no sharp change due to the impurity concentration, it can be seen that there is almost no dangling bond.

Here, supplementing dangling bonds, the amount of dangling bonds can be measured by ESR (Electron Spin Resonance). Normally, dangling bonds are terminated to about 96% by injecting high-concentration impurities and processing at a high temperature (2 × e ¹⁹ / cm ³ , 1000 ° C.) without performing forced termination with hydrogen or the like. Temperature characteristics are almost lost. However, even at the same concentration, the treatment at 900 ° C. only terminates 93%, and has a large temperature characteristic coefficient.

  Therefore, by pre-terminating 98% or more with hydrogen or the like, a good polysilicon having almost no temperature characteristics can be obtained.

Next, an example in which the gate is polycrystalline Si _X Ge _1-X will be described. Unlike the case of polysilicon, polycrystalline Si _X Ge _1-X has a very high impurity activation rate, and is therefore less affected by dangling bonds. Therefore, the carrier concentration n is n = A × Ng
VPTAT is obtained as in the case of a single crystal.

In this case, if the Ge content is increased, the band gap is reduced, which is disadvantageous for obtaining a large VPTAT. In order to obtain a desirable VPTA> 0.2 (V) in consideration of process variations, the range of the composition ratio of Si _X Ge _1-X is:
0.01 <X <0.5
It is desirable to be in.

In each of the embodiments described below, it is described that the gate is made of polysilicon. However, the present invention is not limited to such a configuration, and as described above, single-crystal silicon may be used. It is assumed that 98% or more of the ring bonds are terminated with hydrogen or the like, or in the case of polycrystalline Si _X Ge _1-X , the composition ratio is in the range of 0.01 <X <0.5. And

  Hereinafter, as a specific example of a voltage generation circuit using a PTAT according to the present invention with reference to the drawings, an example of a specific circuit configuration for extracting a difference in threshold voltage Vt of a pair MOS transistor, that is, a difference in φf will be described. explain. In the figure, the gate of the MOS transistor M1 surrounded by a triangle is low-concentration (Ng1) n-type polysilicon. The MOS transistor M2 is a MOS transistor having a high concentration (Ng2) n-type polysilicon gate. In the following circuit configuration examples, the MOS transistors M1 and M2 are MOS transistors having the same insulating film thickness, channel dope, channel length, channel width, and different impurity concentrations.

  First, an example of a circuit configuration using paired MOS transistors with gate connections will be described. In this case, VPTAT is taken out as a difference between the source voltages of the pair MOS transistors.

  First, a circuit configuration example in which MOS transistors M1 and M2 are connected in parallel will be described.

  FIG. 6 is a diagram showing a basic diagram of this circuit configuration example (first embodiment). As shown in the figure, this circuit includes a MOS transistor M1 having a low-concentration (Ng1) n-type polysilicon gate and a high-concentration (Ng2) n between two power supplies, that is, between the power supplies VCC and GND. The MOS transistor M2 having a polysilicon gate is commonly connected to the gate, and the drain and gate of the MOS transistor M1 having a low-concentration (Ng1) n-type polysilicon at the gate are connected to each other. The drain-source current is made equal (I1 = I2).

With this configuration, the source potential of the MOS transistor M2 having a high concentration (Ng2) n-type polysilicon gate (that is, the MOS transistor M1 having a low concentration (Ng1) n-type polysilicon at the gate and the high concentration (Ng2) difference in source potential of the MOS transistor M2 having a n-type polysilicon gate) is extracted as _{VPTAT = U T ln (Ng2 /} Ng1).

  Next, a circuit configuration example in which MOS transistors M1 and M2 are connected in series will be described. FIG. 7 is a diagram showing a basic diagram of this circuit configuration example (second embodiment). As shown in the figure, this circuit includes a MOS transistor M1 having a low-concentration (Ng1) n-type polysilicon gate and a high-concentration (Ng2) n between two power supplies, that is, between the power supplies VCC and GND. The MOS transistors M2 having the type polysilicon are connected in series, and the gates are commonly connected to the drain of the MOS transistor M2.

With this configuration, since the source potential of the MOS transistor M2 (that is, the source potential of the MOS transistor M1 is GND), the source potential of the MOS transistor M2 is the MOS transistor M1 having n-type polysilicon having a low concentration (Ng1) as a gate. U _T ln (Ng2 / Ng1), which is the difference in Fermi level, is obtained as the output VPTAT from the above and the source potential difference of the MOS transistor M2 having a high concentration (Ng2) n-type polysilicon at the gate.

  Next, a circuit configuration example using a source-connected pair MOS transistor will be described. In this case, VPTAT is taken out as a difference between the gate voltages of the pair MOS transistors.

  FIG. 8 is a diagram showing a basic diagram of this circuit configuration example (third embodiment). As shown in the figure, this circuit includes a MOS transistor M1, which is provided between two power supplies, that is, between the power supplies VCC and GND, and has a low concentration (Ng1) n-type polysilicon at its gate. ) Of the n-type polysilicon gate, the p-type channel MOS transistors M3 and M4, and the n-type channel MOS transistor M5. The sources of the MOS transistor M1 having a low concentration (Ng1) n-type polysilicon gate and the MOS transistor M2 having a high concentration (Ng2) n-type polysilicon gate are connected in common.

  Specifically, p-type channel MOS transistors M3 and M4 constitute a current mirror circuit, and p-type channel MOS transistor M3 and n-type channel MOS transistor M2 having a high concentration (Ng2) n-type polysilicon gate are connected in series. At the same time, the gate and source of the n-type channel MOS transistor M2 are connected (constant current connection), and the p-type channel MOS transistor M4 and the n-type channel MOS transistor M1 having a low concentration (Ng1) n-type polysilicon gate are provided. Connected in series. Due to the current mirror function of the p-type channel MOS transistors M3 and M4, the same current as the depletion MOS transistor M1 connected to the constant current flows through the high-concentration (Ng2) n-type channel MOS transistor M2.

Further, an n-type channel MOS transistor M5 having a drain connected to the power supply VCC, a gate connected to the drain of the n-type channel MOS transistor M1, and a source connected to the gate of the n-type channel MOS transistor M1 is provided. The source follower n-type channel MOS transistor M5 biases the gate of the n-type channel MOS transistor M1 so that Id _M1 = Id _M2 . With this configuration, the gate potential of n-type channel MOS transistor M1 (the source potential of n-type channel MOS transistor M5) becomes VPTAT. This VPTAT is equal to the Fermi level difference U _T ln (Ng2 / Ng1).

Further, as a modification of the circuit configuration of FIG. 8, a circuit configuration as shown in FIG. 9 is also possible (a first modification of the third embodiment). The circuit configuration shown in FIG. 9 comprises a resistor R between the gate of the MOS transistor M1 having the low concentration (Ng1) n-type polysilicon of FIG. 8 at its gate and the power supply GND as resistors R1 and R2. Take the output voltage VPTAT from the connection point. At this time, the output voltage VPTAT = (R2 / (R1 + R2)) U _T ln (Ng2 / Ng1).

Further, as a modification of the circuit configuration of FIG. 8, a circuit configuration as shown in FIG. 10 is also possible (second modification of the third embodiment). The circuit configuration shown in FIG. 10 has a resistance R between the gate of the MOS transistor M1 having the gate of the low concentration (Ng1) n-type polysilicon of FIG. 8 and the power supply GND as R2, and the gate of the MOS transistor M1. A resistor R1 is inserted between the source of the n-type channel MOS transistor M5, and the output voltage VPTAT is taken out from the source of the n-type channel MOS transistor M5. The output voltage VPTAT at this time is ((R1 + R2) / R2) U _T ln (Ng2 / Ng1).

Further, as a modification of the circuit configuration of FIG. 8, a circuit configuration as shown in FIG. 11 is also possible (third modification of the third embodiment). The circuit configuration shown in FIG. 11 includes p-type channel MOS transistors M6 and M7 in a current path that flows through the resistance R between the gate and source of the MOS transistor M1 having the low-concentration (Ng1) n-type polysilicon of FIG. The output current VPTAT is extracted from the source of the p-type channel MOS transistor M7. At this time, the output voltage VPTAT = MU _T ln (Ng2 / Ng1). Here, “M” in the equation is the ratio of the current mirror function.

As shown in FIG. 9, 10, 11 described above, by adding deformation to the circuit of FIG. 8, the output voltage U _T ln (Ng2 / Ng1) to a resistance ratio or current ratio (ratio of the current mirror function of FIG. 8 ) Can be obtained, and the concentration ratio (Ng2 / Ng1), which is a process factor, can be arbitrarily corrected by changing these resistance ratio and current ratio. In order to obtain process-independent VPTAT, the resistance values R1 and R2 may be adjusted to correct the concentration ratio as a process factor. For this purpose, trimming means (resistance value adjusting means) for selectively irradiating the resistor portion with laser light and performing trimming after the diffusion and film formation steps can be used.

  FIG. 30 shows an example of this trimming means. In the figure, a desired resistance value (a multiple of the resistance value r) can be obtained by burning out any portion marked with x with a laser beam with respect to the series circuit of the resistance element r. By using such means, it is possible to adjust the resistance values of the resistors R1 and R2.

  Next, a circuit configuration example (fourth embodiment) using a MOS transistor M1 that supplies the same current as the depletion transistor M2 connected with constant current will be described. The output VPTAT in this case is the gate-source voltage VGS of the MOS transistor M1.

  FIG. 12A is a diagram showing a basic diagram of this circuit configuration example (fourth embodiment). As shown in the figure, this circuit includes a depletion type MOS transistor M2 having a high concentration (Ng2) n-type polysilicon gate and a low concentration (Ng1) between two power supplies, that is, between the power supplies VCC and GND. A depletion type MOS transistor M1 having n-type polysilicon at its gate is connected in series, and the gate and source of the depletion type MOS transistor M2 are connected (constant current connection: VGS2 = 0).

  Further, an n-type channel MOS transistor M3 is provided in which a gate is connected to the connection portion between the gate and source of the depletion type MOS transistor M2, a drain is connected to the power source VCC, and a gate is connected to the gate of the depletion type MOS transistor M1.

In this configuration, the voltage of the gate of the depletion type MOS transistor M1 (source of the n-type channel MOS transistor M3) is VPTAT. At this time, VPTAT is equal to the gate-source voltage VGS1 of the depletion type MOS transistor M1, and becomes the Fermi level difference U _T ln (Ng2 / Ng1). Note that the circuit configuration example in FIG. 12A shows a case where the MOS transistor M1 is configured as a depression type, but the MOS transistor M1 may be an enhancement type.

Further, as a modified example of the circuit configuration of FIG. 12A, a circuit configuration as shown in FIG. 13A is also possible (first modified example of the fourth embodiment). In the circuit configuration shown in FIG. 13A, the resistance R between the gate of the MOS transistor M1 having the gate of the low concentration (Ng1) n-type polysilicon of FIG. The output voltage VPTAT is taken out from the connection point. The output voltage VPTAT at this time is (R2 / (R1 + R2)) U _T ln (Ng2 / Ng1).

Further, as a modified example of the circuit configuration of FIG. 12A, a circuit configuration as shown in FIG. 14A is also possible (second modified example of the fourth embodiment). In the circuit configuration shown in FIG. 14A, the resistance between the gate of the MOS transistor M1 having the n-type polysilicon of low concentration (Ng1) in FIG. A resistor R1 is inserted between the gate of the transistor M1 and the source of the n-type channel MOS transistor M3, and the output voltage VPTAT is taken out from the source of the n-type channel MOS transistor M3. The output voltage VPTAT at this time is ((R1 + R2) / R2) U _T ln (Ng2 / Ng1).

Further, as a modified example of the circuit configuration of FIG. 12A, a circuit configuration as shown in FIG. 15 is also possible (third modified example of the fourth embodiment). The circuit configuration shown in FIG. 15 has a p-type channel MOS transistor M6 in the current path flowing through the resistance R between the gate and source of the MOS transistor M1 having the low concentration (Ng1) n-type polysilicon of FIG. , M7, and an output voltage VPTAT is taken out from the source of the p-type channel MOS transistor M7. At this time, the output voltage VPTAT = MU _T ln (Ng2 / Ng1). Here, “M” in the equation is the ratio of the current mirror function.

As shown in FIGS. 13 (A), 14 (A), and 15 described above, the output voltage U _T ln (Ng2 / Ng1) in FIG. 12 (A) is obtained by modifying the circuit in FIG. 12 (A). It is possible to obtain an output voltage that is multiplied by the resistance ratio or current ratio (current mirror function ratio M), and change the resistance ratio and current ratio to the concentration ratio (Ng2 / Ng1), which is the process factor. Can be arbitrarily corrected. In order to obtain process-independent VPTAT, the resistance values R1 and R2 may be adjusted to correct the concentration ratio as a process factor. Therefore, as described above (see FIG. 30), trimming means (resistance value adjusting means) for selectively irradiating the resistor portion with laser light and performing trimming after the diffusion and film forming steps can be used.

  Next, a gate voltage different by the difference in Fermi level is applied to the MOS transistor M1 having a low-concentration (Ng1) n-type polysilicon gate and the MOS transistor M2 having a high-concentration (Ng2) n-type polysilicon gate. A circuit configuration example (fifth embodiment) for equalizing conductance will be described.

  FIG. 16 is a diagram showing a basic diagram of this circuit configuration example (fifth embodiment). As shown in the figure, this circuit includes a MOS transistor M1 having a source-coupled low-concentration (Ng1) n-type polysilicon at the gate between two power supplies, that is, between the power supplies VCC and GND. Ng2) MOS transistor M2 having an n-type polysilicon gate is provided in parallel, the potentials of the drains of MOS transistor M1 and MOS transistor M2 are input to differential amplifier A1, and the output of differential amplifier A1 is routed through resistor R2. Feedback to the gate of the MOS transistor M2, and a resistor R1 is provided between the power supply VCC and the gate of the MOS transistor M2.

In this configuration, the voltage VCC is applied to the gate of the MOS transistor M1, and a voltage lower than VCC is applied to the gate of the MOS transistor M2 by the amount of the voltage drop caused by the resistor R1, so that the gate conductance becomes equal. Voltage applied to the gate of the MOS transistor _{M2, VPTAT = U T ln (Ng2} / Ng1) next, based on the VCC Further, the output of the differential amplifier A1, VOUT based on the VCC = (R2 / R1) U _T ln (Ng2 / Ng1) (see FIG. 16).

  Each of the above-described embodiments is an example in which n-type channel MOS transistors are used as the MOS transistors M1 and M2, but a similar circuit can be realized by using p-type channel MOS transistors. In that case, the channel type (n-type channel / p-type channel) of each MOS transistor used in each of the above embodiments may be reversed, and the power supply voltage may be reversed between the high voltage side and the low voltage side. (See FIGS. 12B, 13B, and 14B).

  Next, a reference voltage source realized by using the technique of the “voltage generation circuit using a field effect transistor” will be described.

  As a reference voltage source using a conventional MOS, one using a difference in threshold voltage between a depletion transistor and an enhancement transistor produced by changing the concentration of a substrate or channel dope is known. However, transistors with different substrate and channel dope concentrations have different conductivity coefficients and their temperature characteristics, and it is difficult to realize a reference voltage source having desired temperature characteristics.

  Therefore, in the present invention, the VPTAT voltage source having a positive temperature coefficient by a pair MOS transistor having semiconductor gates having the same conductivity type and different impurity concentrations, the substrate and the channel dope concentration being equal between each pair, and different conductivity types A desired reference voltage VREF = VPN + VPTAT is generated by combining a VPN voltage source having a negative temperature coefficient by a pair MOS transistor having a semiconductor gate of the above.

  According to the present invention, the PTAT voltage source uses a field effect transistor that can be used in the co-inversion region instead of the weak inversion region that cannot stably operate due to leakage at 80 ° C. or higher (in the following embodiments, an example of a MOS transistor) A reference voltage source is realized.

As described above, β1 = β2 and Id1 = Id2 in a pair MOS transistor having the same carrier mobility μ, dielectric constant εOX of oxide film, oxide film thickness TOX, effective channel width Weff, and effective channel length Leff, (VGS1-VT1) ² = (VGS2-VT2) ² . Therefore, VGS can be appropriately biased to extract the difference in threshold voltage Vt, that is, the difference in Fermi level φf.

As described above, the difference in threshold voltage of paired MOS transistors having gates of the same conductivity type and different impurity concentrations is the difference in Fermi level of the gate material,
VPTAT = (kT / q) ln (Ng2 / Ni)-(kT / q) ln (Ng1 / Ni) = (kT / q) ln (Ng2 / Ng1)
Where k is the Boltzmann constant, T is the absolute temperature, q is the electron charge, Ni is the number of carriers in the intrinsic semiconductor, Ng2 is the impurity concentration in the high-concentration gate, and Ng1 is the impurity concentration in the low-concentration gate. A voltage source VPTAT having a positive temperature coefficient can be produced by taking out the difference between the threshold voltages of the transistors.

Similarly, the difference in threshold voltage of a pair transistor having gates of different conductivity types and different impurity concentrations is the sum of Fermi levels of the gate material,
VPN = (kT / q) ln (Ng2 / Ni) + (kT / q) ln (Pg2 / Ni) = (kT / q) ln (Ng2 * Pg2 / Ni ² )
By extracting the difference between the threshold voltages of the pair transistors, a voltage source VPN having a negative temperature coefficient can be created.

  As described in Reference D, the VPN of a pair MOS transistor having the same shape and channel dope and having a polysilicon gate of a high concentration p-type and a high concentration n-type has a silicon bandgap voltage Δ VG (1.2 V at T = 0, 1.12 V at T = room temperature), and is given by the difference between the threshold voltages of these pair transistors. The shift between the drain current and the gate-source potential difference curve also holds in the weak inversion and transition region below the threshold.

  The present invention realizes a reference voltage source circuit having desired temperature characteristics by a simple circuit combining the voltage source VPTAT having a positive temperature coefficient and the voltage source VPN having a negative temperature coefficient as described above. .

  Hereinafter, various circuit configuration examples of the reference voltage source circuit according to the present invention will be described with reference to the drawings. FIG. 17 is a diagram showing the relationship between the gate impurity, the concentration, and the threshold voltage. In FIG. 17, NH is a high-concentration n-type gate (Ng2), NL is a low-concentration n-type gate (Ng1), PH is a high-concentration p-type gate (Pg2), and PL is a low-concentration p-type gate (Pg1). ).

  In the circuit diagrams used to describe the embodiments below, a circled transistor has a field effect transistor having a high-concentration p-type gate, and a square-shaped transistor in the drawing has a low-concentration p-type gate. Each field effect transistor surrounded by a triangle in the figure indicates a field effect transistor having a low-concentration n-type gate.

  FIG. 18 is a diagram for explaining a sixth embodiment of the present invention. In the figure, all of the field effect transistors M1, M2, and M3 are n-type channels, and the impurity concentrations of the substrate and the channel dope are equal, and are formed in the p-well of the n-type substrate. It is equal to the potential. The ratio S = W / L of channel width W and channel length L are all equal. That is, Sm1 = Sm2 = Sm3. However, Smi represents the ratio S between the channel width W and the channel length L of the field effect transistor Mi (the same applies hereinafter).

  The field effect transistor M1 is a depletion type of a high-concentration n-type gate, and serves as a constant current source by connecting the gate and the source. The field effect transistor M2 has a low-concentration n-type gate, and a gate potential is applied by a source follower circuit including an n-type channel field effect transistor M4 and a resistor R1. The field effect transistor M3 is a p-type gate enhancement type, and the gate and the drain are connected.

  Since the same current flows through the pair field effect transistors M1 and M3, the gate-source voltage of the field effect transistor M3, that is, V2 is VPN. The pair field effect transistors M1 and M2 are biased by the source follower circuit so that the same current flows, and the gate-source voltage of the field effect transistor M2 becomes VPTAT.

Therefore, the gate potential V3 of the field effect transistor M2 is
V3 = VPN + VPTAT (= Vref: reference voltage)
It becomes. Desired temperature characteristics can be arbitrarily set by changing the impurity concentration of the high-concentration n-type gate, the low-concentration n-type gate, and the p-type gate.

  FIG. 19 is a view for explaining a seventh embodiment of the present invention. In the figure, the field effect transistors M1, M2, and M3 are all p-type channels, the substrate and channel dope impurity concentrations are equal, and are formed in the n-well of the p-type substrate, and the substrate potential of each field effect transistor is the source. It is equal to the potential. The ratio S = W / L of channel width W and channel length L are all equal. That is, Sm1 = Sm2 = Sm3.

  The field effect transistor M1 is an enhancement type of a high-concentration n-type gate, and the gate and the drain are connected. The field effect transistor M2 has a low-concentration p-type gate, and a gate potential is applied by a source follower circuit including a p-type channel field-effect transistor M4 and a resistor R1 (when the resistor R2 in the figure is short-circuited). The field effect transistor M3 is a depletion type of a p-type gate, and connects the gate and the source to become a constant current source.

  Since the same current flows through the pair field effect transistors M1 and M3, the gate-source voltage of the field effect transistor M1, that is, (VCC-V1) is VPN. The pair field effect transistors M1 and M2 are biased by the source follower circuit so that the same current flows, and the gate-source voltage of the field effect transistor M2, that is, (V1-V3) becomes VPTAT.

Therefore, the difference (VCC−V3) between the power supply voltage VCC and the gate potential V3 of the field effect transistor M2 is
VCC-V3 = VPN + VPTAT (= Vref1: reference voltage 1)
It becomes.

Desired temperature characteristics can be arbitrarily set by changing the impurity concentration of the high-concentration n-type gate, the low-concentration n-type gate, and the p-type gate. Further, when a resistor R2 is inserted into the source follower circuit at the position shown in FIG.
V4 = (VPN + VPTAT) * R2 / R1 (= Vref2: Reference voltage 2)
Thus, a GND-based reference voltage source that can set the set voltage by the resistance ratio can be realized.

  FIG. 20 is a view for explaining an eighth embodiment of the present invention. In the figure, the field effect transistors M1, M2, M3, and M4 are all n-type channels, the substrate and the channel doping impurity concentration are equal, and are formed in the p-well of the n-type substrate. Is equal to the source potential. The ratio S = W / L between the channel width W and the channel length L is Sm1 = Sm2 and Sm3 = Sm4.

  The field effect transistor M1 is a depletion type of a high-concentration n-type gate, and serves as a constant current source by connecting the gate and the source. The field effect transistor M2 has a high-concentration p-type gate, and a gate potential is applied by a source follower circuit including an n-type channel field effect transistor M5 and resistors R1 and R2. The field effect transistor M3 is a high-concentration n-type gate field effect transistor, and the field-effect transistor M4 is a low-concentration n-type gate field effect transistor.

Since the same current flows through the pair field effect transistors M1 and M2, the gate-source voltage V2 of the field effect transistor M2 is VPN. The pair field effect transistors M3 and M4 are input transistors of the differential amplifier, and the same current flows through the current mirror circuit of the p-type channel MOS transistors M6 and M7. Therefore, this differential amplifier has an input offset of VPTAT. VPN * R2 / (R1 + R2) is applied to the gate of the field effect transistor M3 by a source follower circuit, and a feedback loop comprising a differential amplifier having a VPTAT offset, a p-type channel field effect transistor M8, and resistors R3 and R4. Thus, the gate potential V4 of the field effect transistor M4 is
VPN * R2 / (R1 + R2) + VPTAT
It becomes.

Therefore, as the drain potential V5 of the field effect transistor M8,
V5 = (VPN * R2 / (R1 + R2) + VPTAT) * (R3 + R4) / R4 (= Vref: reference voltage)
Get.

  Desired temperature characteristics can be arbitrarily set by changing the impurity concentration of the high-concentration n-type gate, the low-concentration n-type gate, the p-type gate, or the resistances R1 and R2. Further, it is possible to realize a reference voltage source capable of setting the set voltage by the resistance ratio by the resistors R3 and R4. In addition, the current drive capability can be increased by the field effect transistor M8.

  FIG. 21 is a view for explaining a ninth embodiment of the present invention. In the figure, the field effect transistors M1 and M2 are p-type channels, and the impurity concentrations of the substrate and channel dope are equal, and are formed in the n-well of the p-type substrate. The substrate potential of each field effect transistor is equal to the source potential. It is. The field effect transistors M3 and M4 are n-type channels, and the impurity concentrations of the substrate and the channel dope are equal and are formed in the p-well of the p-type substrate. The substrate potential of each field effect transistor is the GND potential unlike the source potential. . The ratio S = W / L between the channel width W and the channel length L is Sm1 = Sm2 and Sm3 = Sm4.

  The field effect transistor M2 is a depletion type of a high-concentration p-type gate and serves as a constant current source by connecting the gate and the source. The field effect transistor M1 has a high-concentration n-type gate, and a gate potential is applied by a source follower circuit composed of a p-type channel field effect transistor M5 and resistors R1 and R2. The field effect transistor M3 is a high-concentration n-type gate field effect transistor, and the field-effect transistor M4 is a low-concentration n-type gate field effect transistor.

Since the same current flows through the pair field effect transistors M1 and M2, the gate-source voltage of the field effect transistor M1 is VPN. The pair field effect transistors M3 and M4 are input transistors of the differential amplifier, and the same current flows through the current mirror circuit of the p-type channel MOS transistors M6 and M7. Therefore, this differential amplifier has an input offset of VPTAT. The gate of the field effect transistor M3 is applied with V3 = VPN * R2 / (R1 + R2) by a source follower circuit, and comprises a differential amplifier having an offset of VPTAT, a p-type channel field effect transistor M8, and resistors R3 and R4. Due to the feedback loop, the gate potential V4 of the field effect transistor M4 is
V4 = VPN * R2 / (R1 + R2) + VPTAT (= Vref1: reference voltage 1)
It becomes.

Therefore, as the drain potential V5 of the field effect transistor M8,
V5 = (VPN * R2 / (R1 + R2) + VPTAT) * (R3 + R4) / R4 (= Vref2: Reference voltage 2)
Get.

  Desired temperature characteristics can be arbitrarily set by changing the impurity concentration or resistances R1 and R2 of the high-concentration n-type gate, the low-concentration n-type gate, and the p-type gate. Further, a reference voltage source capable of setting the set voltage by the resistance ratio is formed by the resistors R3 and R4. In addition, the current driving capability can be increased by the field effect transistor M8. In this way, even pair transistors with different source potentials and substrate potentials that are subject to back bias can be used as VPN and VPTAT voltage sources if the back bias voltage is made equal.

  FIG. 22 is a view for explaining a tenth embodiment of the present invention. In the figure, the field effect transistors M1, M2, M3, and M4 are all n-type channels, have the same substrate and channel-doped impurity concentrations, are formed in the p-well of the n-type substrate, and the substrate potential of each field-effect transistor is It is equal to the source potential. The ratio S = W / L between the channel width W and the channel length L is Sm1 = Sm2 and Sm3 = Sm4.

  The field effect transistor M1 is a depletion type of a high-concentration n-type gate, and serves as a constant current source by connecting the gate and the source. The field effect transistor M2 has a high-concentration p-type gate, and a gate potential is applied by a source follower circuit including an n-type channel field effect transistor M5 and a resistor R2 (when the resistor R1 is short-circuited in the figure). The field effect transistor M3 is a depletion type with a high-concentration n-type gate, and the field effect transistor M4 is a depletion type with a low-concentration n-type gate. The gate and source are connected to form a constant current source.

  Since the same current flows through the pair field effect transistors M1 and M2, the gate-source voltage of the field effect transistor M2 is VPN. Further, since the same current flows through the pair field effect transistors M3 and M4, the gate-source voltage of the field effect transistor M3 is −VPTAT.

Therefore, the source potential V3 of the field effect transistor M3 is
V3 = VPN-(-VPTAT) = VPN + VPTAT (= Vref1: reference voltage 1)
It becomes. Desired temperature characteristics can be arbitrarily set by changing the impurity concentration of the high-concentration n-type gate, the low-concentration n-type gate, and the p-type gate.

Furthermore, when a resistor R1 is inserted into the source follower circuit as shown in FIG.
V3 = VPN * R2 / (R1 + R2) + VPTAT (= Vref2: Reference voltage 2)
And a reference voltage source capable of setting desired temperature characteristics even with a resistance ratio.

  FIG. 23 is a diagram for explaining an eleventh embodiment of the present invention. In the figure, the field effect transistors M1, M2, M3, and M4 are all p-type channels, the substrate and channel dope impurity concentrations are equal, and are formed in the n-well of the p-type substrate. The substrate potential of each field effect transistor is It is equal to the source potential. The ratio S = W / L between the channel width W and the channel length L is Sm1 = Sm2 and Sm3 = Sm4.

  The field effect transistor M1 has a high-concentration n-type gate, and is given a gate potential by a source follower circuit composed of a p-type channel field effect transistor M5 and a resistor R1 (when shorted without the resistor R2 in the figure). The field effect transistor M2 is a depletion type of a high-concentration p-type gate, and the gate and the source are connected to form a constant current source. The field effect transistor M3 is a low-concentration n-type gate field effect transistor, and the field-effect transistor M4 is a high-concentration n-type gate field effect transistor.

Since the same current flows through the pair field effect transistors M1 and M2, the gate-source voltage of the field effect transistor M1 is −VPN. Further, since the same current flows through the pair field effect transistors M3 and M4, the gate-source voltage of the field effect transistor M4 becomes (−VPTAT + V _GSM3 ).

Therefore, the source potential V3 of the field effect transistor M4 is
V3 = VPN + VPTAT (= Vref1: reference voltage 1)
It becomes. Desired temperature characteristics can be arbitrarily set by changing the impurity concentration of the high-concentration n-type gate, the low-concentration n-type gate, and the p-type gate.

Further, when a resistor R2 is inserted into the source follower circuit as shown in FIG.
V3 = VPN * R2 / (R1 + R2) + VPTAT (= Vref2: Reference voltage 2)
Thus, a reference voltage source capable of setting desired temperature characteristics even with a resistance ratio can be realized.

  FIG. 24 is a view for explaining a twelfth embodiment of the present invention. In the figure, field effect transistors M1 and M2 are n-type channel field effect transistors, and the substrate and channel dope impurity concentrations are equal and are formed in the p-well of the n-type substrate. The substrate potential of each field effect transistor is It is equal to the source potential. The field effect transistors M3 and M4 are p-type channel field effect transistors, and are formed in an n-well separated from the substrate of the n-type substrate with the same substrate and channel doping impurity concentration. The potential is equal to the source potential. The ratio S = W / L between the channel width W and the channel length L is Sm1 = Sm2 and Sm3 = Sm4.

  The field effect transistor M1 is a depletion type of a high-concentration n-type gate, and serves as a constant current source by connecting the gate and the source. The field effect transistor M2 has a high-concentration p-type gate, and a gate potential is applied by a source follower circuit including an n-type channel field effect transistor M5 and a resistor R2 (when the resistor R1 is short-circuited in the figure). The field effect transistor M3 is a depletion type of a high-concentration p-type gate, and connects the gate and the source to become a constant current source. The field effect transistor M4 is a low concentration p-type gate field effect transistor.

  Since the same current flows through the pair field effect transistors M1 and M2, the gate-source voltage of the field effect transistor M2 is VPN. Further, since the same current flows through the pair field effect transistors M3 and M4, the gate-source voltage of the field effect transistor M4 is −VPTAT.

Therefore, the source potential V3 of the field effect transistor M4 is
V3 = VPN + VPTAT (= Vref1: reference voltage 1)
It becomes.

Desired temperature characteristics can be arbitrarily set by changing the impurity concentration of the high concentration p-type gate, the low concentration p-type gate, and the n-type gate. Furthermore, when the resistor R1 is inserted into the source follower circuit,
V2 = VPN * R2 / (R1 + R2) + VPTAT (= Vref2: Reference voltage 2)
Thus, a reference voltage source capable of setting desired temperature characteristics even with a resistance ratio can be realized.

  FIG. 25 is a diagram for explaining the thirteenth embodiment. In the figure, field effect transistors M1 and M2 are p-type channel field effect transistors, and are formed in an n well separated from the substrate of the n-type substrate with the same substrate and channel doping impurity concentration. The substrate potential of the effect transistor is made equal to the source potential. Field effect transistors M3 and M4 are n-type channel field effect transistors, and the impurity concentrations of the substrate and the channel dope are equal and are formed in the p-well of the n-type substrate, and the substrate potential of each field effect transistor is equal to the source potential. It is. The ratio S = W / L between the channel width W and the channel length L is Sm1 = Sm2 and Sm3 = Sm4.

  The field effect transistor M1 has a high-concentration n-type gate, and is given a gate potential by a source follower circuit composed of a p-type channel field-effect transistor M5 and resistors R1 and R2. The field effect transistor M2 is a depletion type of a high-concentration p-type gate, and the gate and the source are connected to form a constant current source. The field effect transistor M3 is a depletion type with a high-concentration n-type gate, and the field effect transistor M4 is a depletion type with a low-concentration n-type gate. The gate and source are connected to form a constant current source.

  Since the same current flows through the pair field effect transistors M1 and M2, the gate-source voltage of the field effect transistor M1 is (VCC-VPN). Further, since the same current flows through the pair field effect transistors M3 and M4, the gate-source voltage of the field effect transistor M3 is −VPTAT.

Therefore, the source potential V3 of the field effect transistor M3 is
V3 = VPN * R2 / R1 + VPTAT (= Vref: reference voltage)
It becomes. Desired temperature characteristics can be arbitrarily set by changing the impurity concentration of the gates of the high-concentration n-type gate, the low-concentration n-type and the p-type gate, or the resistances R1 and R2. FIG. 26 is a diagram for explaining the fourteenth embodiment. In the figure, the field effect transistors M1, M2, M3, M4, M5, and M6 are all n-type channels, and the impurity concentrations of the substrate and the channel dope are equal and are formed in the p-well of the n-type substrate. The substrate potential of the transistor is equal to the source potential. The ratio S = W / L between the channel width W and the channel length L is Sm1 = Sm2, Sm3 = Sm4, Sm5 = Sm6.

  The field effect transistor M1 is a depletion type of a high-concentration n-type gate, and serves as a constant current source by connecting the gate and the source. The field effect transistor M2 is an enhancement type of a high-concentration p-type gate, and the gate and the drain are connected. The field effect transistors M3 and M5 are depletion type with a high concentration n-type gate, and the field effect transistors M4 and M6 are a depletion type with a low concentration n-type gate, and the gate and the source are connected to form a constant current source.

  Since the same current flows through the pair field effect transistors M1 and M2, the gate-source voltage of the field effect transistor M2 is VPN. Further, since the same current flows through the pair field effect transistors M3 and M4, the gate-source voltage of the field effect transistor M3 is −VPTAT. Also, since the same current flows through the pair field effect transistors M5 and M6, the gate-source voltage of the field effect transistor M5 is -VPTAT.

Therefore, the source potential V4 of the field effect transistor M5 is
V4 = VPN + VPTAT + VPTAT (= Vref: reference voltage)
It becomes.

  Desirable temperature characteristics include changing the impurity concentration of the high-concentration n-type gate, the low-concentration n-type gate, and the p-type gate, or a pair transistor (M3 / M4, M5) that is a voltage source having a positive temperature system number. / M6,...)) Can be arbitrarily set by changing the number of stages.

  FIG. 27 is a diagram for explaining the fifteenth embodiment. In the figure, the field effect transistors M1, M2, M3, M4, M5, M6, and M7 are all n-type channels, and the impurity concentrations of the substrate and the channel dope are equal and formed in the p-well of the n-type substrate. The substrate potential of the field effect transistor is made equal to the source potential. The ratio S = W / L between the channel width W and the channel length L is Sm1 = Sm2 = Sm3 and Sm4 = Sm5.

  The field effect transistor M1 is a depletion type of a high-concentration n-type gate, and serves as a constant current source by connecting the gate and the source. The field effect transistors M2 and M3 are enhancement-type high-concentration p-type gates that connect the gate and the drain. The field effect transistors M4 and M6 are high-concentration n-type gate depletion types, and the field-effect transistors M5 and M7 are low-concentration n-type gate depletion types. The gates and sources are connected to form a constant current source.

  Since the same current flows through the pair field effect transistors M1 and M2 and the pair field effect transistors M1 and M3, the gate-source voltages of the field effect transistors M2 and M3 are VPN. Since the same current flows through the pair field effect transistors M4 and M5, the gate-source voltage of the field effect transistor M4 is −VPTAT. Since the same current flows through the pair of field effect transistors M6 and M7, the gate-source voltage of the field effect transistor M6 is -VPTAT.

Therefore, the source potential V4 of the field effect transistor M6 is
V4 = VPN + VPN + VPTAT + VPTAT (= Vref: reference voltage)
It becomes.

  Desirable temperature characteristics include a pair transistor (M1 / M2, M1) that is a voltage source having a negative temperature system, or changing the impurity concentration of a high-concentration n-type gate, a low-concentration n-type gate, or a p-type gate. / M3,...) Or by changing the number of pairs of transistors (M4 / M5, M6 / M7,...) That are voltage sources having a positive temperature system number.

  FIG. 28 is a view for explaining a sixteenth embodiment of the present invention. In the figure, field effect transistors M1, M2, M3, M4, M5, and M6 are all enhancement type n-type channel field effect transistors, the substrate concentration is equal, and each field is formed in a p-well of an n-type substrate. The substrate potential of the effect transistor is made equal to the source potential. The ratio S = W / L of the channel width W to the channel length L is Sm1 = Sm2, Sm3 = Sm4, Sm5 = Sm6, and no channel doping is performed.

  The field effect transistor M1 is an enhancement type of a high-concentration n-type gate and serves as a constant current source that operates in a weak inversion or transition region by connecting the gate and the source. The field effect transistor M2 is an enhancement type of a high-concentration p-type gate, and the gate and the drain are connected. The field effect transistors M3 and M5 are high-concentration n-type gate enhancement types, and the field effect transistors M4 and M6 are low-concentration n-type gate enhancement types. It becomes a current source.

  Since the same current flows through the pair field effect transistors M1 and M2, the gate-source voltage of the field effect transistor M2 is VPN. Further, since the same current flows through the pair field effect transistors M3 and M4, the gate-source voltage of the field effect transistor M3 is −VPTAT. Also, since the same current flows through the pair field effect transistors M5 and M6, the gate-source voltage of the field effect transistor M5 is -VPTAT.

Therefore, the source potential V4 of the field effect transistor M5 is V4 = VPN + VPTAT + VPTAT (= Vref: reference voltage)
It becomes. Desired temperature characteristics can be arbitrarily set by changing the impurity concentration of the high-concentration n-type gate, the low-concentration n-type gate, and the p-type gate.

  As a specific numerical example, the threshold voltage of the high-concentration n-type field effect transistors M1, M3, and M5 is 0.2 V and the low-concentration n is a gate-source voltage through which a drain current of 1 nA flows. When the threshold voltage of the field effect transistors M4 and M6 is 0.3V and the S value, which is the displacement width of the gate-source voltage required to change the drain current by one digit, is 100 mV, the gate and the source are connected. The drain current of the field effect transistor M1 is 10 nA, and the drain currents of the field effect transistors M4 and M6 in which the gate and the source are connected are 1 nA.

  By using pair field effect transistors having the same substrate concentration without channel doping as described above, it is possible to improve pair characteristics and reduce current consumption.

It is a figure which shows the example of a conventional circuit structure (the 1). It is a figure which shows the conventional circuit structural example (the 2). It is a figure which shows the conventional circuit structural example (the 3). It is a band diagram of a MOS transistor. It is a figure for demonstrating the relationship of the fluctuation | variation of phosphorus concentration Ng1, Ng2 of the polysilicon gate of a pair transistor, and the fluctuation | variation of VTAT. It is a figure which shows the basic circuit structure of 1st Example of this invention. It is a figure which shows the basic circuit structure of 2nd Example of this invention. It is a figure which shows the basic circuit structure of 3rd Example of this invention. It is a figure which shows the basic circuit structure of the 1st modification of 3rd Example of this invention. It is a figure which shows the basic circuit structure of the 2nd modification of 3rd Example of this invention. It is a figure which shows the basic circuit structure of the 3rd modification of 3rd Example of this invention. FIG. 6A is a diagram showing a basic circuit configuration of a fourth embodiment of the present invention, and FIG. 6B is a diagram showing a basic circuit configuration of a modification thereof. It is the figure (A) which shows the basic circuit structure of the 1st modification of 4th Example of this invention, and the figure (B) which shows the basic circuit structure of the further modification. It is the figure (A) which shows the basic circuit structure of the 2nd modification of 4th Example of this invention, and the figure (B) which shows the basic circuit structure of the further modification. It is a figure which shows the basic circuit structure of the 3rd modification of 4th Example of this invention. It is a figure which shows the basic circuit structure of 5th Example of this invention. It is a figure which shows the relationship between the impurity of gate, density | concentration, and a threshold voltage. It is a figure which shows the basic circuit structure of 6th Example of this invention. It is a figure which shows the basic circuit structure of 7th Example of this invention. It is a figure which shows the basic circuit structure of 8th Example of this invention. It is a figure which shows the basic circuit structure of 9th Example of this invention. It is a figure which shows the basic circuit structure of 10th Example of this invention. It is a figure which shows the basic circuit structure of 11th Example of this invention. It is a figure which shows the basic circuit structure of 12th Example of this invention. It is a figure which shows the basic circuit structure of 13th Example of this invention. It is a figure which shows the basic circuit structure of 14th Example of this invention. It is a figure which shows the basic circuit structure of 15th Example of this invention. It is a figure which shows the basic circuit structure of 16th Example of this invention. It is a figure which shows the relationship between the impurity concentration of a semiconductor, and its specific resistance for demonstrating the effect at the time of terminating a dangling bond. It is a figure which shows the structural example of a resistance trimming means.

Explanation of symbols

M1: MOS transistor having a low concentration (Ng1) n-type polysilicon gate M2: MOS transistor having a high concentration (Ng2) n-type polysilicon gate M3 to M7, T1, T2, Ta, Tb: MOS transistors R, R1 to R4: resistors A1: differential amplifier

Claims (38)

  A voltage generation circuit using a plurality of field effect transistors having gates having at least a part of the same conductivity type and different impurity concentrations.   2. A voltage generation circuit using a field effect transistor according to claim 1, wherein the impurity concentration is varied by one digit or more. In the voltage generation circuit using the field effect transistor according to claim 2,
The plurality of field effect transistors include first and second field effect transistors having gates of the same conductivity type and different impurity concentrations,
The gates of the first field effect transistor and the second field effect transistor are connected, and the difference between the source voltages of the first field effect transistor and the second field effect transistor is output. A voltage generation circuit using a field effect transistor. In the voltage generation circuit using the field effect transistor according to claim 2,
The plurality of field effect transistors include first and second field effect transistors having gates of the same conductivity type and different impurity concentrations,
The source of the first field effect transistor and the second field effect transistor are connected, and the difference in gate voltage between the first field effect transistor and the second field effect transistor is output. A voltage generation circuit using a field effect transistor. In the voltage generation circuit using the field effect transistor according to claim 2,
The plurality of field effect transistors include first and second field effect transistors having gates of the same conductivity type and different impurity concentrations,
The gate-source voltage of one of the first field-effect transistor and the second field-effect transistor is set to 0 volts, and the gate-source voltage of the other field-effect transistor is output. A voltage generation circuit using a field effect transistor. In the voltage generation circuit using the field effect transistor according to claim 5,
The second field effect transistor is an n-type channel field effect transistor having a depletion type high concentration n type gate in which a gate and a source are connected;
The first field effect transistor is an n-type channel field effect transistor having a lightly doped n-type gate having a drain connected to a source of the second field effect transistor;
And a third n-channel field effect transistor and a resistor connected in series,
A source follower circuit for connecting a gate of the first field effect transistor to a connection point between the third n-type channel field effect transistor and a resistor to give a gate potential of the first field effect transistor;
A voltage generation circuit using a field effect transistor, wherein the gate potential of the first field effect transistor is output from the connection point. In the voltage generation circuit using the field effect transistor according to claim 5,
The second field effect transistor is an n-type channel field effect transistor having a depletion type high concentration n type gate in which a gate and a source are connected;
The first field effect transistor is an n-type channel field effect transistor having a low concentration n-type gate having a drain connected to a source of the second field effect transistor; and
A third n-channel field effect transistor, a first resistor and a second resistor connected in series;
A source follower circuit for connecting a gate of the first field effect transistor to a connection point between the third n-type channel field effect transistor and a first resistor to give a gate potential of the first field effect transistor; ,
A voltage generation circuit using a field-effect transistor, wherein a potential at a connection point between the first resistor and the second resistor is output. In the voltage generation circuit using the field effect transistor according to claim 5,
The second field effect transistor is an n-type channel field effect transistor having a depletion type high concentration n type gate in which a gate and a source are connected;
The first field effect transistor is an n-type channel field effect transistor having a low concentration n-type gate having a drain connected to a source of the second field effect transistor; and
A third n-channel field effect transistor, a first resistor and a second resistor connected in series;
A source follower circuit for providing a gate potential of the first field-effect transistor by connecting a gate of the first field-effect transistor to a connection point between the first resistor and the second resistor;
A voltage generation circuit using a field effect transistor, wherein a potential at a connection point between the third n-type channel MOS transistor and the first resistor is used as an output. In the voltage generation circuit using the field effect transistor according to claim 7 or 8,
A voltage generating circuit comprising means capable of adjusting values of the first resistor and the second resistor after diffusion and film formation steps in manufacturing.   10. The voltage generation circuit using the field effect transistor according to claim 6, wherein the first field effect transistor and the second field effect transistor are p-type channel field effect transistors. A voltage generation circuit using a field effect transistor. In the voltage generation circuit using the field effect transistor according to any one of claims 2 to 10,
The plurality of field effect transistors include first and second field effect transistors having gates of the same conductivity type and different impurity concentrations,
A voltage generating circuit, wherein drain currents of the first and second field effect transistors are equalized. A voltage source circuit having a positive temperature coefficient composed of a plurality of field effect transistors having semiconductor gates having at least a part of the same conductivity type and different impurity concentrations;
A reference voltage source circuit using a field effect transistor, comprising a voltage source circuit having a negative temperature coefficient composed of a plurality of field effect transistors having at least a part of semiconductor gates of different conductivity types. The reference voltage source circuit using the field effect transistor according to claim 12,
The first to third field effects in which the voltage source circuit having a positive temperature coefficient and the voltage source circuit having a negative temperature coefficient are connected in series having at least a part of semiconductor gates having different conductivity types or impurity concentrations. A reference voltage source circuit using a field effect transistor, characterized by comprising a transistor. In the reference voltage circuit using the field effect transistor according to claim 13,
A depletion type n-type gate having a high concentration n-type gate and an n-type channel first field effect transistor having a gate and a source connected thereto, an n-type channel second field effect transistor having a low concentration n-type gate, and a p-type And an n-channel third field effect transistor in which the gate and the drain are connected in series with the enhancement type of the gate,
Providing a source follower circuit for providing a gate potential of the second field effect transistor;
A reference voltage source circuit using a field effect transistor, wherein a gate voltage of the second field effect transistor is used as a reference voltage output point. In the reference voltage circuit using the field effect transistor according to claim 13,
A p-channel first field effect transistor having an n-type gate enhancement type and a gate and drain connected, a p-type channel second field effect transistor having a low-concentration p-type gate, and a high-concentration p-type A depletion type of the gate of the p-channel third field effect transistor in which the gate and the source are connected in series, and
Providing a source follower circuit for providing a gate potential of the second field effect transistor;
A reference voltage source circuit using a field effect transistor, wherein a gate voltage of the second field effect transistor is used as a reference voltage output point. In the reference voltage circuit using the field effect transistor according to claim 12,
The voltage source circuit having the positive temperature coefficient and the voltage source circuit having the negative temperature coefficient are configured by at least a part of first to fourth field effect transistors having semiconductor gates having different conductivity types or impurity concentrations. A reference voltage source circuit. The reference voltage circuit using the field effect transistor according to claim 16,
An n-type gate depletion type n-channel first field effect transistor in which the gate and source are connected and a p-type n-channel second field effect transistor connected in series, and
Providing a source follower circuit for providing a gate potential of the second field effect transistor; and
The third field effect transistor of the n-type channel of the high-concentration n-type gate to which the gate potential is applied by the source follower circuit and the fourth field effect transistor of the n-type channel of the low-concentration n-type gate are input transistors. Configured differential amplifier,
A reference voltage source circuit using a field effect transistor, wherein a gate potential of the fourth field effect transistor is used as a reference voltage output point. The reference voltage circuit using the field effect transistor according to claim 16,
The n-type gate p-type channel first field effect transistor and the p-type gate depletion type p-type channel second field effect transistor in which the gate and the source are connected are connected in series.
Providing a source follower circuit for providing a gate potential of the second field effect transistor; and
The third field effect transistor of the n-type channel of the high-concentration n-type gate to which the gate potential is applied by the source follower circuit and the fourth field effect transistor of the n-type channel of the low-concentration n-type gate are input transistors. Configured differential amplifier,
A reference voltage source circuit using a field effect transistor, wherein a gate potential of the fourth field effect transistor is used as a reference voltage output point. The reference voltage circuit using the field effect transistor according to claim 16,
An n-type gate depletion type n-channel first field effect transistor in which the gate and source are connected and a p-type n-channel second field effect transistor connected in series, and
Providing a source follower circuit for providing a gate potential of the second field effect transistor; and
The third field effect transistor of the n-type channel of the high-concentration n-type gate to which the gate potential is applied by the source follower circuit, and the n-type channel of the depletion type of the low-concentration n-type gate and having the gate and source at the GND potential A fourth field effect transistor in series,
A reference voltage source circuit using a field effect transistor, wherein a connection point between the third field effect transistor and the fourth field effect transistor is a reference voltage output point. The reference voltage circuit using the field effect transistor according to claim 16,
The n-type gate p-type channel first field effect transistor and the p-type gate depletion type p-type channel second field effect transistor in which the gate and the source are connected are connected in series.
Providing a source follower circuit for providing a gate potential of the first field effect transistor; and
A third field effect transistor of the p-type channel of the low-concentration n-type gate to which a gate voltage is applied by the source follower circuit, and a fourth electric field of the p-type channel in which the gate and drain of the high-concentration n-type gate are connected. Connect effect transistors in series,
A reference voltage source circuit using a field effect transistor, wherein a connection point between the third field effect transistor and the fourth field effect transistor is a reference voltage output point. The reference voltage circuit using the field effect transistor according to claim 16,
An n-type gate depletion type n-channel first field effect transistor in which the gate and source are connected and a p-type gate n-type channel second field effect transistor are connected in series, and
Providing a source follower circuit for providing a gate potential of the second field effect transistor; and
A p-channel third field effect transistor in which a gate and a source are connected in a depletion type with a high-concentration p-type gate, and a p-type channel of a low-concentration p-type gate to which a gate voltage is applied by the source follower circuit. 4 field effect transistors connected in series,
A reference voltage source circuit using a field effect transistor, wherein a connection point between the third field effect transistor and the fourth field effect transistor is a reference voltage output point. The reference voltage circuit using the field effect transistor according to claim 16,
The n-type gate p-type channel first field effect transistor and the p-type gate depletion type p-type channel second field effect transistor in which the gate and the source are connected are connected in series.
Providing a source follower circuit for providing a gate potential of the first field effect transistor; and
The third field effect transistor of the depletion type n-type channel of the high concentration n type gate to which the gate voltage is applied by the source follower circuit, and the n type channel of the n type channel in which the gate and the source are connected by the low concentration n type gate. 4 field effect transistors connected in series,
A reference voltage source circuit using a field effect transistor, wherein a connection point between the third field effect transistor and the fourth field effect transistor is a reference voltage output point. In the reference voltage circuit using the field effect transistor according to claim 12,
A reference voltage source circuit using a field effect transistor, wherein one or both of the voltage source circuit having the positive temperature coefficient and the voltage source circuit having the negative temperature coefficient are used. . A reference voltage circuit using the field effect transistor according to claim 23,
The voltage source circuit having the negative temperature system number includes an n-type gate depletion type n-channel first field effect transistor in which the gate and the source are connected, and a p-type gate enhancement type gate and drain. A series connection configuration of second field effect transistors of connected n-type channels,
The voltage source circuit having the positive temperature system number includes a third field effect transistor of an n-type channel of a high-concentration n-type gate to which a gate potential is applied by a drain voltage of the second field-effect transistor, and a low-concentration n A series connection configuration of fourth field effect transistors of an n-type channel in which a depletion type of a gate type and a gate and a source have a GND potential;
A fifth field effect transistor to which a gate potential is applied by a voltage at a connection point between the third field effect transistor and the fourth field effect transistor, and a depletion type of a low-concentration n-type gate. A series connection configuration of sixth n-channel field effect transistors,
A reference voltage source circuit using a field effect transistor, wherein a connection point between the fifth field effect transistor and the sixth field effect transistor is a reference voltage output point. A reference voltage circuit using the field effect transistor according to claim 23,
The voltage source circuit having the negative temperature system number includes an n-type gate depletion type n-channel first field effect transistor in which the gate and the source are connected, and a p-type gate enhancement type gate and drain. A series connection configuration of second and third field effect transistors of connected n-type channels;
The voltage source circuit having the positive temperature system number is a n-channel fourth field effect transistor having a high-concentration n-type gate and a depletion type having a low-concentration n-type gate. A series-connected configuration of fifth field effect transistors of the type channel;
A high-concentration n-type n-channel sixth field-effect transistor to which a gate potential is applied by a voltage at a connection point between the fourth field-effect transistor and the fifth field-effect transistor; and a low-concentration n-type gate A depletion type n-channel seventh field effect transistor having a GND potential at the gate and the source,
A reference voltage source circuit using a field effect transistor, wherein a connection point between the sixth field effect transistor and the seventh field effect transistor is a reference voltage output point. In the reference voltage circuit using the field effect transistor according to claim 12,
The field effect transistors constituting the voltage source circuit having the positive temperature coefficient and the voltage source circuit having the negative temperature coefficient have at least a part of gates having different conductivity types or impurity concentrations and do not use channel doping. A reference voltage source circuit using a field effect transistor. A reference voltage source circuit using the field effect transistor according to claim 26,
The voltage source circuit having the negative temperature system includes an n-type gate enhancement type n-channel first field effect transistor in which the gate and the source are connected, and a p-type gate enhancement type gate and drain. A series connection configuration of second field effect transistors of connected n-type channels,
The voltage source circuit having the positive temperature system number includes an n-type third field effect transistor having a high-concentration n-type gate and an n-type enhancement type having a low-concentration n-type gate and a gate-source GND potential. A series connection configuration of fourth field effect transistors in the channel;
A fifth field effect transistor of an n-type channel of a high-concentration n-type gate to which a gate potential is applied by a voltage at a connection point between the third field-effect transistor and the fourth field-effect transistor; and a low-concentration n-type gate And a series connection configuration of sixth field effect transistors of n-type channel with the gate and the source at the GND potential.
A reference voltage source circuit using a field effect transistor, wherein a connection point between the fifth field effect transistor and the sixth field effect transistor is a reference voltage output point. A reference voltage source circuit using the field effect transistor according to any one of claims 15 to 27,
A reference voltage source circuit characterized in that drain currents of at least some of the field effect transistors constituting each of the voltage source circuit having a positive temperature coefficient and the voltage source circuit having a negative temperature coefficient are made equal. In the voltage generation circuit using the field effect transistor according to any one of claims 1 to 11,
A voltage generating circuit, wherein each gate is made of single crystal silicon. In the voltage generation circuit using the field effect transistor according to any one of claims 1 to 11,
A voltage generating circuit, wherein each gate is made of polycrystalline silicon. In the voltage generation circuit using the field effect transistor according to claim 30,
A voltage generating circuit, wherein approximately 98% or more of the dangling bonds of the polycrystalline silicon are terminated. In the voltage generation circuit using the field effect transistor according to any one of claims 1 to 11,
A voltage generating circuit, wherein each gate is made of polycrystalline Si _X Ge _1-X . In the voltage generation circuit using the field effect transistor according to claim 32,
The composition ratio of Si _X Ge _1-X is approximately
0.01 <X <0.5
A voltage generation circuit characterized by being in the range of. A reference voltage source circuit using the field effect transistor according to any one of claims 12 to 28,
A reference voltage source circuit, wherein each gate is made of single crystal silicon. A reference voltage source circuit using the field effect transistor according to any one of claims 12 to 28,
A reference voltage source circuit, wherein each gate is made of polycrystalline silicon. A reference voltage source circuit using the field effect transistor according to claim 35,
A reference voltage source circuit, wherein approximately 98% or more of the dangling bonds of the polycrystalline silicon are terminated. A reference voltage source circuit using the field effect transistor according to any one of claims 12 to 28,
A reference voltage source circuit, wherein each gate is made of polycrystalline Si _X Ge _1-X . A reference voltage source circuit using the field effect transistor according to claim 37,
The composition ratio of Si _X Ge _1-X is approximately
0.01 <X <0.5
A reference voltage source circuit characterized by being in the range of

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