JP2007267290A - Solid-state imaging device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device for improving the sensitivity of a specific color sequence with average exposure time different for each color sequence, in the solid-state imaging device including a driving mode using both of vertical thinning-out read and pixel addition. <P>SOLUTION: In the solid-state imaging device including color filters of a Bayer array, the distance between the center of gravity of pixels with two or more B pixels (pixels of a first color sequence) added thereto and the center of gravity of pixels with two or more R pixels (pixels of a second color sequence) added thereto is set so that pixels to be read during motion picture imaging are arranged at equal intervals. Furthermore, a read gate is provided, which drives the pixels to be read during motion picture imaging, independently of other sequences, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a driving method thereof, and more particularly to a technique for adding signal charges read from a photodiode.

  FIG. 7 shows a schematic configuration diagram of a CCD which is a general solid-state imaging device. FIG. 7A is a diagram showing an outline of the entire configuration, and FIG. 7B is a diagram showing a positional relationship between a photodiode as a photoelectric conversion unit and a drive gate of a vertical CCD, and FIG. () Is a diagram showing an example of an arrangement of color filters arranged on a photodiode.

  Light collected by a lens or the like (not shown) enters a photodiode 700 provided in each of the pixels arranged in a matrix and is converted into signal charges. Usually, charge reading from the photodiode 700 is performed for each row.

  The signal charges are sequentially transferred in the vertical CCD 701 and reach the horizontal CCD 702. Thereafter, the signal charge is transferred in the horizontal CCD 702 and reaches the amplifier 703 which is an amplifying unit. The signal charge is amplified by the amplifier 703 and output as a pixel signal.

  In the vertical CCD 701, a plurality of gates 704 are vertically arranged on the transfer channel via an insulating film. As shown in FIG. 7B, two gates are provided for one photodiode 700. One of the two gates is a read / transfer gate, and the other is a transfer gate.

  In the example shown in FIG. 7B, six gates having different applied signals are periodically arranged. In FIG. 7B, three types of gates corresponding to φV1, φV3, and φV5 are read / transfer gates, and three types of gates corresponding to φV2, φV4, and φV6 are transfer gates. When a high voltage is applied to the read / transfer gate, signal charges are read from the photodiode 700. Thereafter, signals are applied to the gates corresponding to φV1 to φV6 at different timings, and charges move downward from the top of the drawing.

  Further, the array shown in FIG. 7C is an array of primary color filters called a Bayer array. In the Bayer arrangement, R, G, and B filters are arranged with 2 × 2 pixels as a unit.

  The solid-state image sensor is mounted on, for example, a digital still camera. The digital still camera reads a signal charge for each row and then processes a pixel signal obtained from each row to obtain a color signal.

  In recent years, the number of pixels of a solid-state imaging device mounted on a digital still camera or the like has been extremely increased. In recent years, digital still cameras are required not only for still image shooting but also for moving image shooting. The moving image shooting function is used, for example, in a monitor mode before shooting a still image. As described above, a technique for reducing the apparent number of pixels in the vertical direction is generally adopted for a digital still camera having a very large number of pixels and having a still image shooting function and a moving image shooting function. . In other words, a digital still camera reads signal charges from all pixels (all photodiodes) when shooting a still image, and when shooting a moving image, the digital still camera uses one of all pixels to increase the frame rate. The signal charges are read by thinning out the pixels of the portion, and the read signal charges are added to reduce the apparent number of pixels in the vertical direction.

  Furthermore, in recent years, digital still cameras that can realize a plurality of driving modes, for example, driving in a mode of 30 fps and driving in a mode of 60 fps have appeared. Thus, in a digital still camera that can realize a plurality of drive modes, the apparent number of pixels in the vertical direction is often changed in accordance with the drive mode. Hereinafter, this reason will be briefly described.

  In general, a higher image resolution is better, but in order to secure a high frame rate of 30 fps, 60 fps or more, it is necessary to reduce the vertical resolution in a multi-pixel solid-state image sensor, particularly a CCD. is there. On the other hand, the resolution of the moving image is preferably about 240H lines corresponding to QVGA when used as a through image, and about 480H lines corresponding to VGA when used for recording moving images. It is said that. Therefore, the apparent number of pixels in the vertical direction is changed according to the change in the frame rate. In order to reduce the apparent number of pixels in the vertical direction, the design is made in consideration of the number of horizontal lines, the frame rate, and the operating characteristics of the solid-state imaging device.

  Further, when the pixel usage rate is low, a false signal called smear and a false signal called moire tend to appear. Therefore, in general, pixel addition is performed in addition to thinning out pixels in the vertical direction in order to increase the pixel usage rate. In other words, if you try to reduce the apparent number of pixels only by thinning out the pixels, the pixel usage rate will decrease, so instead of reducing the number of pixels to be thinned out, adding the read vertical signal charge will make the vertical direction apparent The number of pixels is reduced.

  In the case of adding pixels, it is desirable to select pixels to be added (reading targets) so that pixel centroids are evenly arranged in order to prevent generation of false colors in the added image. FIG. 8 shows an example of pixel addition in the vertical direction. When the pixel to be added is selected as shown in FIG. 8A, the pixel centroid distribution becomes more uniform than when the pixel to be added is selected as shown in FIG. 8B, and a false color is generated. Hateful.

  Further, when the signal charge is added, the output sensitivity per pixel is increased in a pseudo manner. This is because comparing the case where pixel addition is performed with the case where pixel addition is not performed, the exposure time required for obtaining the same output can be shortened when pixel addition is performed.

  Although related to device design, there are many solid-state imaging devices that are configured to read signal charges in multiple times from a photodiode to a vertical CCD when adding pixels in the vertical direction. At this time, since the sensitivity becomes pseudo-high as described above, it is desirable that the exposure time of the pixel to be added is set to a constant time between all color series. For example, if the upper row (Gb-B) of one unit of the Bayer array shown in FIG. 7C is the first color series and the lower row (R-Gr) is the second color series, these If there is a time difference in exposure time between the color series, a difference occurs in the color spectrum depending on the shutter speed.

  This will be described with reference to FIG. FIG. 9 is a diagram showing the relationship between the shutter timing and the signal charge readout timing. The difference between the timing at which the mechanical shutter closes and the timing at which the signal for reading out the signal charge from the pixel (photodiode) is applied to the gate is the exposure. Hit the time. During the low-speed shutter operation shown in FIG. 9A, since the exposure time is long, the difference between the exposure time in the first color series and the exposure time in the second color series is relative to the exposure time itself. Although it is small, there is no problem, but since the exposure time itself is shortened during the high-speed shutter operation shown in FIG. 9B, the difference in the exposure time for each color series affects the color reproducibility of the output image.

  Since it is necessary to make the characteristics at the time of readout uniform, it is actually difficult to drive the exposure time of all the pixels by driving multiple types of readout and transfer gates. There has been proposed a technique for equalizing the apparent exposure time by making the total amount of each of the color series uniform (see, for example, Patent Document 1).

However, due to the recent reduction in size of the aperture, there is a phenomenon that the sensitivity of the R pixel is lower than that of the other color pixels due to the wavelength of the light, and a method for making the exposure time between the color sequences constant. Then, there is a difference in color spectroscopy.
Japanese Patent No. 3345182

  In view of the above problems, the present invention provides a difference in exposure time while maintaining a uniform pixel centroid distribution in a shooting mode (drive mode) in which pixel addition is performed in the vertical direction. It is an object of the present invention to provide a solid-state imaging device capable of improving sensitivity and realizing a high frame rate and a driving method thereof.

  A solid-state imaging device according to a first aspect of the present invention includes a plurality of pixels each having a photoelectric conversion unit and arranged in a matrix, and a first color series and a second color series arranged on the pixels. Are alternately arranged in the column direction, a vertical CCD that reads and transfers the signal charge accumulated in the photoelectric conversion unit, and a horizontal CCD that transfers the signal charge transferred from the vertical CCD to the amplification unit. , And a solid-state imaging device having a drive mode in which signal charges are read out from pixels in each of the first and second color series arranged in the vertical direction and added in the vertical CCD for each color series. The pixels to be read from which the signal charges are read out in the drive mode are arranged so that the pixel centroids for each color series after addition are evenly arranged in the vertical direction, and the vertical CCD is connected to the drive mode. To as a gate for reading out a signal charge, independently have a four or more gates can be driven to the other strains, it is characterized.

  According to a second aspect of the present invention, there is provided the solid-state imaging device according to the first aspect, wherein each readout target pixel of the first and second color series is a predetermined repeating unit. Two or more gates are arranged for each number of pixels, and four or more types of gates that can be driven independently of other systems are provided so that signal charges are added for each repeating unit. It is characterized by that.

  A solid-state imaging device according to claim 3 of the present invention is the solid-state imaging device according to claim 1 or 2, wherein the pixels to be read are arranged so as not to be adjacent to each other. And

  A solid-state imaging device according to claim 4 of the present invention is the solid-state imaging device according to any one of claims 1 to 3, wherein the number of pixels to be read is the first and second color series. It is characterized by differing between.

  A solid-state image sensor driving method according to claim 5 of the present invention is the solid-state image sensor driving method according to any one of claims 1 to 4, wherein the signal charge is supplied from the start of exposure in the driving mode. The signal charge is read so that the time until reading is different for each pixel to be read, and the average exposure time is different between the pixels to be read for the first and second color series. To do.

  According to a sixth aspect of the present invention, there is provided a method for driving a solid-state image pickup device according to the fifth aspect, wherein at least one of the first or second color series is read. A pixel from which signal charges are read out is selected from the target pixels.

  According to the present invention, the exposure time of each pixel to be read can be changed by controlling the readout timing, and the sensitivity can be improved by increasing the exposure time of pixels of a specific color series. A frame rate can be realized.

(Embodiment 1)
FIG. 1 is a schematic diagram for explaining the configuration of the solid-state imaging element according to Embodiment 1 of the present invention. FIG. 1A is a diagram showing an arrangement relationship between a photodiode serving as a photoelectric conversion unit and a drive gate of a vertical CCD, and FIG. 1B shows an arrangement of pixels to be added (pixels to be read) in the vertical direction. FIG.

  The photodiode and the vertical CCD in the first embodiment correspond to the photodiode 700 and the vertical CCD 701 shown in FIG. 7, and the basic operation is as described above. The color filter array is the same as that shown in FIG.

  That is, the pixels are arranged in a matrix, and a color filter in which the first color series and the second color series are alternately arranged in the column direction is arranged on these pixels. The vertical CCD reads out the signal charge accumulated by the photodiode and transfers it to the horizontal CCD. Usually, charge reading from the photodiode is performed for each row. The horizontal CCD transfers the signal charge transferred from the vertical CCD to an amplifying unit (amplifier). The amplifier amplifies the signal charge and outputs it as a pixel signal. In addition, the solid-state imaging device has a drive mode in which signal charges are thinned out and read out from the pixels of the first and second color series arranged in the vertical direction and added in the vertical CCD for each color series.

  As shown in FIG. 1A, a photodiode is disposed in each pixel, and two types of gates, a read / transfer gate and a transfer gate, are disposed in each photodiode. In FIG. 1A, seven types of gates corresponding to φV1, φV3, φV5, φV1A, φV1C, φV3A, and φV3C are read / transfer gates, and three types of gates corresponding to φV2, φV4, and φV6 are transfer gates. It is.

  The vertical CCD of the solid-state imaging device in the first embodiment is 6-phase drive, and the read / transfer gate corresponding to φV1A, φV1C, φV3A, and φV3C can be driven independently of other systems. Gates corresponding to these φV1A, φV1C, φV3A, and φV3C are provided corresponding to the photodiodes PD1 to PD4 that are pixels to be added (pixels to be read). In the configuration shown in FIG. 1A, vertical pixel addition and vertical thinning readout can be performed using 12 pixels as a repeating unit.

  Further, as shown in FIG. 1B, the addition target pixels PD1 to PD4 are arranged so as not to be adjacent to each other, and the distance between the midpoint of PD1 and PD2 to be added and the midpoint of PD3 and PD4. Are arranged at equal intervals. That is, the addition target pixels PD1 to PD4 are arranged so that the pixel centroids after the pixel addition are arranged uniformly.

  In the vertical CCD, in the drive mode in which vertical pixel addition and vertical thinning readout operations are performed, signal charges from the same color series PD1 and PD2 and other same color series PD3 and PD4 are stored in the vertical CCD. After the addition, the addition signals of PD1 and PD2 and the addition signals of PD3 and PD4 are moved from the top to the bottom of the drawing. In this way, the vertical CCD outputs two signals out of the signals of 12 pixels arranged vertically, so-called vertical 1/6 thinning driving method (driving method in which the vertical thinning rate is 1/6) ) Is adopted.

  FIG. 2 shows a timing chart during pixel addition and thinning readout operations of the solid-state imaging device according to the first embodiment. For example, at time T1, an intermediate voltage (VM level voltage) is applied to the gates corresponding to φV3 to φV6, which is a signal charge accumulation region. Further, a low voltage (low level voltage) is applied to the gates corresponding to the remaining φV1 and φV2 to form a barrier region. In this state, a high voltage (high level voltage) is applied to the gate corresponding to φV3A to read the signal charge of PD1 which is the first color series, and then the signals to the gate in the order of φV1, φV3, φV2, and φV4 are read. The applied voltage level is controlled to move the storage region, and the signal charge is moved using the gates corresponding to φV1, φV2, φV5, and φV6 as the storage region and the gates corresponding to φV3 and φV4 as the barrier region. By repeating this procedure, the thinning-out readout operation and the movement control of the accumulation region are performed, and the addition target pixels are read out and added in the order of PD1 to PD4 from time T1 to time T3.

  That is, as shown in FIG. 2, a high voltage (high level voltage) is applied to the gate corresponding to φV3A at time T1, and the signal charges of the first color series are read from PD1. Next, at time T2, a high voltage (high level voltage) is applied to the gates corresponding to φV1A and φV1C, and the signal charges of the first color series are read from PD2 and the second color series are read from PD3. Next, at time T <b> 3, a high voltage (high level voltage) is applied to the gate corresponding to φV <b> 3 </ b> C, and the signal charges of the second color series are read from PD <b> 4.

  The signal charge from PD1 is read out under the gate corresponding to φV3A, then transferred in the vertical CCD from φV4 → φV5 → φV6, and then read out from the gate corresponding to φV1A from PD2. The charge is added and transferred in the vertical CCD. Similarly, after the signal charge from PD3 is read under the gate corresponding to φV1C, it is transferred in the vertical CCD from φV2 → φV3 → φV4 → φV5 → φV6 → φV1 → φV2, and then corresponds to φV3C. The signal charge from the PD 4 read out under the gate is added and further transferred in the vertical CCD.

  As described above, with the gate configuration shown in FIG. 1, the vertical CCD receives the signal charge of the first color series twice for the first and second readings, and the second for the third and fourth readings. The readout operation is performed four times for the signal charges of the color series.

  By performing pixel addition and decimation readout operations at the above timing, the average exposure time (PD1 + PD2) of the first color series is shortened and the average exposure time (PD3 + PD4) of the second color series is lengthened as shown in FIG. The sensitivity of the second color series can be improved more than the sensitivity of the first color series. Further, a high frame rate can be realized by thinning readout in the vertical direction and pixel addition.

  As described with reference to FIG. 9, the “exposure time of the pixel to be added” refers to the timing at which the mechanical shutter is closed and the timing at which the signal for reading the signal charge from the pixel to be added (photodiode) is applied to the gate. And the difference time. The “average exposure time” is, for example, an average value of the time from the start of exposure to time T1 and the time from the start of exposure to time T2.

(Embodiment 2)
FIG. 3 is a schematic diagram for explaining the configuration of the solid-state imaging element according to Embodiment 2 of the present invention. FIG. 3A is a diagram showing the positional relationship between a photodiode as a photoelectric conversion unit and a drive gate of a vertical CCD, and FIG. 3B shows the layout of pixels to be added (pixels to be read) in the vertical direction. FIG.

  In the second embodiment, the signal charge is read also from PD5 arranged between PD3 and PD4 which are the second color series, and the signal charge is added to the signal charge from PD3 and PD4 and outputted. This is different from the first embodiment described above. Hereinafter, this difference will be mainly described.

  The vertical CCD in the second embodiment is 6-phase drive as in the first embodiment. Further, as shown in FIG. 3A, every other PD3 to PD5 that are pixels to be added (pixels to be read) are arranged so as not to be adjacent to each other. Further, as shown in FIG. 3B, the addition target pixels PD1 to PD5 are arranged so that the distances between the midpoints of PD1 and PD2 to be added and the midpoints of PD3 to PD5 are equal. ing. That is, as in the first embodiment described above, the addition target pixels (read target pixels) PD1 to PD5 are arranged so that the pixel centroids after pixel addition for each color series are evenly arranged. Further, the vertical CCD in the second embodiment is provided with a read / transfer gate (gate corresponding to φV5C) that can be driven independently of other systems, corresponding to PD5. In the configuration shown in FIG. 3A, similarly to the first embodiment, vertical pixel addition and vertical thinning readout can be performed using 12 pixels as a repeating unit.

  In the vertical CCD, in the drive mode in which vertical pixel addition and vertical thinning readout operations are performed, signal charges from the same color series PD1 and PD2 and the other same color series PD3 to PD5 are stored in the vertical CCD. After the addition, the addition signals PD1 and PD2 and the addition signals PD3 to PD5 are moved from the top to the bottom of the drawing. As described above, the vertical CCD employs a so-called vertical 1/6 thinning driving method that outputs two signals out of signals for 12 pixels arranged vertically.

  FIG. 4 is a timing chart at the time of pixel addition and thinning readout operations of the solid-state imaging device according to the second embodiment. For example, at time T1, an intermediate voltage (VM level voltage) is applied to the gates corresponding to φV3 to φV6, which is a signal charge accumulation region. Further, a low voltage (low level voltage) is applied to the gates corresponding to the remaining φV1 and φV2 to form a barrier region. In this state, a high voltage (high level voltage) is applied to the gate corresponding to φV3A to read the signal charge of PD1 which is the first color series, and then the signals to the gate in the order of φV1, φV3, φV2, and φV4 are read. The applied voltage level is controlled to move the storage region, and the signal charge is moved using the gates corresponding to φV1, φV2, φV5, and φV6 as the storage region and the gates corresponding to φV3 and φV4 as the barrier region. By repeating this procedure, the thinning-out reading operation and the movement control of the accumulation area are performed, and the addition target pixel is read and added in the order of PD1, PD2, PD3, PD5, and PD4 from time T1 to time T4.

  That is, as shown in FIG. 4, at time T1, a high voltage (high level voltage) is applied to the gate corresponding to φV3A, and the signal charges of the first color series are read from PD1. Next, at time T2, a high voltage (high level voltage) is applied to the gates corresponding to φV1A and φV1C, and the signal charges of the first color series are read from PD2 and the second color series are read from PD3. Next, at time T <b> 3, a high voltage (high level voltage) is applied to the gate corresponding to φV <b> 5 </ b> C, and the signal charges of the second color series are read from PD <b> 5. Next, at time T4, a high voltage (high level voltage) is applied to the gate corresponding to φV3C, and the signal charges of the second color series are read from PD4.

  The signal charge from PD1 is read out under the gate corresponding to φV3A, then transferred in the vertical CCD from φV4 → φV5 → φV6, and then read out from the gate corresponding to φV1A from PD2. The charge is added and transferred in the vertical CCD. Similarly, the signal charge from PD3 is read under the gate corresponding to φV1C, then transferred in the vertical CCD from φV2 → φV3 → φV4, and then read out under the gate corresponding to φV5C. Is added to the signal charge from. Further, after being transferred in the order of φV6 → φV1 → φV2, the signal charge from PD4 read out under the gate corresponding to φV3C is added and transferred in the vertical CCD.

  As described above, with the gate configuration shown in FIG. 3, the vertical CCD can read the first color series signal charge twice in the first and second readouts, the third, fourth, and fifth readouts. Thus, the signal charge of the second color series is read out three times, for a total of five times.

  By performing the pixel addition and thinning readout operation at the above timing, the average exposure time (PD1 + PD2) of the first color series is shortened and the average exposure time (PD3 + PD4 + PD5) of the second color series is lengthened as shown in FIG. The sensitivity of the second color series can be improved more than the sensitivity of the first color series. Further, a high frame rate can be realized by thinning readout in the vertical direction and pixel addition.

  According to the first and second embodiments, since the pixels to be added are arranged so as not to be adjacent to each other, the influence of the potential of the adjacent photodiode can be removed, and the output level of the photodiode becomes the Knee region. It can be used and a wide dynamic range can be realized.

  Further, according to the first and second embodiments, the signal amount of the second color series can be made larger than the signal amount of the first color series and the exposure time can be adjusted. Adjustment is possible. Since the setting of the color sensitivity of the photodiode varies depending on the manufacturing process or the like, for example, when a photodiode set to have a low R sensitivity among RGB is used, the signal amount is relatively set as described above. By increasing the color reproducibility, the color reproducibility can be improved.

  If only the signal amount is relatively changed, the signal charge may be read from only one of PD1 and PD2 in the configuration described in the first embodiment. However, in this case, since the entire signal amount is reduced, the sensitivity is reduced. On the other hand, the signal amount of the first color series can be made lower than the signal amount of the second color series. For example, in the configuration described in the first embodiment, the PD3 The signal charge may be read from only one of the PDs 4 or the signal charge may be read from only one of PD3 to PD5 in the configuration described in the second embodiment. Such a drive is also possible because the addition target pixel is associated with a gate that can be driven independently.

(Embodiment 3)
FIG. 5 is a schematic diagram for explaining the configuration of the solid-state imaging element according to Embodiment 3 of the present invention. FIG. 5A is a diagram showing the arrangement relationship between the photodiodes as photoelectric conversion units and the drive gates of the vertical CCD, and FIG. 5B shows the arrangement of pixels to be added (pixels to be read) in the vertical direction. FIG.

  Note that the photodiode and the vertical CCD in the third embodiment correspond to the photodiode 700 and the vertical CCD 701 shown in FIG. 7, and the basic operation is as described above. The color filter array is the same as that shown in FIG.

  That is, the pixels are arranged in a matrix, and a color filter in which the first color series and the second color series are alternately arranged in the column direction is arranged on these pixels. The vertical CCD reads out the signal charge accumulated by the photodiode and transfers it to the horizontal CCD. Usually, charge reading from the photodiode is performed for each row. The horizontal CCD transfers the signal charge transferred from the vertical CCD to an amplifying unit (amplifier). The amplifier amplifies the signal charge and outputs it as a pixel signal. In addition, the solid-state imaging device has a drive mode in which signal charges are thinned out and read out from the pixels of the first and second color series arranged in the vertical direction and added in the vertical CCD for each color series.

  As shown in FIG. 5A, a photodiode is disposed in each pixel. In FIG. 5A, PD10 to PD16 are pixels to be added (pixels to be read) and are arranged not to be adjacent to each other. Among these photodiodes, PD10 to P12 correspond to pixels of the first color series, and PD13 to P16 correspond to pixels of the second color series.

  In addition, two types of gates, a read / transfer gate and a transfer gate, are arranged in each photodiode. In FIG. 5A, 12 types of gates corresponding to φV1, φV3, φV5, φV7, φV9, φV1A, φV1C, φV3A, φV3C, φV5C, φV7A, φV9C are read and transfer gates, and φV2, φV4, φV6 , Φ8, and φ10 correspond to the transfer gates.

  The vertical CCD of the solid-state imaging device in the third embodiment is 10-phase drive, and the readout and transfer gates corresponding to φV1A, φV1C, φV3A, φV3C, φV5C, φV7A, and φV9C can be driven independently of other systems. It has become. Gates corresponding to φV3A, φV7A, and φV1A are provided in the first color series PD10 to P12, and gates corresponding to φV1C, φV5C, φV9C, and φV3C are provided in the second color series PD13 to P16. Is provided. In the configuration shown in FIG. 5A, vertical pixel addition and vertical thinning readout can be performed using 20 pixels as a repeating unit.

  As shown in FIG. 5B, also in the third embodiment, the pixel centroid of the first color series and the pixel centroid of the second color series are equal, as in the first and second embodiments. The addition target pixels PD10 to PD16 are arranged so as to line up.

  In the vertical CCD, in the driving mode of vertical pixel addition and vertical thinning-out reading operation, the vertical CCD receives signal charges from the same color series PD10 to PD12 and other same color series PD13 to PD16 in the vertical CCD, respectively. After the addition, the addition signals of PD10 to PD12 and the addition signals of PD13 to PD16 are moved from the top to the bottom of the drawing. As described above, the vertical CCD employs a so-called vertical 1/10 thinning driving method in which two signals are output from signals of 20 pixels arranged vertically.

  FIG. 6 shows a timing chart at the time of pixel addition and thinning readout operations of the solid-state imaging device according to the third embodiment. For example, at time T3, an intermediate voltage (VM level voltage) is applied to the gates corresponding to φV1 to φV7, which is a signal charge accumulation region. Further, a low voltage (low level voltage) is applied to the gates corresponding to the remaining φV8 to φV10 to form a barrier region. In this state, for example, after applying a high voltage (high level voltage) to the gate corresponding to φV1C and reading the signal charge of the PD13 which is the second color series, the gates in the order of φV8, φV1, φV9, φV2 The storage region is moved by controlling the voltage level applied to the gate, and the signal charge is moved using the gate corresponding to φV3 to φV9 as the storage region and the gates corresponding to φV10, φV1, and φV2 as the barrier region. By repeating this procedure, the thinning readout operation and the movement control of the accumulation area are performed, and the addition target pixel is read out and pixel addition is performed in the order of PD10 to PD16 from time T1 to time T6.

  That is, as shown in FIG. 6, a high voltage (high level voltage) is applied to the gate corresponding to φV3A at time T1, and the signal charges of the first color series are read out from the PD10. Next, at time T2, a high voltage (high level voltage) is applied to the gate corresponding to φV7A, and the signal charges of the first color series are read out from the PD11. Next, at time T3, a high voltage (high level voltage) is applied to the gates corresponding to φV1A and φV1C, and the signal charges of the first color series and the second color series are read from PD12. Next, at time T <b> 4, a high voltage (high level voltage) is applied to the gate corresponding to φV <b> 5 </ b> C, and the signal charges of the second color series are read from the PD 14. Next, at time T <b> 5, a high voltage (high level voltage) is applied to the gate corresponding to φV <b> 9 </ b> C, and the signal charges of the second color series are read from the PD 15. Next, at time T <b> 6, a high voltage (high level voltage) is applied to the gate corresponding to φV <b> 3 </ b> C, and the signal charges of the second color series are read from the PD 16.

  The signal charge from the PD 10 is read out under the gate corresponding to φV3A, then transferred in the vertical CCD from φV4 → φV5 → φV6, and then read out under the gate corresponding to φV7A. It is added to the charge. Thereafter, after being transferred in the vertical CCD in the order of φV8 → φV9 → φV10, the signal charge from the PD 12 read out under the gate corresponding to φV1A is added, and further transferred in the vertical CCD. Similarly, the signal charge from the PD 13 is read under the gate corresponding to φV1C, then transferred in the vertical CCD from φV2 → φV3 → φV4, and then read out under the gate corresponding to φV5C. Is added to the signal charge from. Then, after being transferred in the vertical CCD as φV6 → φV7 → φV8, the signal charge from the PD 15 read out under the gate corresponding to φV9C is added. Thereafter, after being transferred in the vertical CCD in the order of φV10 → φV1 → φV2, the signal charge from the PD 16 read out under the gate corresponding to φV3C is added and further transferred in the vertical CCD.

  As described above, with the gate configuration shown in FIG. 5, the vertical CCD receives the signal charges of the first color series three times in the first, second, and third readouts, the fourth, the fifth, and the sixth. In the seventh and seventh readings, the signal charges of the second color series are read four times, for a total of seven reading operations.

  By performing the pixel addition and decimation readout operation at the above timing, the average exposure time (PD10 + PD11 + PD12) of the first color series is shortened and the average exposure time (PD13 + PD14 + PD15 + PD16) of the second color series is lengthened as shown in FIG. The sensitivity of the second color series can be improved more than the sensitivity of the first color series. Further, a high frame rate can be realized by thinning readout in the vertical direction and pixel addition.

  According to the third embodiment, the signal amount of the second color series can be made larger than the signal amount of the first color series, and the exposure time can be adjusted, so that the relative sensitivity can be adjusted. Become. Since the setting of the color sensitivity of the photodiode varies depending on the manufacturing process or the like, for example, when a photodiode set to have a low R sensitivity among RGB is used, the signal amount is relatively set as described above. By increasing the color reproducibility, the color reproducibility can be improved.

  Also in the third embodiment, if the pixel that actually reads the signal charge can be selected from the addition target pixels, the pixel addition ratio can be freely switched while changing the average exposure time of each color series. Can do. For example, if signal charges are not read out from PD11, PD13, and PD16 among PD10 to PD16, the addition signal of PD10 and PD12, which is the first color series, and PD14, which is the second color series, The output of the addition signal of PD15 can be obtained. Further, if signal charges are not read out from PD14, PD12, and PD16, output signals of the first color series PD10 and PD11 and the second color series PD13 and PD15 are output. Can be obtained.

  Further, according to the third embodiment, since the addition target pixels are arranged so as not to be adjacent to each other, the influence of the potential of the adjacent photodiode can be removed, and even if the output level of the photodiode becomes the Knee region. It can be used and a wide dynamic range can be realized.

  In the first to third embodiments, the description has been given by taking the 6-phase drive vertical CCD and the 10-phase drive vertical CCD as examples. However, the present invention is not limited to this, and can be driven independently during the thinning readout operation. The present invention can be applied to a solid-state imaging device including a multi-phase driven vertical CCD having four or more types of gates.

  In the first to third embodiments, the Bayer array of the primary color filter array has been described as an example. However, a complementary color filter array may be used.

  According to the solid-state imaging device and the driving method thereof according to the present invention, it is possible to improve the sensitivity of pixels of a specific color series with a difference in exposure time. It is preferable to apply to an apparatus.

Schematic diagram for explaining the configuration of the solid-state imaging device according to Embodiment 1 of the present invention. The figure which shows the timing chart at the time of the pixel addition of the solid-state image sensor in Embodiment 1 of this invention, and a thinning-out read-out operation | movement. Schematic diagram for explaining the configuration of the solid-state imaging device according to the second embodiment of the present invention. The figure which shows the timing chart at the time of pixel addition of the solid-state image sensor in Embodiment 2 of this invention, and a thinning-out read-out operation | movement. Schematic diagram for explaining the configuration of the solid-state imaging device according to Embodiment 3 of the present invention. The figure which shows the timing chart at the time of pixel addition of the solid-state image sensor in Embodiment 3 of this invention, and a thinning-out read-out operation | movement. Schematic diagram of CCD as a general solid-state image sensor The figure which shows an example of the conventional pixel addition of the vertical direction The figure which shows the relationship between general shutter timing and signal charge read-out timing

Explanation of symbols

700 Photodiode 701 Vertical CCD
702 Horizontal CCD
703 Amplifier 704 Gate

Claims (6)

A plurality of pixels each having a photoelectric conversion unit and arranged in a matrix, and a color filter in which a first color series and a second color series arranged on the pixels are alternately arranged in the column direction; The first CCD and the vertical CCD for reading and transferring the signal charges accumulated in the photoelectric conversion unit and a horizontal CCD for transferring the signal charges transferred from the vertical CCD to the amplification unit and arranged in the vertical direction A solid-state imaging device having a driving mode in which signal charges are thinned out and read out from each pixel of the second color series and added in the vertical CCD for each color series,
Pixels to be read from which signal charges are read out in the drive mode are arranged so that pixel centroids for each color series after addition are evenly arranged in the vertical direction, and the vertical CCD is a gate for reading out signal charges in the drive mode. As for having four or more types of gates that can be driven independently of other systems,
A solid-state imaging device.   Two or more pixels to be read out of each of the first and second color series are arranged for each predetermined number of pixels as a repeating unit, and signal charges are added for each repeating unit. 4. The solid-state image pickup device according to claim 1, further comprising four or more types of gates that can be driven independently of other systems.   The solid-state imaging device according to claim 1, wherein the pixels to be read are arranged so as not to be adjacent to each other.   4. The solid-state imaging device according to claim 1, wherein the number of pixels to be read is different between the first and second color series. 5.   5. The driving method of a solid-state imaging device according to claim 1, wherein in the driving mode, the signal charge is set so that a time from the start of exposure to reading of the signal charge is different for each pixel to be read. A method for driving a solid-state imaging device, wherein reading is performed so that an average exposure time differs between pixels to be read out of the first and second color series. 6. The method of driving a solid-state imaging device according to claim 5, wherein a pixel from which signal charges are read is selected from pixels to be read out of at least one of the first or second color series.

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