JP2007266986A - Television receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To exactly switch antennas. <P>SOLUTION: A high frequency television signal is captured by each of antennas 12a and 12b. A selector 14 selects either one of the antennas 12a and 12b. An interleave circuit 28 creates image data of a plurality of fields based on the received high frequency television signal. A write control circuit 30 intermittently writes the created image data in a buffer memory 32 in terms of fields. The read control circuit 34 reads the image data stored in the buffer memory 32 between an interval of the writing operation by the write control circuit 34. An LCD driver 36 displays the image based on the image data read from the buffer memory 32 on an LCD monitor 38 between an interval of writing operation. A CPU 22 demands the selector 14 to switch antennas between an interval of the writing operation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a television receiver, and more particularly to a television receiver that displays, on a monitor, an image based on, for example, a high-frequency television signal captured by any one of a plurality of antennas.

An example of a conventional device of this type is disclosed in Patent Document 1. This prior art is intended to execute a video diversity operation for selecting an antenna having a maximum video electric field level among a plurality of antennas during a vertical blanking period of a video signal. Thereby, it is possible to prevent the video from being out of synchronization.
JP 7-322156 A [H04N 5/44, H04B 7/08]

    However, the conventional technique has a problem that the antenna cannot be switched accurately because the period in which the video diversity operation can be performed is limited to the vertical blanking period.

    Therefore, a main object of the present invention is to provide a television receiver capable of switching antennas accurately.

  The television receiver (10) according to the invention of claim 1 is selected by the selecting means (14) and the selecting means for selecting any one of the plurality of antennas (12a, 12b) each capturing a high-frequency television signal. Creation means (16, 18, 20, 26, 28) for creating video data for multiple screens based on high-frequency television signals captured by the antenna, and the video data created by the creation means is intermittently displayed in screen units. Extraction means (30) for extraction, display means (36) for displaying video based on the video data extracted by the extraction means on the video monitor (38), and switching of the antenna to the selection means between extraction operations by the extraction means Requesting means (S47, S49) for requesting is provided.

  A high frequency television signal is captured by each of the plurality of antennas. The selection means selects any one of the plurality of antennas. The video data of a plurality of screens is created by the creating means based on the high frequency television signal captured by the selected antenna. The extraction means intermittently extracts the created video data for each screen. The video based on the extracted video data is displayed on the video monitor by the display means. The requesting unit requests the selection unit to switch the antenna between extraction operations by the extracting unit.

  By extracting video data intermittently in units of screens, a period corresponding to at least one screen is ensured between extraction operations. Switching between antennas is required between such intervals, thereby switching antennas. By securing a period corresponding to at least one screen, the antenna can be switched accurately.

  A television receiver according to the invention of claim 2 is dependent on claim 1, and the requesting means specifies a switching destination antenna by paying attention to reception sensitivity information of each of the plurality of antennas (S47), and Issue means (S49) for issuing a request signal for requesting switching to the antenna specified by the specifying means. As a result, the quality of the displayed video is improved.

  The television receiver according to the invention of claim 3 is dependent on claim 2, wherein the creating means includes conversion means (18) for converting the high-frequency television signal into an intermediate frequency signal, and the reception sensitivity information is converted by the conversion means. Control voltage for controlling the gain of the intermediate frequency signal. As a result, the antenna to be switched to is selected based on the gain of the intermediate frequency signal.

  The television receiver according to the invention of claim 4 is according to claim 2 or 3, further comprising an activation means (S37) for activating the request means when the gain of the high-frequency television signal meets an error condition. Prepare. Therefore, antenna switching control is enabled / disabled based on the gain of the high frequency television signal. As a result, unnecessary antenna switching control is omitted, and power consumption is reduced.

  A television receiver according to the invention of claim 5 is dependent on any one of claims 1 to 4, wherein the odd-numbered field screen and the even-numbered field screen in which the video data of the plurality of screens created by the creation means are subjected to interlace scanning. The extraction means performs the extraction operation in one of the odd field period and the even field period.

  A television receiver according to the invention of claim 6 is dependent on claim 5 and comprises a memory (32) for storing the video data extracted by the extracting means, and the video data stored in the memory for the odd field period and the even field. It further comprises reading means (34) for reading out the other of the periods, and the display means displays a video based on the video data read by the reading means.

  That is, the video data is intermittently written to the memory in units of screens, while the video data stored in the memory is read between write operations. Thus, the quality of the video data written in the memory, that is, the quality of the displayed video is not deteriorated by the high frequency noise generated due to the display operation of the display means. As a result, the quality of the displayed video is improved.

  A television receiver according to a seventh aspect of the invention is dependent on any one of the first to sixth aspects, and the vertical resolution of the video monitor is equal to or lower than the vertical resolution of the video data of each screen created by the creation means. As a result, it is possible to prevent the display video update cycle from being lowered due to the intermittent writing operation.

  The television receiver according to the invention of claim 8 is dependent on claim 7, and the creating means includes a reducing means for reducing the resolution of the video data extracted by the extracting means. By reducing the resolution prior to extraction, the amount of processing data can be suppressed.

  According to the present invention, video data is intermittently extracted in units of screens, so that a period corresponding to at least one screen is ensured between extraction operations. Switching between antennas is required between such intervals, thereby switching antennas. By securing a period corresponding to at least one screen, the antenna can be switched accurately.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, portable television receiver 10 of this embodiment includes a plurality of antennas 12a and 12b. A plurality of high-frequency television signals transmitted from a plurality of broadcasting stations are captured by each of the antennas 12a and 12b. The selector 14 selects one of the antennas 12a and 12b, and the tuner 16 extracts a high-frequency television signal of a desired channel from a plurality of high-frequency television signals captured by the antenna selected by the selector 14. To do.

  A high-frequency television signal to be broadcast is a signal subjected to amplitude modulation. The VIF / SIF circuit 18 inputs such a high-frequency television signal from the tuner 16 and converts the input high-frequency television signal into a video intermediate frequency signal and an audio intermediate frequency signal. The converted video intermediate frequency signal and audio intermediate frequency signal are applied to an NTSC decoder 20 and an audio processing circuit (not shown), respectively.

  The NTSC decoder 20 decodes the supplied video intermediate frequency signal to generate an NTSC composite video signal. As shown in FIG. 2A, the generated composite video signal includes a plurality of interlace-scanned video signals and a plurality of vertical synchronizing signals Vsync inserted at a rate of one per field. The video signal of each field is given to the A / D converter 26 every 1/60 seconds, and the vertical synchronization signal Vsync is given to the CPU 22 every 1/60 seconds.

  The A / D converter 26 converts the supplied video signal into video data that is a digital signal. The vertical resolution of the LCD monitor 38 is equal to or lower than the vertical resolution of the video data of each field output from the A / D converter 26. The thinning circuit 28 reduces the resolution of the converted video data and supplies the video data having the reduced resolution to the write control circuit 30. The resolution reduced by the processing of the thinning circuit 28 matches the resolution of the LCD monitor 38.

  The CPU 22 gives a write command to the write control circuit 30 at a rate of once every two fields based on the vertical synchronization signal Vsync. The write control circuit 30 writes the video data belonging to the field at the time of receiving the write command to the buffer memory 32 via the bus B1. Thereby, for example, the video data of the odd field shown in FIG. 2B is stored in the buffer memory 32.

  The CPU 22 also applies a read command and a display command to the read control circuit 34 and the LCD driver 36 at a rate of once every two fields. However, each of the read command and the display command is issued at a timing complementary to the issue timing of the write command. That is, when the write command is issued in one of the odd field and the even field, each of the read command and the display command is issued in the other of the odd field and the even field.

  The read control circuit 34 reads one field of video data stored in the buffer memory 32 every time a read command is issued. The video data of each field is read from the buffer memory 32 in the manner shown in FIG. 2C, and is given to the LCD driver 36 via the bus B1 and the read control circuit 34. When the LCD driver 36 receives the display command, the LCD driver 36 drives the LCD monitor 38 over one field period in accordance with the video data supplied from the read control circuit 34. As a result, the image displayed on the monitor screen is updated every 1/30 seconds as shown in FIG.

  The VIF / SIF circuit 18 converts the RF_AGC voltage for adjusting the gain of the high frequency television signal to the target value and the gain of the video intermediate frequency signal, in addition to converting the high frequency television signal into the video intermediate frequency signal and the audio intermediate frequency signal. An IF_AGC voltage for adjusting to the target value is created. The generated RF_AGC voltage and IF_AGC voltage are both supplied to the CPU 22.

  The RF_AGC voltage changes in the manner shown in FIG. Further, the IF_AGC voltage changes in the manner shown in FIG. 3B with respect to the electric field strength. Looking in the direction in which the electric field strength decreases, the RF_AGC voltage rises in a pulse shape when the electric field strength falls below the delay point DP, whereas the IF_AGC voltage gradually rises after the electric field strength falls below the delay point DP. . Accordingly, when the RF_AGC voltage is equal to or lower than the threshold value TH corresponding to the delay point DP, it can be determined that the reception sensitivity of the currently selected antenna is good.

  As shown in FIG. 2E, the CPU 22 sets the even field period as the antenna switching period, and takes in the RF_AGC voltage from the VIF / SIF circuit 18 during this period. The captured RF_AGC voltage is compared with a threshold value TH. If the RF_AGC voltage exceeds the threshold value TH, the CPU 22 considers that the reception sensitivity of the currently selected antenna is poor, and executes the following diversity operation.

  First, the CPU 22 requests the selector 14 to select the antenna 12a, and takes in the IF_AGC voltage suitable for the video intermediate frequency signal based on the high-frequency television signal captured by the antenna 12a from the VIF / SIF circuit 18. The CPU 22 also requests the selector 14 to select the antenna 12 b and takes in the IF_AGC voltage suitable for the video intermediate frequency signal based on the high-frequency television signal captured by the antenna 12 b from the VIF / SIF circuit 18.

  The CPU 22 specifies an IF_AGC voltage having a smaller voltage value from the two IF_AGC voltages thus taken, and requests the selector 14 to select an antenna corresponding to the specified IF_AGC voltage. As a result, an antenna with good reception sensitivity is selected, and the quality of the image displayed on the LCD monitor 38 is improved.

  The CPU 22 executes in parallel a plurality of tasks including the capture control task shown in FIG. 4, the display control task shown in FIG. 5, and the antenna control task shown in FIG. Note that control programs corresponding to these tasks are stored in the flash memory 24.

  Referring to FIG. 4, in step S1, a write flag Fw is set. In step S3, it is determined whether or not the vertical synchronization signal Vsync has been generated. In step S5, it is determined whether or not the write flag Fw is set. If the vertical synchronization signal Vsync is generated when the write flag Fw is set, YES is determined in each of steps S3 and S5, and a write command is issued to the write control circuit 30 in step S7.

  One field of video data provided from the thinning circuit 28 is written into the buffer memory 32 by the write control circuit 30. In subsequent step S9, the write flag Fw is reset, and then the process returns to step S3.

  If the vertical synchronization signal Vsync is generated when the write flag Fw is in the reset state, YES is determined in step S3, while NO is determined in step S5, and the write flag Fw is set in step S11. When the process of step S11 is completed, the process returns to step S3.

  Therefore, the write flag Fw is set every two fields, and the video data of each field is written into the buffer memory 32 once every two fields.

  Referring to FIG. 5, in step S21, it is determined whether or not the vertical synchronization signal Vsync has been generated. In step S23, it is determined whether or not the write flag Fw is in a reset state. If the vertical synchronization signal Vsync is generated when the write flag Fw is set, YES is determined in step S21, NO is determined in step S23, and the process returns to step S21.

  If the vertical synchronization signal Vsync is generated when the write flag Fw is in the reset state, YES is determined in each of steps S21 and S23, and the process proceeds to step S25. In step S25, a read command is issued to the read control circuit 34, and in step S27, a display command is issued to the LCD driver 36.

  One field of video data stored in the buffer memory 32 is read by the read control circuit 34. The LCD driver 36 drives the LCD monitor 38 over one field period based on the read video data. As a result, one field of video is displayed on the monitor screen. When the process of step S27 is completed, the process returns to step S21.

  Referring to FIG. 6, in step S31, it is determined whether or not the vertical synchronization signal Vsync has been generated. In step S33, it is determined whether or not the write flag Fw is in a reset state. If the vertical synchronization signal Vsync is generated when the write flag Fw is set, YES is determined in step S31, NO is determined in step S33, and the process returns to step S31. If the vertical synchronization signal Vsync is generated when the write flag Fw is in the reset state, YES is determined in each of steps S31 and S33, and the process proceeds to step S35.

  In step S35, the RF_AGC voltage is taken from the VIF / SIF circuit 18. In a succeeding step S37, it is determined whether or not the captured RF_AGC voltage exceeds the threshold value TH (whether or not the RF_AGC voltage matches an error condition). If the RF_AGC voltage is equal to or lower than the threshold value TH, it is assumed that the reception sensitivity of the currently selected antenna is good, and the process returns to step S31 as it is. On the other hand, if the RF_AGC voltage exceeds the threshold value, the reception sensitivity of the currently selected antenna is regarded as poor, and steps S39 to S49 are executed to select an antenna with better reception sensitivity.

  First, in step S39, the selector 14 is requested to select the antenna 12a. As a result, the high-frequency television signal captured by the antenna 12 a is given to the tuner 16 via the selector 14. In step S41, the IF_AGC voltage is taken from the VIF / SIF circuit. The captured IF_AGC voltage is a voltage for setting the gain of the video intermediate frequency signal corresponding to the high-frequency television signal captured by the antenna 12a to a target value (default value).

  In step S43, the selector 14 is requested to select the antenna 12b. As a result, the high-frequency television signal captured by the antenna 12 b is given to the tuner 16 via the selector 14. In step S45, the IF_AGC voltage is taken from the VIF / SIF circuit. The captured IF_AGC voltage is a voltage for setting the gain of the video intermediate frequency signal corresponding to the high-frequency television signal captured by the antenna 12b to a target value (default value).

  In step S47, the IF_AGC voltage having the smaller voltage value among the two IF_AGC voltages fetched in steps S41 and S45 is specified. In step S49, the selector 14 is requested to select an antenna corresponding to the specified IF_AGC voltage. When the process of step S49 is completed, the process returns to step S31.

  As can be seen from the above description, the high-frequency television signal is captured by each of the antennas 12a and 12b. The selector 14 selects one of the antennas 12a and 12b. The thinning circuit 28 creates video data of a plurality of fields (a plurality of screens) based on the received high frequency television signal. The created video data is intermittently written to the buffer memory 32 by the write control circuit 30 in units of fields. The read control circuit 34 reads the video data stored in the buffer memory 32 between write operations (extraction operations) by the write control circuit 34. The LCD driver 36 displays an image based on the image data read from the buffer memory 32 on the LCD monitor 38 between extraction operations. Further, the CPU 22 requests the selector 14 to switch the antenna between extraction operations (S49).

  By intermittently extracting the video data in field units, a period corresponding to at least one field is ensured between extraction operations. Antenna switching is required between such intervals, thereby switching the antenna. By securing a period corresponding to at least one field, the antenna can be switched accurately.

  The video data is intermittently written to the buffer memory 32 in field units, while the video data stored in the buffer memory 32 is read between write operations. Thus, the quality of the video data written to the buffer memory 32, that is, the quality of the displayed video is not deteriorated by the high frequency noise generated due to the display operation of the LCD driver 36. As a result, the quality of the displayed video is improved.

  Further, the vertical resolution of the LCD monitor 38 is lower than the vertical resolution of the video data of each field output from the A / D converter 26. As a result, it is possible to prevent the display video update cycle from being lowered due to the intermittent writing operation. Further, the thinning circuit 28 is provided in the previous stage of the write control circuit 30. Thereby, the capacity of the buffer memory 32 can be suppressed.

  In this embodiment, the write operation to the buffer memory 32 and the display operation of the LCD monitor 38 are executed every 1/30 seconds. However, these operation cycles are N minutes of 1/30 seconds. 1 (N: an integer of 2 or more) may be used.

  As long as the antenna switching operation is performed between write operations, the write operation may be irregular.

It is a block diagram which shows the structure of one Example of this invention. (A) is a timing diagram showing a part of the video receiving operation, (B) is a timing diagram showing a part of the video writing operation to the memory, and (C) is a part of the video reading operation from the memory. (D) is a timing diagram showing a part of the video display operation on the LCD monitor, and (E) is a timing diagram showing a part of the diversity operation. (A) is a graph which shows an example of the relationship between electric field strength and RF_AGC voltage, (B) is a graph which shows an example of the relationship between electric field strength and IF_AGC voltage. It is a flowchart which shows a part of operation | movement of CPU. It is a flowchart which shows another part of operation | movement of CPU. It is a flowchart which shows a part of other operation | movement of CPU.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Television receiver 12a, 12b ... Antenna 14 ... Selector 16 ... Tuner 18 ... VIF / SIF circuit 20 ... NTSC decoder 22 ... CPU
30 ... Write control circuit 32 ... Buffer memory 34 ... Read control circuit 36 ... LCD driver 38 ... LCD monitor

Claims (8)

Selecting means for selecting any one of a plurality of antennas each capturing a high-frequency television signal;
Creating means for creating video data of a plurality of screens based on a high-frequency television signal captured by an antenna selected by the selecting means;
Extraction means for intermittently extracting video data created by the creation means in units of screens;
A television receiver comprising: display means for displaying video based on the video data extracted by the extraction means on a video monitor; and request means for requesting the selection means to switch antennas between extraction operations by the extraction means .   The request unit is configured to specify a switching destination antenna by paying attention to reception sensitivity information of each of the plurality of antennas, and to issue a request signal for requesting switching to the antenna specified by the specifying unit. The television receiver of claim 1 including means. The creating means includes conversion means for converting the high-frequency television signal into an intermediate frequency signal,
3. The television receiver according to claim 2, wherein the reception sensitivity information includes a control voltage for controlling a gain of the intermediate frequency signal converted by the conversion means.   4. The television receiver according to claim 1, further comprising an activating unit that activates the request unit when a gain of the high-frequency television signal meets an error condition. The image data of a plurality of screens created by the creating means is formed by an odd field screen and an even field screen subjected to interlace scanning,
5. The television receiver according to claim 1, wherein the extraction unit performs an extraction operation in one of an odd field period and an even field period. 6. A memory for storing the video data extracted by the extraction means; and a reading means for reading the video data stored in the memory in the other of the odd field period and the even field period,
6. The television receiver according to claim 5, wherein the display means displays a video based on the video data read by the reading means.   The television receiver according to claim 1, wherein a vertical resolution of the video monitor is equal to or less than a vertical resolution of video data of each screen created by the creation unit.   8. The television receiver according to claim 7, wherein the creating means includes a reducing means for reducing the resolution of the video data extracted by the extracting means.

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