JP2007266407A - Non-volatile memory and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile memory that suppresses the leakage current of a ferroelectric substance and can be used stably, and to provide a method of manufacturing the non-volatile memory. <P>SOLUTION: The memory cell of the non-volatile memory 1 comprises: a cell selection transistor 5, and a ferroelectric capacitor 2 connected to the cell selection transistor 5 electrically. The ferroelectric capacitor 2 comprises: a lower electrode 15; a ferroelectric film 17 that is formed on the lower electrode 15, and contains a magnetic element; and an upper electrode 19 formed on the ferroelectric film 17. The non-volatile memory 1 is formed by applying a magnetic field of 10 kOe in a direction vertical to the surface of the ferroelectric film 17 and heating to 400°C. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory and a manufacturing method thereof.

Nonvolatile memory (FeRAM) using a ferroelectric material having spontaneous polarization in the capacitor portion is expected to be applied to a non-contact IC card or the like as a next-generation memory. The ferroelectric capacitor material currently used is a perovskite oxide Pb (Zr, Ti) O ₃ system. The amount of spontaneous polarization Pr of the perovskite oxide Pb (Zr, Ti) O ₃ system is about 50 μC / cm ² . When the amount of spontaneous polarization is twice or more, a higher-density nonvolatile memory can be manufactured.

In recent years, a result showing a huge amount of spontaneous polarization in a perovskite oxide containing a magnetic element has been reported. For example, Non-Patent Document 1 reports that the amount of spontaneous polarization Pr of a bismuth iron oxide (BiFeO ₃ ) thin film exhibits a value of 100 to 150 μC / cm ² . There is also progress in the theoretical calculation of ferroelectricity, and ferroelectricity is calculated from the electronic structure. For example, Non-Patent Document 2 predicts that the spontaneous polarization amount Pr of BiCoO ₃ is 179 μC / cm ² . Although it has been thought that materials containing magnetic elements do not have a positive effect on ferroelectricity, it has been found that they can play an important role.
K. Y. YUNet. al. , Jpn. J. et al. Appl. Phys. , Vol. 43, no. 5A (2004) Y. Uratani, et. al. , Japan Journal of Applied Physics, Vol. 44, no. 9B, 2005, pp. 7130-7133

  However, since a ferroelectric material containing a magnetic element has a large leakage current, it has been difficult to actually incorporate it into a device.

  An object of the present invention is to provide a nonvolatile memory that can suppress the leakage current of a ferroelectric and can be used stably, and a method for manufacturing the same.

  The object is to provide a first electrode formed on a semiconductor substrate, a ferroelectric film formed on the first electrode and containing a magnetic element, and a second electrode formed on the ferroelectric film. This is achieved by a non-volatile memory having a ferroelectric capacitor including an electrode and a magnetic field applying unit that applies a magnetic field to the ferroelectric film.

  Also, the object is to form a ferroelectric film containing a magnetic element formed on a semiconductor substrate, a gate electrode formed on the ferroelectric film, and a channel at the interface of the semiconductor substrate below the ferroelectric film. This is achieved by a non-volatile memory having source / drain regions formed on both sides of the region and a magnetic field applying unit for applying a magnetic field to the ferroelectric film.

  Also, the object is to form a first electrode on a substrate, form a ferroelectric film containing a magnetic element on the first electrode, and form a second electrode on the ferroelectric film. A ferroelectric capacitor is formed, and a magnetic field or a magnetic field and an electric field are applied to the ferroelectric film and heated, and the ferroelectric film is cooled. .

  Further, the object is to form a ferroelectric film containing a magnetic element on a semiconductor substrate, to form a gate electrode on the ferroelectric film, and to form a channel region at the interface of the semiconductor substrate below the ferroelectric film. According to a non-volatile memory manufacturing method, source / drain regions are formed on both sides sandwiched, a magnetic field or a magnetic field and an electric field are applied to the ferroelectric film and heated, and the ferroelectric film is cooled. Achieved.

  According to the present invention, it is possible to realize a nonvolatile memory that can suppress the leakage current of the ferroelectric and can be used stably.

  The first to fourth embodiments described below are examples of the present invention and do not limit the scope of the present invention. It goes without saying that other embodiments may belong to the category of the present invention as long as they match the gist of the present invention.

[First Embodiment]
A nonvolatile memory and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS. First, a ferroelectric material containing a magnetic element will be described with reference to FIG. FIG. 1 shows the crystal structure of BiFeO ₃ as a ferroelectric material containing a magnetic element. As shown in FIG. 1, BiFeO ₃ has a simple perovskite structure represented by ABO ₃ . Bi corresponds to the A site and Fe corresponds to the B site. A combination of Bi ³⁺ and Fe ³⁺ is standard. When at least one of Bi ³⁺ and Fe ^{3+ has} a valence other than plus trivalent, lattice defects increase in the crystal and leakage current tends to increase. In particular, the valence of the B site is likely to fluctuate. Furthermore, bismuth oxide has a low melting point of 817 ° C. and is easily evaporated by heating. For this reason, Bi is easily lost from the site of the perovskite structure during the crystallization process. When the amount of Bi loss increases, a heterogeneous phase having no ferroelectricity is generated and the leakage current increases. The formation method of the BiFeO ₃ is not particularly limited, but MOCVD method, pulse laser deposition method (PLD method), chemical solution deposition method (CSD method) and the like are preferable.

Such a capacitive element using BiFeO ₃ as a dielectric can be used as a part of FeRAM, for example. The FeRAM can be suitably used for an integrated circuit in which an active element such as a transistor, a passive element such as a resistor and a capacitor, and a multilayer wiring are combined. FeRAM can be suitably used for electronic devices such as personal computers, smart cards, security cards, RFIC tags, mobile phones, and PDAs.

  Next, a schematic configuration of the nonvolatile memory 1 according to the present embodiment will be described with reference to FIG. FIG. 2 shows a cross-sectional structure perpendicular to the substrate surface of one memory cell in the memory cell array formed in an array of the nonvolatile memory 1 of the present embodiment. As shown in FIG. 2, the memory cell of the nonvolatile memory 1 is formed in an element region defined by an element isolation insulating film 7 formed on, for example, an n-type silicon semiconductor substrate 3. The memory cell of the nonvolatile memory 1 has a cell selection transistor 5 and a ferroelectric capacitor 2 electrically connected to the cell selection transistor 5. The memory cell of the nonvolatile memory 1 has a 1-transistor 1-capacitor (1T1C) type structure.

The cell selection transistor 5 includes a gate insulating film 4 formed on the semiconductor substrate 3 and a gate electrode G made of, for example, a polysilicon film formed on the gate insulating film 4. The gate electrode G is connected to a word line (not shown) to which a cell selection signal used for selecting a memory cell is input. The cell selection transistor 5 has a source region S and a drain region D of a p-type impurity diffusion layer formed on both sides of a channel region formed in the semiconductor substrate 3 under the gate insulating film 4. An interlayer insulating film 9 made of, for example, silicon dioxide (SiO ₂ ) is formed on the entire surface of the semiconductor substrate 3. The surface of the interlayer insulating film 9 is flattened. The interlayer insulating film 9 in the upper layer portion of the source region S of the cell selection transistor 5 is opened to form a contact hole. For example, tungsten is buried in the contact hole to form a tungsten plug 11. The drain region D is connected to a bit line (not shown) to which a voltage corresponding to data written to the memory cell is applied.

On the silicon oxide film 13 formed on the interlayer insulating film 9 on the element isolation insulating film 7 side, the ferroelectric capacitor 2 is formed. The ferroelectric capacitor 2 includes a lower electrode (first electrode) 15 connected to a plate line (not shown), a ferroelectric film 17 formed on the lower electrode 15 and containing a magnetic element, and a ferroelectric material. And an upper electrode (second electrode) 19 formed on the film 17. The ferroelectric film 17 is made of, for example, a BiFeO ₃ material.

The material for forming the ferroelectric film 17 is not limited to BiFeO ₃ and may be any ferroelectric material containing a magnetic element. The material for forming the ferroelectric film 17 is, for example, a perovskite material having a crystal lattice with a composition formula of ABO ₃ , and the A site of the crystal lattice includes Pb ions or Bi ions and at least one rare earth cation, The B site may be a cation and contain a magnetic ion. Furthermore, the magnetic ions are preferably V ions, Cr ions, Mn ions, Fe ions, Co ions, Ni ions, or Cu ions.

  An insulating film 21 made of silicon oxide is formed so as to cover the ferroelectric capacitor 2. A contact hole CH that exposes a part of the surface of the upper electrode 19 is formed in the insulating film 21. On the insulating film 21, a wiring 23 is formed which is buried in the contact hole CH and extends to the cell selection transistor 5 side. The wiring 23 electrically connects the upper electrode 19 exposed in the contact hole CH and the tungsten plug 11 exposed on the surface of the interlayer insulating film 9.

  As will be described later, the nonvolatile memory 1 is formed by applying a magnetic field of 10 kOe in the surface vertical direction (film thickness direction) of the ferroelectric film 17 and heating to 400 ° C. Thereby, since the leakage current of the ferroelectric film 17 is suppressed, the retention characteristics and the imprint characteristics of the nonvolatile memory 1 are improved, and the nonvolatile memory 1 can be used stably. become.

  Next, the data write / read operation of the nonvolatile memory 1 according to the present embodiment will be briefly described with reference to FIG. First, the data write operation of the nonvolatile memory 1 according to this embodiment will be described. For example, a voltage of -Vg (V) is applied to the gate electrode G of the cell selection transistor 5 through the word line to select a memory cell in which data is written. Next, when data “1” is written, for example, the voltage is applied to each wiring so that the voltage Vb of the bit line is higher than the voltage Vp of the plate line. Thereby, a voltage having a higher potential is applied to the ferroelectric film 17 on the upper electrode 19 side than on the lower electrode 15 side. Therefore, the ferroelectric film 17 is polarized in the direction from the upper electrode 19 to the lower electrode 15. The polarization direction is associated with “1”.

  On the other hand, when data “0” is written, a voltage is applied to each wiring so that the voltage Vb of the bit line is lower than the voltage Vp of the plate line, for example. As a result, a voltage having a lower potential is applied to the ferroelectric film 17 on the upper electrode 19 side than on the lower electrode 15 side. Therefore, the ferroelectric film 17 is polarized in the direction from the lower electrode 15 to the upper electrode 19. The polarization direction is associated with “0”. Thus, the nonvolatile memory 1 can write “1” or “0” data by associating the data to be written with the polarization direction of the ferroelectric film 17.

  Next, the data read operation of the nonvolatile memory 1 according to this embodiment will be described. First, a memory cell from which data is read is selected by applying a voltage of, for example, -Vg (V) to the gate electrode G of the cell selection transistor 5 through the word line. Next, for example, a voltage is applied to each wiring so that the voltage Vb of the bit line is higher than the voltage Vp of the plate line. As a result, a voltage having a higher potential is applied to the upper electrode 19 than to the lower electrode 15. When “1” is stored in the memory cell, the polarization of the ferroelectric film 17 is not reversed, so that the charge distribution of the ferroelectric capacitor 2 does not change greatly. For example, almost no current flows in the bit line. Not flowing. On the other hand, when “0” is stored in the memory cell, the polarization of the ferroelectric film 17 is inverted, so that a large change occurs in the charge distribution of the ferroelectric capacitor 2, for example, relative to the bit line. Large current flows. As described above, since the magnitude of the current flowing through the bit line differs depending on the data stored in the memory cell, the nonvolatile memory 1 can determine the value of the read data based on the magnitude of the current value.

  The conventional nonvolatile memory using a ferroelectric material containing a magnetic element and a large spontaneous polarization has a relatively large leakage current flowing in the ferroelectric film, so that the spontaneous polarization is easily lost over time, and the stored data is lost. Have the problem of On the other hand, the nonvolatile memory 1 according to the present embodiment is formed by applying a magnetic field of 10 kOe in the film thickness direction of the ferroelectric film 17 and heating it to 400 ° C. to thereby form a leakage current of the ferroelectric film 17. Is suppressed. As a result, the nonvolatile memory 1 can prevent the loss of stored data because the spontaneous polarization is unlikely to be lost over time even when a ferroelectric material containing a magnetic element and having a large spontaneous polarization is used. Therefore, the nonvolatile memory 1 can be used stably.

Next, a method for manufacturing the nonvolatile memory 1 according to the present embodiment will be described with reference to FIGS. 3 to 6 are process cross-sectional views illustrating the method for manufacturing the nonvolatile memory 1 according to the present embodiment. First, as shown in FIG. 3A, for example, SiO ₂ is formed on the entire surface of the n-type silicon semiconductor substrate 3 in which the p-type cell selection transistor 5 is formed in the element region defined by the element isolation insulating film 7. An interlayer insulating film 9 is formed. The interlayer insulating film 9 is formed using a plasma CVD method using TEOS gas. Subsequently, the interlayer insulating film 9 is polished by a chemical mechanical polishing (CMP) method to planarize the surface. Next, a contact hole that opens a part of the surface of the source region S is formed in the interlayer insulating film 9. Next, a tungsten plug 11 is formed by filling the contact hole.

Next, as shown in FIG. 3B, a silicon oxide film 63 is formed on the entire surface of the interlayer insulating film 9. Next, a titanium oxide layer (not shown) is formed as an adhesion layer on the entire surface of the silicon oxide film 63, and then a platinum (Pt) layer 65 serving as a lower electrode is formed on the entire surface of the titanium oxide layer by using, for example, a sputtering method. . Then, for example, by MOCVD to form the BiFeO ₃ layer 67 on the entire surface of the Pt layer 65 and then a Pt layer 69 made of, for example, an upper electrode on the entire surface of the BiFeO ₃ layer 67 by vacuum evaporation.

Next, as shown in FIG. 4A, a resist is applied and patterned to form a resist layer 60 on the element isolation insulating film 7 side. Next, the top of the semiconductor substrate 3 is etched using a chlorine-based etching gas using the resist layer 60 as an etching mask, and the exposed Pt layer 69 and BiFeO ₃ layer 67 are sequentially removed as shown in FIG. Etching is performed until the Pt layer 65 is exposed. Finally, the resist layer 60 used as an etching mask is removed.

Next, as shown in FIG. 4B, a resist is applied and patterned, and a resist layer 62 is formed so as to cover the Pt layer 69 and the BiFeO ₃ layer 67 on the element isolation insulating film 7 side. Next, the top of the semiconductor substrate 3 is etched using a chlorine-based etching gas using the resist layer 62 as an etching mask, and the exposed Pt layer 65 is removed as shown in FIG. Etching is carried out until is exposed. Finally, the resist layer 62 used as an etching mask is removed.

  Next, as shown in FIG. 5A, a resist is applied and patterned to form a resist layer 64 that opens on the source region S of the cell selection transistor 5. Next, the top surface of the semiconductor substrate 3 is etched using a chlorine-based etching gas using the resist layer 64 as an etching mask, the silicon oxide film 63 in the exposed portion is removed, and etching is performed until the tungsten plug 11 is exposed. . Finally, the resist layer 64 used as an etching mask is removed.

Thus, as shown in FIG. 5B, the Pt lower electrode 15 formed on the silicon oxide film 13, the BiFeO ₃ ferroelectric film 17 formed on the lower electrode 15, and the ferroelectric film. The ferroelectric capacitor 2 having the Pt upper electrode 19 formed on the capacitor 17 is completed. Next, as shown in FIG. 5B, a silicon oxide film 71 is formed on the entire surface. Next, a resist is applied and patterned to form a resist layer (not shown) that covers the ferroelectric capacitor 2. A region where a contact hole CH will be formed in the future is opened in the resist layer.

  Next, as shown in FIG. 6A, the top surface of the semiconductor substrate 3 is etched by etching the semiconductor substrate 3 using a chlorine-based etching gas using the resist layer as an etching mask, and removing the exposed silicon oxide film 71. Etching is performed until the tungsten plug 11 is exposed. Finally, the resist layer used as an etching mask is removed. Thereby, the insulating film 21 having the contact hole CH is formed. Next, a metal layer (not shown) is formed on the entire surface using aluminum (Al) or copper (Cu) and patterned into a predetermined shape, and is embedded in the contact hole CH as shown in FIG. A wiring 23 extending to the cell selection transistor 5 side is formed. As a result, the upper electrode 19 and the source region S are electrically connected via the wiring 23 and the tungsten plug 11.

  Next, a magnetic field H of 10 kOe is applied in the film thickness direction of the ferroelectric film 17 and heated to 400 ° C. at 1 ° C./second, for example. Next, after hold | maintaining for 30 minutes at 400 degreeC, it cools at 1 degree-C / sec. Next, the application of the magnetic field H is terminated. Thus, the 1T1C type nonvolatile memory 1 is completed.

  As described above, the manufacturing method of the nonvolatile memory according to the present embodiment is the same manufacturing method as that of the conventional nonvolatile memory except that it includes a magnetic field application process and a heating process to the ferroelectric film 17. Can be used. According to the method for manufacturing the nonvolatile memory according to the present embodiment, the 1T1C type nonvolatile memory 1 having excellent memory retention characteristics by suppressing the leakage current of the ferroelectric film 17 can be manufactured. Further, a ferroelectric material containing a magnetic element can be used for the ferroelectric capacitor 2 and the amount of spontaneous polarization of the ferroelectric capacitor 2 is improved, so that the non-volatile memory 1 is increased in density and capacity. be able to.

[Second Embodiment]
A non-volatile memory and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. First, the principle of suppressing the leakage current of the ferroelectric film in the nonvolatile memory of the present embodiment will be described with reference to FIG. FIG. 7 is a diagram showing the leakage current of the BiFeO ₃ epitaxial film with respect to temperature and magnetic field. In the figure, the horizontal axis of each of the upper, middle and lower stages represents time Time (sec), the vertical axis of the upper stage represents temperature Temp (° C.), and the vertical axis of the middle stage represents magnetic field H (kOe). The lower vertical axis represents the leakage current I (A).

As shown in the range from 0 (sec) to 300 (sec) in FIG. 7, the BiFeO ₃ film is heated to 60 ° C. without applying the magnetic field H, maintained at 60 ° C. for about 30 seconds, and then at room temperature. When the temperature is cooled down, the leakage current I of the BiFeO ₃ film increases as the temperature rises and returns to the original value when it returns to room temperature. Next, as shown in the range from 300 (sec) to 1000 (sec) in FIG. 7, the BiFeO ₃ film is heated to 60 ° C. and maintained at 60 ° C. for about 30 seconds, and then 10 (kOe). A magnetic field H is applied. In this case, the leakage current I of the BiFeO ₃ film decreases as the magnetic field H is applied. When the magnetic field H is applied to the leakage current I of the BiFeO ₃ film, the current value is lower than that before heating and application of the magnetic field even when the temperature returns to room temperature. When the application of the magnetic field H is finished, the leakage current I of the BiFeO ₃ film returns to the current value before heating and magnetic field application.

  The nonvolatile memory 1 according to the first embodiment is applied with a magnetic field at a high temperature of 400 ° C. during manufacture. Therefore, the nonvolatile memory 1 according to the first embodiment can suppress the leakage current of the ferroelectric film 17 even when no magnetic field is applied in an environment where the ambient temperature is about room temperature. However, since a manufacturing apparatus capable of heating up to 400 ° C. while applying a magnetic field to the nonvolatile memory is expensive, it may lead to an increase in the manufacturing cost of the nonvolatile memory.

  Therefore, the nonvolatile memory according to the present embodiment is characterized in that a magnetic field application unit is provided so that a magnetic field can be always applied in order to suppress leakage current. Furthermore, the manufacturing method of the nonvolatile memory according to the present embodiment is characterized in that the manufacturing cost can be reduced by applying a magnetic field at a low temperature of about 60 ° C. Hereinafter, the nonvolatile memory and the manufacturing method thereof according to the present embodiment will be described more specifically with reference to examples. Of the constituent elements of the nonvolatile memory 1 of the present embodiment, constituent elements having the same functions / actions as those of the nonvolatile memory 1 of the first embodiment are denoted by the same reference numerals and description thereof is omitted. In addition, since the data writing / reading method of the nonvolatile memory 1 according to the following examples is the same as that of the nonvolatile memory 1 of the first embodiment, the description thereof is omitted.

(Example 2-1)
The non-volatile memory 1 according to Example 2-1 of this embodiment will be described with reference to FIG. FIG. 8A shows a cross-sectional structure perpendicular to the substrate surface of one memory cell of the nonvolatile memory 1 according to this embodiment. FIG. 8B shows a cross-sectional structure perpendicular to the substrate surface of one memory cell of the nonvolatile memory 1 according to the modification of the present embodiment. As shown in FIG. 8A, the nonvolatile memory 1 has a ferromagnetic layer 25 as a magnetic field application unit formed on the upper electrode 19. The ferromagnetic layer 25 is made of a CoCrPt alloy. The ferromagnetic layer 25 is not limited to a CoCrPt alloy, and may be formed of any other Co alloy such as a CoCr alloy, a CoPt alloy, or a CoCrTa alloy. Further, it goes without saying that the ferromagnetic layer 25 may be formed of a Ni alloy or a Fe alloy in addition to the Co alloy. Furthermore, the ferromagnetic layer 25 may be formed of La _1-x Sr _x MnO ₃ (x = 0.0 to 1.0) oxide.

  The ferromagnetic layer 25 can apply a magnetic field in the film thickness direction of the ferroelectric film 17. In this embodiment, the ferromagnetic layer 25 is formed on the back side of the surface of the upper electrode 19 facing the ferroelectric film 17. However, the ferromagnetic layer 25 is formed on the back surface side (the lower layer of the lower electrode 15) of the lower electrode 15 facing the ferroelectric film 17 if a magnetic field can be applied in the film thickness direction of the ferroelectric film 17. Of course it is good.

  As shown in FIG. 8A, the insulating film 21 is formed with a contact hole CH that exposes a substantially central portion of the ferromagnetic layer 25. A wiring 23 is embedded in the contact hole CH. As a result, the upper electrode 19 is electrically connected to the source region S of the cell selection transistor 5 via the ferromagnetic layer 25, the wiring 23 and the tungsten plug 11.

  As will be described later, the nonvolatile memory 1 according to this embodiment is formed by applying a magnetic field of 15 kOe by the ferromagnetic layer 25 in the film thickness direction of the ferroelectric film 17 and heating to 60 ° C. during manufacture. . The non-volatile memory 1 according to this example has a lower heating temperature in the manufacturing stage than the non-volatile memory 1 according to the first embodiment. However, the nonvolatile memory 1 according to this embodiment can always apply a magnetic field from the ferromagnetic layer 25 to the ferroelectric film 17 when actually used as a storage device. Thereby, even if the nonvolatile memory 1 is used in a room temperature or high temperature environment, the leakage current of the ferroelectric film 17 can be suppressed. Thereby, the non-volatile memory 1 according to the present example can obtain the same effect as the non-volatile memory 1 according to the first embodiment.

Next, a method for manufacturing the nonvolatile memory 1 according to this embodiment will be briefly described. Since the manufacturing method of this example is almost the same as that of the first embodiment, only the steps having differences will be described briefly. After the Pt layer 69 shown in FIG. 3B is formed, a CoCrPt alloy magnetic layer is formed by sputtering, and then a resist layer 60 shown in FIG. 4A is formed. Next, etching is performed on the semiconductor substrate 3 using the chlorine-based etching gas using the resist layer 60 as an etching mask, and the exposed CoCrPt alloy magnetic layer, the Pt layer 69 and the BiFeO ₃ layer 67 are sequentially removed. Etching is performed until the Pt layer 65 is exposed. Thus, a CoCrPt alloy magnetic layer is formed on the Pt layer 69 to be the upper electrode 19.

  Thereafter, a contact hole CH is formed in the silicon oxide film 71 to be the insulating film 21, and the magnetic layer is exposed in the contact hole CH. Thereby, the ferromagnetic layer 25 is completed. Thereafter, the nonvolatile memory 1 shown in FIG. 8A is formed, heated to 60 ° C., maintained at 60 ° C. for about 30 seconds, and then cooled at 1 ° C./second. A magnetic field H of about 15 kOe is applied to the ferroelectric film 17 by the ferromagnetic layer 25 before and after heating. Thus, the nonvolatile memory 1 of this embodiment is completed.

  As described above, the manufacturing method of the nonvolatile memory 1 according to the present example can lower the heating temperature although the formation process of the ferromagnetic layer 25 is increased as compared with the manufacturing method of the first embodiment. The heating time can be shortened. Thereby, since the nonvolatile memory 1 according to the present embodiment can be manufactured by a relatively inexpensive manufacturing apparatus, the manufacturing cost can be reduced.

  Next, a nonvolatile memory 1 according to a modification of the present embodiment will be described with reference to FIG. As shown in FIG. 8B, the nonvolatile memory 1 of the present modification is characterized in that a contact hole CH is formed so as to expose the end portion side of the ferromagnetic layer 25. The non-volatile memory 1 of the present modification has the same structure as that of the non-volatile memory 1 shown in FIG. 8A except that the contact hole CH is formed at a different position, and is manufactured by the same manufacturing method. The Thereby, the nonvolatile memory 1 of the present modification can obtain the same effect as the nonvolatile memory 1 shown in FIG.

(Example 2-2)
The non-volatile memory 1 according to Example 2-2 of the present embodiment will be described with reference to FIG. FIG. 9 shows a cross-sectional structure perpendicular to the substrate surface of one memory cell of the nonvolatile memory 1 according to this embodiment. As shown in FIG. 9, the nonvolatile memory 1 according to the present embodiment is characterized in that it includes a pair of permanent magnets 27a and 27b as magnetic field application units instead of the ferromagnetic layer 25 of the embodiment 2-1. Have. The pair of permanent magnets 27a and 27b are arranged to face each other with the memory cell interposed therebetween so that a magnetic field can be applied in the film thickness direction of the ferroelectric film 17. The nonvolatile memory 1 according to the present example has the same memory cell configuration as the nonvolatile memory 1 of the first embodiment.

  The permanent magnet 27 a is formed on the back surface of the upper electrode 19 facing the ferroelectric film 17 and on the insulating film 29 that covers the ferroelectric capacitor 2. The permanent magnet 27 b is formed on the back side of the surface of the lower electrode 15 facing the ferroelectric film 17 and on the back side of the film forming surface of the semiconductor substrate 3. The surfaces of the permanent magnets 27a and 27b on the film surface side of the ferroelectric film 17 are magnetized by different magnetic poles so that the pair of permanent magnets 27a and 27b can apply a magnetic field in the film thickness direction of the ferroelectric film 17. Yes. For example, the surface of the permanent magnet 27a on the side of the ferroelectric film 17 is magnetized to the N pole, and the surface of the permanent magnet 27b on the side of the ferroelectric film 17 is magnetized to the S pole. Thereby, a magnetic field directed from the upper electrode 19 side to the lower electrode 15 side is applied to the ferroelectric film 17. The pair of permanent magnets as the magnetic field applying unit is not necessarily a pair, and the nonvolatile memory 1 has only one of the permanent magnets 27a and 27b as long as a magnetic field having a predetermined strength can be applied to the ferroelectric film 17. It only has to be.

  As will be described later, the nonvolatile memory 1 according to this embodiment is formed by applying a 15 kOe magnetic field by the permanent magnets 27a and 27b in the film thickness direction of the ferroelectric film 17 and heating it to 60 ° C. during manufacture. The Thereby, the non-volatile memory 1 according to the present embodiment can obtain the same effects as the non-volatile memory 1 according to the embodiment 2-1.

  Next, a method for manufacturing the nonvolatile memory 1 according to this embodiment will be briefly described. Since the manufacturing method of this example is almost the same as that of the first embodiment, only the steps having differences will be described briefly. The wirings 23 are formed on the semiconductor substrate 3 by the same manufacturing method as in the first embodiment. Next, as shown in FIG. 9, an insulating film 29 is formed on the entire surface of the semiconductor substrate 3 as necessary. Thereafter, the insulating film 29 is polished by CMP to flatten the surface. Next, for example, the permanent magnet 27 a is attached with the N pole side facing the surface of the insulating film 29, and the permanent magnet 27 b is attached with the S pole side facing the back surface of the semiconductor substrate 3.

  Next, the semiconductor substrate 3 is heated and cooled with the same temperature profile as in Example 2-1. Before and after heating, a magnetic field H of about 15 kOe is applied to the ferroelectric film 17 by the permanent magnets 27a and 27b. Thus, the nonvolatile memory 1 of this embodiment is completed.

  As described above, the manufacturing method of the nonvolatile memory 1 according to the present example can lower the heating temperature although the attaching process of the permanent magnets 27a and 27b is increased compared to the manufacturing method of the first embodiment. In addition, the heating time can be shortened. Thereby, the non-volatile memory 1 according to the present embodiment can obtain the same effects as those of the embodiment 2-1.

(Example 2-3)
The nonvolatile memory 1 according to Example 2-3 of this embodiment will be described with reference to FIG. FIG. 10 shows a cross-sectional structure perpendicular to the substrate surface of the memory cell array of the nonvolatile memory 1 according to this embodiment. As shown in FIG. 10, the nonvolatile memory 1 according to the present embodiment is characterized in that it includes a pair of permanent magnets 27a and 27b as a magnetic field application unit, as in the case of the embodiment 2-2. The pair of permanent magnets 27a and 27b are arranged to face each other with the memory cell array interposed therebetween so that a magnetic field can be applied in the film surface direction of the ferroelectric film 17. The nonvolatile memory 1 according to the present example has the same memory cell configuration as the nonvolatile memory 1 of the first embodiment.

  For example, the pair of permanent magnets 27a and 27b are disposed opposite to each other on the outer periphery of the memory cell array with the memory array interposed therebetween. The pair of permanent magnets 27 a and 27 b are disposed so as to be substantially orthogonal to the film surface of the ferroelectric film 17. The pair of permanent magnets 27a and 27b are magnetized with different magnetic poles on the surface on the memory cell array side so that a magnetic field can be applied in the film surface direction of the ferroelectric film 17. For example, the surface of the permanent magnet 27a is magnetized to the N pole, and the surface of the permanent magnet 27b is magnetized to the S pole. Thereby, a magnetic field directed from the permanent magnet 27a to the permanent magnet 27b is applied to the ferroelectric film 17 provided in each memory cell. The pair of permanent magnets as the magnetic field applying unit is not necessarily a pair, and the nonvolatile memory 1 has only one of the permanent magnets 27a and 27b as long as a magnetic field having a predetermined strength can be applied to the ferroelectric film 17. It only has to be.

  The nonvolatile memory 1 according to the present embodiment is formed by applying a 15 kOe magnetic field by the permanent magnets 27a and 27b in the direction of the film surface of the ferroelectric film 17 and heating to 60 ° C. at the time of manufacture. Thereby, the non-volatile memory 1 according to the present embodiment can obtain the same effects as the non-volatile memory 1 according to the embodiment 2-2.

By the way, the bulk of BiFeO ₃ has a spiral spin structure with a period of about 60 nm. Reported by Sosnowska et al. (I. Sosnowska, et.al. Solid State Phys (1982)). For this reason, when the BiFeO ₃ material is formed on the (100) epitaxial film, the magnetization varies in the plane. On the other hand, the existence of the electromagnetic effect of BiFeO ₃ material has been reported by Kadomtseva et al. (AM Kadomtseva, et.al., Physica B (1995)). From this result, it can be seen that magnetization and polarization interact. In the case of a thin film, since a voltage is applied in the direction perpendicular to the plane, it is considered that the function of magnetization variation in the plane leads to leakage current. Therefore, it is necessary to suppress variations in in-plane magnetization. In the case of BiFeO ₃ film from the above, the magnetic field was applied perpendicular to the plane of the film, believed to leakage current of the BiFeO ₃ film is lowered.

  In both the present embodiment and the embodiment 2-2, the effect of suppressing the leakage current of the ferroelectric film 17 can be obtained. However, for the above reason, the leakage current of the ferroelectric film 17 can be effectively suppressed when the permanent magnets 27a and 27b are arranged as in the embodiment 2-2.

  Since the manufacturing method of the non-volatile memory 1 according to the present embodiment is the same as the manufacturing method of the non-volatile memory 1 according to the embodiment 2-2 except that the attaching positions of the permanent magnets 27a and 27b are different, the description thereof is omitted. .

[Third Embodiment]
A nonvolatile memory and a method for manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS. First, a schematic configuration of the nonvolatile memory 10 according to the present embodiment will be described with reference to FIG. FIG. 11 schematically shows a cross-sectional structure perpendicular to the substrate surface of one memory cell in the memory cell array formed in the array shape of the nonvolatile memory 10 of the present embodiment. As shown in FIG. 11, the memory cell of the nonvolatile memory 10 is formed in an element region defined by an element isolation insulating film (not shown) formed on the n-type silicon semiconductor substrate 3, for example. The gate portion 39 of the nonvolatile memory 10 is a gate formed of, for example, a 5 nm thick YSZ (Yttrium Stabilized Zirconia) film 31 and a 10 nm thick strontium titanate film (STO film) 33 formed on the semiconductor substrate 3. An insulating film 30; a BiFeO ₃ ferroelectric film 35 of, eg, a 200 nm-thickness formed on the gate insulating film 30; and a Pt gate electrode G, eg, of 200 nm-thickness, formed on the ferroelectric film 35; have.

The material for forming the ferroelectric film 35 is not limited to BiFeO ₃ , and the same material as that for the ferroelectric film 17 in the first embodiment can be used. Further, the gate insulating film 30 may be formed using another insulating material instead of the YSZ film 31 and the STO film 33. If a good interface with few carrier trap levels is obtained, the ferroelectric film 35 may be formed directly on the semiconductor substrate 3 without forming the gate insulating film 30.

  A surface layer portion of the semiconductor substrate 3 below the gate insulating film 30 is a channel region 37. On both sides of the channel region 37, a source region S and a drain region D which are p-type impurity activation regions are formed. End portions of the source region S and the drain region D are formed so as to extend below the gate insulating film 30.

As described above, the nonvolatile memory 10 includes the gate portion 39 in which the gate insulating film 30, the ferroelectric film 35, and the gate electrode G are stacked in this order, the channel region 37 under the gate portion 39, and the channel region. The structure of a p-channel MFIS (metal (METAL) -ferroelectric (FERROMAGNETIC) -insulating layer (INSULATOR) -semiconductor (SEMICONDUCTOR)) type FET having source / drain regions S and D formed on both sides of 37 is shown. Have. In the present embodiment, the formation material Pt of the gate electrode G is “M”, BiFeO _{3 as} the formation material of the ferroelectric film 35 is “F”, and the STO film 33 / The YSZ film 31 is “I”.

A silicon oxynitride (SiON) cover film and a silicon dioxide (SiO ₂ ) interlayer insulating film (both not shown) are formed on the entire surface of the semiconductor substrate 3 to cover the gate portion 39. On the source / drain regions S and D and the gate electrode G, tungsten plugs 41, 43 and 45 are formed by burying tungsten (W) in contact holes having an interlayer insulating film opened. The source region S is connected to the plate line PL via the tungsten plug 41, the drain region D is connected to the bit line BL via the tungsten plug 43, and the gate electrode G is connected to the word line WL via the tungsten plug 45. It is connected to the.

  The nonvolatile memory 10 of the present embodiment stores data according to the direction of spontaneous polarization of the ferroelectric film 35. As will be described later, the nonvolatile memory 10 is formed by applying a magnetic field of 10 kOe in the surface vertical direction (film thickness direction) of the ferroelectric film 35 and heating to 400 ° C. Thereby, since the leakage current of the ferroelectric film 35 is suppressed in the nonvolatile memory 10, the spontaneous polarization is not easily lost over time. Therefore, the nonvolatile memory 10 has improved retention characteristics such as retention characteristics and imprint characteristics, and can be used stably.

  Next, the data write / read operation of the nonvolatile memory 10 according to the present embodiment will be briefly described with reference to FIG. First, the data write operation of the nonvolatile memory 10 according to the present embodiment will be described. For example, a voltage of −Vg (V) is applied to the gate electrode G through the word line WL to select a memory cell in which data is written. Next, when data “1” is written, for example, a voltage of 0 (V) is applied to the bit line BL. As a result, a voltage having a lower potential on the gate electrode G side than on the semiconductor substrate 3 side is applied to the ferroelectric film 35. Therefore, the ferroelectric film 35 is polarized in the direction from the semiconductor substrate 3 toward the gate electrode G. The direction of this polarization is associated with the data “1”.

  On the other hand, when writing “0” data, for example, a voltage of −2 Vg (V) is applied to the bit line BL. As a result, a voltage having a higher potential is applied to the ferroelectric film 35 on the gate electrode G side than on the semiconductor substrate 3 side. Accordingly, the ferroelectric film 35 is polarized in the direction from the gate electrode G to the semiconductor substrate 3. This polarization direction is associated with data “0”.

  Next, the data read operation of the nonvolatile memory 10 according to this embodiment will be described. In both cases of data reading of “1” and “0”, for example, a voltage of 0 (V) is applied to the gate electrode G of the memory cell to be read through the word line WL, and the bit line BL is applied, for example. A read voltage + Vr (V) is applied, and the plate line PL is connected to GND, for example. When data “1” is stored in the memory cell, holes are collected in the channel region 37 due to polarization in the direction from the semiconductor substrate 3 to the gate electrode G generated in the ferroelectric film 35. As a result, an inversion layer is formed in the channel region 37, so that a current flows through the bit line BL, for example. On the other hand, when “0” data is stored, electrons are collected in the channel region 37 due to polarization in the direction from the gate electrode G generated in the ferroelectric film 35 toward the semiconductor substrate 3. Thereby, since the inversion layer is not formed in the channel region 37, only a very small current that can be regarded as 0 flows through the bit line BL, for example. Thus, since the magnitude of the current flowing through the bit line BL differs depending on the data stored in the memory cell, the nonvolatile memory 10 can determine the value of the read data based on the magnitude of the current value.

  The nonvolatile memory 10 according to the present embodiment applies a magnetic field of 10 kOe in the film thickness direction of the ferroelectric film 35 and is heated to 400 ° C. as in the nonvolatile memory 1 according to the first embodiment. As a result, the leakage current of the ferroelectric film 35 is suppressed. Thereby, since the non-volatile memory 10 is less likely to lose its spontaneous polarization with the passage of time and the stored data is hardly lost, the nonvolatile memory 10 can be used stably.

Next, a method for manufacturing the nonvolatile memory 10 according to the present embodiment will be described with reference to FIGS. 12 and 13 are process cross-sectional views illustrating the method for manufacturing the nonvolatile memory 10 according to the present embodiment. First, a 2-inch n-type silicon single crystal semiconductor substrate 3 having a (001) orientation is washed and then immersed in 9 wt% dilute hydrofluoric acid to remove the SiOx layer on the substrate surface. Next, as shown in FIG. 12A, the semiconductor substrate 3 is set in the film forming chamber and held at an actual substrate temperature of 550 ° C., and the pressure in the film forming chamber is set to 7 × 10 ⁻² (Pa). To do. Then, while flowing 12 sccm (gas flow rate per minute at 20 ° C. and 1 atm (mL / min)) into the film forming chamber, the YSZ target was irradiated with a KrF excimer laser, and pulsed laser deposition was used. A YSZ layer 81 having a thickness of 5 nm is epitaxially grown on the entire surface of the semiconductor substrate 3.

  Although the crystal structure of the ferroelectric layer can be directly formed on the YSZ layer 81, it is preferable to use another orientation because the orientation becomes (101) and the amount of polarization decreases. Therefore, the YSZ target in the film forming chamber is changed to a strontium carbonate target. Thereafter, the pressure in the deposition chamber is set to 1.3 Pa, the oxygen is supplied into the deposition chamber at a flow rate of 6 sccm, the actual substrate temperature is maintained at 650 ° C., a KrF excimer laser is irradiated to the strontium carbonate target, and YSZ An SrO layer (not shown) having a thickness of 2 nm is epitaxially grown on the entire surface of the layer 81.

  Next, the strontium carbonate target in the deposition chamber is changed to a strontium titanate target. Next, the pressure in the film forming chamber is set to 27 Pa, and oxygen is supplied into the film forming chamber at a flow rate of 6 sccm while irradiating a KrF excimer laser to form the STO layer 83 on the entire surface of the SrO / YSZ layer 81 with a thickness of 10 nm. Epitaxial growth in the (001) direction. Since the SrO layer is thin, it is taken into the STO layer 83 during the formation of the strontium titanate film. Thus, the YSZ layer 81 and the STO layer 83 are stacked on the semiconductor substrate 3. These films serve as an insulating layer, a role that enables crystal epitaxial growth of a ferroelectric layer to be formed later, and a barrier between the semiconductor substrate 3 and the ferroelectric layer, thereby forming a ferroelectric layer. It has a role of preventing a chemical reaction between the body layer and Si.

Next, the strontium titanate target in the film forming chamber is changed to a BiFeO ₃ target. Next, as shown in FIG. 12B, the pressure in the film formation chamber is set to 0.1 Pa, and a BiFeO ₃ target is irradiated with a KrF excimer laser while oxygen is supplied into the film formation chamber at a flow rate of 1 sccm. A ferroelectric layer 85 made of BiFeO ₃ is epitaxially grown in the (001) direction with a thickness of 200 nm on the entire surface of the layer 83 / YSZ layer 81. Next, a Pt layer 87 is formed on the entire surface of the ferroelectric layer 85 by using an electron beam evaporation method.

  Next, as shown in FIG. 12B, a magnetic field H of 10 kOe is applied in the direction perpendicular to the surface of the ferroelectric layer 85 and the semiconductor substrate 3 is heated to 400 ° C. at 1 ° C./second. The semiconductor substrate 3 is held at 400 ° C. for 30 minutes and then cooled at 1 ° C./second. Thereafter, the application of the magnetic field H is terminated.

  Next, as shown in FIG. 13A, a resist is applied and patterned to form a resist layer 80 on a region where a gate portion 39 will be formed in the future. Next, the four layers from the Pt layer 87 to the YSZ layer 81 are patterned into a predetermined shape using a photolithography technique. Etching is performed on the semiconductor substrate 3 using a mixed gas of argon and chlorine as an etching gas using the resist layer 80 as an etching mask, and an exposed Pt layer 87, a ferroelectric layer 85, an STO layer 83, and a YSZ layer 81 are sequentially formed. Etching is performed until the semiconductor substrate 3 is removed. Thereafter, the resist layer 80 is removed. Thus, the four layers from the Pt layer 87 to the YSZ layer 81 can be etched at once. Thus, the gate part 39 shown in FIG. 13B is completed.

Next, as shown in FIG. 13B, a p-type impurity such as B (boron) is introduced into a region in the semiconductor substrate 3 by using, for example, an ion implantation method using the gate electrode G as a mask. P-type impurity regions 91 and 93 are formed at positions where the source region S and the drain region D are formed. For example, the implantation conditions of B are acceleration energy of 20 keV to 60 keV and a dose of 2 × 10 ¹⁵ cm ⁻² to 2 × 10 ¹⁶ cm ⁻² , preferably an acceleration energy of 40 keV and a dose of 8 × 10 ¹⁵ cm ⁻² . Ion implanted.

  Next, annealing is performed using a rapid lamp heating device or the like to activate the implanted impurities. This annealing treatment is performed, for example, at a heating temperature (attainment temperature) of 700 ° C. to 1000 ° C. and a heating time of 20 s to 120 s. As a result, the p-type impurity regions 91 and 93 are activated, and a source region S and a drain region D are formed on both sides of the gate portion 39 as shown in FIG.

Thereafter, an interlayer insulating film (not shown) of silicon dioxide (SiO ₂ ) is grown on the cover film to a thickness of about 1.0 μm by plasma CVD using TEOS gas. Subsequently, the interlayer insulating film is polished by CMP to planarize the surface. Next, contact holes that expose portions of the surfaces of the source region S, the drain region D, and the gate electrode G are formed in the interlayer insulating film. Next, tungsten plugs 41, 43, and 45 are formed by filling each contact hole. Next, wirings (not shown) electrically connected to the tungsten plugs 41, 43, and 45 are formed, and an interlayer insulating film (not shown) is formed so as to embed the wirings. This wiring process is repeated a plurality of times depending on the circuit configuration. Thereafter, plate lines PL, bit lines BL, and word lines WL electrically connected to the tungsten plugs 41, 43, 45 are formed. Through the above steps, the nonvolatile memory 10 according to the present embodiment having a structure as shown in FIG. 11 is completed.

  As described above, the manufacturing method of the nonvolatile memory according to the present embodiment includes the conventional MFIS FET structure nonvolatile memory except that it includes a magnetic field application step and a heating step to the ferroelectric film 35. Similar manufacturing methods can be used. According to the method for manufacturing the nonvolatile memory according to the present embodiment, since the leakage current of the ferroelectric film 35 is suppressed, the nonvolatile memory 10 is the same as the nonvolatile memory 1 of the first embodiment. An effect is obtained.

[Fourth Embodiment]
A nonvolatile memory and a method for manufacturing the same according to a fourth embodiment of the present invention will be described with reference to FIGS. The nonvolatile memory according to the present embodiment has a memory cell having an MFIS type FET structure, and is characterized in that the leakage current of the ferroelectric film is suppressed based on the same principle as in the second embodiment. ing. Hereinafter, the nonvolatile memory and the manufacturing method thereof according to the present embodiment will be described more specifically with reference to examples. Of the components of the nonvolatile memory 10 of the present embodiment, components having the same functions / actions as those of the nonvolatile memory 10 of the third embodiment are denoted by the same reference numerals, and the description thereof is omitted. Further, the data writing / reading method of the nonvolatile memory 10 according to the following example is the same as that of the nonvolatile memory 10 of the third embodiment, and thus the description thereof is omitted.

(Example 4-1)
The nonvolatile memory 10 according to Example 4-1 of the present embodiment will be described with reference to FIG. FIG. 14 schematically shows a cross-sectional structure perpendicular to the substrate surface of one memory cell of the nonvolatile memory 10 according to this embodiment. As shown in FIG. 14, the nonvolatile memory 10 includes a ferromagnetic layer 47 formed on the gate electrode G as a magnetic field application unit. The ferromagnetic layer 47 is made of a CoCrPt alloy. The ferromagnetic layer 47 is not limited to a CoCrPt alloy, and the same material as that of the ferromagnetic layer 25 shown in Example 2-1 can be used.

  The ferromagnetic layer 47 can apply a magnetic field in the film thickness direction of the ferroelectric film 35. In this embodiment, the ferromagnetic layer 47 is formed on the back side of the surface of the gate electrode G facing the ferroelectric film 35. However, the ferromagnetic layer 47 may be formed on the side facing the ferroelectric film 35 of the gate electrode G (under the gate electrode G) as long as a magnetic field can be applied in the film thickness direction of the ferroelectric film 35. Good.

  The ferromagnetic layer 47 has a contact hole (not shown) for embedding a tungsten plug 45 electrically connected to the gate electrode G. As a result, the gate electrode G is electrically connected to the word line WL via the tungsten plug 45.

  As will be described later, the nonvolatile memory 10 according to the present embodiment is formed by applying a 15 kOe magnetic field by the ferromagnetic layer 47 in the film thickness direction of the ferroelectric film 35 and heating it to 60 ° C. during manufacture. . Further, when the nonvolatile memory 10 according to the present embodiment is actually used as a storage device, a magnetic field generated by the ferromagnetic layer 47 can be constantly applied to the ferroelectric film 35. Therefore, the nonvolatile memory 10 according to the present embodiment can obtain the same effects as those of the nonvolatile memory 1 according to the embodiment 2-1.

  Next, a method for manufacturing the nonvolatile memory 10 according to this embodiment will be briefly described. Since the manufacturing method of this example is almost the same as that of the third embodiment, only the steps having differences will be described briefly. After the formation of the Pt layer 87 shown in FIG. 12B, a magnetic layer of CoCrPt alloy is formed by sputtering. Thereafter, the semiconductor substrate 3 is heated to 60 ° C., maintained at 60 ° C. for about 30 seconds, and then cooled at 1 ° C./second. Before and after the heating, a magnetic field of about 15 kOe is applied to the ferroelectric layer 85 by the ferromagnetic layer. Thereafter, in a wiring process for forming an interlayer insulating film, wiring, and the like, a contact hole is formed in the ferromagnetic layer 47, and a tungsten plug 45 is embedded in the contact hole.

  As described above, the manufacturing method of the nonvolatile memory 10 according to this example can lower the heating temperature although the number of steps of forming the ferromagnetic layer 47 is increased as compared with the manufacturing method of the third embodiment. The heating time can be shortened. Thereby, since the nonvolatile memory 10 according to the present embodiment can be manufactured by a relatively inexpensive manufacturing apparatus, the manufacturing cost can be reduced.

(Example 4-2)
The non-volatile memory 10 according to Example 4-2 of the present embodiment will be described with reference to FIG. FIG. 15 schematically shows a cross-sectional structure perpendicular to the substrate surface of one memory cell of the nonvolatile memory 10 according to this embodiment. As shown in FIG. 15, the nonvolatile memory 10 according to the present embodiment is characterized in that it includes a pair of permanent magnets 49 a and 49 b as magnetic field application units instead of the ferromagnetic layer 47 of the embodiment 4-1. Have. The pair of permanent magnets 49a and 49b are arranged to face each other with the memory cell interposed therebetween so that a magnetic field can be applied in the film thickness direction of the ferroelectric film 35. The nonvolatile memory 10 according to the present example has the same memory cell configuration as the nonvolatile memory 10 of the third embodiment.

  The permanent magnet 29 a is formed on the back surface side of the surface of the gate electrode G facing the ferroelectric film 35 and on the insulating film 51 covering the gate portion 39. The permanent magnet 49 b is formed on the side facing the ferroelectric film 35 of the gate electrode G and on the back side of the film forming surface of the semiconductor substrate 3. The surfaces of the permanent magnets 49a and 49b on the film surface side of the ferroelectric film 35 are magnetized by different magnetic poles so that the pair of permanent magnets 49a and 49b can apply a magnetic field in the film thickness direction of the ferroelectric film 35. Yes. For example, the surface of the permanent magnet 49a on the side of the ferroelectric film 35 is magnetized to the N pole, and the surface of the permanent magnet 49b on the side of the ferroelectric film 35 is magnetized to the S pole. Thereby, a magnetic field directed from the gate electrode G side to the semiconductor substrate 3 side is applied to the ferroelectric film 35. The pair of permanent magnets as the magnetic field applying unit is not necessarily a pair, and the nonvolatile memory 10 has only one of the permanent magnets 49a and 49b as long as a magnetic field having a predetermined strength can be applied to the ferroelectric film 35. It only has to be.

  As will be described later, the non-volatile memory 10 according to the present embodiment is formed by applying a magnetic field of 15 kOe by the permanent magnets 49a and 49b in the film thickness direction of the ferroelectric film 35 and heating to 60 ° C. during manufacture. The Thereby, the nonvolatile memory 10 according to the present embodiment can obtain the same effects as the nonvolatile memory 10 according to the embodiment 4-1.

  Next, a method for manufacturing the nonvolatile memory 10 according to this embodiment will be briefly described. Since the manufacturing method of this example is almost the same as that of the third embodiment, only the steps having differences will be described briefly. The word line WL, the bit line BL, the plate line PL, and the insulating film 51 are formed on the semiconductor substrate 3 by the same manufacturing method as in the third embodiment. Thereafter, the insulating film 51 is polished by a CMP method to flatten the surface. Next, for example, the permanent magnet 49a is pasted with the N pole side facing the surface of the insulating film 51, and the permanent magnet 49b is stuck with the S pole side facing the back surface of the semiconductor substrate 3.

  Next, the semiconductor substrate 3 is heated and cooled with the same temperature profile as in Example 4-1. Before and after heating, a magnetic field of about 15 kOe is applied to the ferroelectric film 35 by the permanent magnets 49a and 49b. Thus, the nonvolatile memory 10 of this embodiment is completed.

  As described above, the manufacturing method of the nonvolatile memory 10 according to the present example can lower the heating temperature although the attaching process of the permanent magnets 49a and 49b is increased compared to the manufacturing method of the third embodiment. Furthermore, the heating time can be shortened. Thereby, the nonvolatile memory 10 according to the present embodiment can obtain the same effects as those of the embodiment 4-1.

(Example 4-3)
The nonvolatile memory 10 according to Example 4-3 of the present embodiment will be described with reference to FIG. FIG. 16 schematically shows a cross-sectional structure perpendicular to the substrate surface of the memory cell array of the nonvolatile memory 10 according to this embodiment. As shown in FIG. 16, the non-volatile memory 10 according to the present embodiment is characterized in that it includes a pair of permanent magnets 49a and 49b as magnetic field application units, as in the case of the embodiment 4-2. The pair of permanent magnets 49a and 49b are arranged opposite to each other with the memory cell array interposed therebetween so that a magnetic field can be applied in the film surface direction of the ferroelectric film 35. The nonvolatile memory 10 according to the present example has the same memory cell configuration as the nonvolatile memory 10 of the third embodiment.

  The pair of permanent magnets 49a and 49b are disposed to face each other, for example, on the outer periphery of the memory cell array with the memory array interposed therebetween. The pair of permanent magnets 49a and 49b is disposed substantially orthogonal to the film surface of the ferroelectric film 35. The pair of permanent magnets 49a and 49b are magnetized with different magnetic poles on the memory cell array side so that a magnetic field can be applied in the direction of the film surface of the ferroelectric film 35. For example, the surface of the permanent magnet 49a is magnetized to the N pole, and the surface of the permanent magnet 49b is magnetized to the S pole. As a result, a magnetic field directed from the permanent magnet 49a to the permanent magnet 49b is applied to the ferroelectric film 35 provided in each memory cell. The pair of permanent magnets as the magnetic field application unit is not necessarily a pair, and the nonvolatile memory 10 has only one of the permanent magnets 49a and 49b as long as a magnetic field having a predetermined strength can be applied to the ferroelectric film 35. It only has to be.

  The nonvolatile memory 1 according to the present embodiment is formed by applying a 15 kOe magnetic field by the permanent magnets 49a and 49b in the direction of the film surface of the ferroelectric film 35 and heating to 60 ° C. during manufacture. Thereby, the nonvolatile memory 10 according to the present embodiment can obtain the same effects as the nonvolatile memory 10 according to the embodiment 4-2.

  In order to more effectively suppress the leakage current of the ferroelectric film 35 in the present embodiment, the permanent magnets 49a and 49b are configured as in Example 4-2 for the same reason as in the second embodiment. It is desirable to arrange.

  Since the manufacturing method of the non-volatile memory 10 according to the present embodiment is the same as the manufacturing method of the non-volatile memory 10 according to the embodiment 4-2 except that the attaching positions of the permanent magnets 49a and 49b are different, the description thereof is omitted. .

The present invention is not limited to the above embodiment, and various modifications can be made.
In the first to fourth embodiments, only the magnetic field is applied to the ferroelectric films 17 and 35 in the manufacturing process, but the present invention is not limited to this. For example, even when a magnetic field and an electric field are applied to the ferroelectric films 17 and 35 and heated to a predetermined temperature, the same effect as in the above embodiment can be obtained.

  In the second and fourth embodiments, the nonvolatile memories 1 and 10 have only one of the ferromagnetic layers 25 and 47 and the permanent magnets 27a, 27b, 49a, and 49b as a magnetic field application unit. However, the present invention is not limited to this. For example, even if the nonvolatile memories 1 and 10 have both a ferromagnetic layer and a permanent magnet as the magnetic field application unit, the same effects as those of the second and fourth embodiments can be obtained.

  In the second and fourth embodiments, a magnetic field is applied to the ferroelectric films 17 and 35 using the ferromagnetic layers 25 and 47 or the permanent magnets 27a, 27b, 49a, and 49b in the manufacturing process. The present invention is not limited to this. For example, in addition to the ferromagnetic layers 25 and 47 or the permanent magnets 27a, 27b, 49a, and 49b, even if a magnetic field is applied to the ferroelectric films 17 and 35 from the magnetic field applying unit of the manufacturing apparatus, The same effects as those of the embodiment can be obtained.

The nonvolatile memory and the manufacturing method thereof according to the present embodiment described above can be summarized as follows.
(Appendix 1)
A first electrode formed on a semiconductor substrate; a ferroelectric film formed on the first electrode and including a magnetic element; and a second electrode formed on the ferroelectric film. Ferroelectric capacitors,
A non-volatile memory comprising: a magnetic field applying unit that applies a magnetic field to the ferroelectric film.
(Appendix 2)
In the nonvolatile memory according to appendix 1,
The magnetic field application unit is formed on at least one of a back surface side of the surface facing the ferroelectric film of the first electrode and a back surface side of the surface facing the ferroelectric film of the second electrode. A non-volatile memory characterized by being a ferromagnetic layer.
(Appendix 3)
In the nonvolatile memory according to appendix 1,
The magnetic field application unit is disposed on at least one of a back surface side of the surface facing the ferroelectric film of the first electrode and a back surface side of the surface facing the ferroelectric film of the second electrode. A nonvolatile memory characterized by being a permanent magnet.
(Appendix 4)
In the nonvolatile memory according to appendix 1,
The non-volatile memory according to claim 1, wherein the magnetic field application unit is a permanent magnet disposed substantially orthogonal to the film surface of the ferroelectric film.
(Appendix 5)
A ferroelectric film formed on a semiconductor substrate and containing a magnetic element;
A gate electrode formed on the ferroelectric film;
Source / drain regions formed on both sides of the channel region at the interface of the semiconductor substrate below the ferroelectric film;
A non-volatile memory comprising: a magnetic field applying unit that applies a magnetic field to the ferroelectric film.
(Appendix 6)
In the nonvolatile memory according to appendix 5,
A non-volatile memory, wherein a gate insulating film is formed between the channel region and the ferroelectric film.
(Appendix 7)
In the nonvolatile memory according to appendix 5 or 6,
The magnetic field applying unit is a ferromagnetic layer formed on at least one of a surface of the gate electrode facing the ferroelectric film and a back surface of the gate electrode facing the ferroelectric film. Nonvolatile memory characterized by.
(Appendix 8)
In the nonvolatile memory according to appendix 5 or 6,
The magnetic field application unit is a permanent magnet disposed on at least one of a surface of the gate electrode facing the ferroelectric film and a back surface of the gate electrode facing the ferroelectric film. Features non-volatile memory.
(Appendix 9)
In the nonvolatile memory according to appendix 5 or 6,
The non-volatile memory according to claim 1, wherein the magnetic field application unit is a permanent magnet disposed substantially orthogonal to the film surface of the ferroelectric film.
(Appendix 10)
The nonvolatile memory according to any one of appendices 1 to 9,
The nonvolatile memory according to claim 1, wherein the magnetic field application unit is arranged so that a magnetic field can be applied in a film thickness direction or a film surface direction of the ferroelectric film.
(Appendix 11)
The nonvolatile memory according to any one of appendices 1 to 10,
The non-volatile memory, wherein the ferroelectric film is formed by applying a magnetic field or a magnetic field and an electric field and heating.
(Appendix 12)
The nonvolatile memory according to any one of appendices 1 to 11,
The ferroelectric material is a perovskite material having a crystal lattice with a composition formula of ABO ₃ ;
The A site of the crystal lattice includes Pb ions or Bi ions and at least one rare earth cation, and the B site of the crystal lattice is a cation and includes magnetic ions.
The non-volatile memory, wherein the magnetic ions are V ions, Cr ions, Mn ions, Fe ions, Co ions, Ni ions, or Cu ions.
(Appendix 13)
In the nonvolatile memory according to appendix 2 or 7,
The ferromagnetic layer is formed of any one material of Ni-based alloy, Fe-based alloy or Co-based alloy,
The Co-based alloy is a CoCr-based alloy, a CoPt-based alloy, a CoCrTa-based alloy, or a CoCrPt-based alloy.
(Appendix 14)
In the nonvolatile memory according to appendix 2 or 7,
The ferromagnetic _{layers, La 1-x Sr x MnO} 3 (x = 0.0~1.0) non-volatile memory, characterized in that it is formed of an oxide.
(Appendix 15)
A first electrode is formed on a substrate, a ferroelectric film containing a magnetic element is formed on the first electrode, and a second electrode is formed on the ferroelectric film to form a ferroelectric capacitor. Forming,
Applying a magnetic field or a magnetic field and an electric field to the ferroelectric film and heating the ferroelectric film;
A method for manufacturing a nonvolatile memory, comprising cooling the ferroelectric film.
(Appendix 16)
In the method for manufacturing a nonvolatile memory according to appendix 15,
Forming a ferromagnetic layer on at least one of a back surface side of the first electrode facing the ferroelectric film and a back surface side of the second electrode facing the ferroelectric film;
A method for manufacturing a nonvolatile memory, wherein the magnetic field is applied to the ferroelectric film using the ferromagnetic layer.
(Appendix 17)
In the method for manufacturing a nonvolatile memory according to appendix 15,
At least one of the back surface side of the surface of the first electrode facing the ferroelectric film and the back surface side of the surface of the second electrode facing the ferroelectric film, or the film surface of the ferroelectric film Place permanent magnets almost orthogonally,
A method for manufacturing a nonvolatile memory, wherein the magnetic field is applied to the ferroelectric film using the permanent magnet.
(Appendix 18)
Forming a ferroelectric film containing a magnetic element on a semiconductor substrate;
Forming a gate electrode on the ferroelectric film;
Forming source / drain regions on both sides of the channel region at the interface of the semiconductor substrate below the ferroelectric film;
Applying a magnetic field or a magnetic field and an electric field to the ferroelectric film and heating the ferroelectric film;
A method for manufacturing a nonvolatile memory, comprising cooling the ferroelectric film.
(Appendix 19)
In the method for manufacturing a nonvolatile memory according to appendix 18,
Forming a ferromagnetic layer on at least one of a side of the gate electrode facing the ferroelectric film and a back side of the gate electrode facing the ferroelectric film;
A method for manufacturing a nonvolatile memory, wherein the magnetic field is applied to the ferroelectric film using the ferromagnetic layer.
(Appendix 20)
In the method for manufacturing a nonvolatile memory according to appendix 18,
Permanent magnet substantially orthogonal to the surface of the gate electrode facing the ferroelectric film and at least one of the back surface of the gate electrode facing the ferroelectric film or the film surface of the ferroelectric film And place
A method for manufacturing a nonvolatile memory, wherein the magnetic field is applied to the ferroelectric film using the permanent magnet.

₃ is a diagram showing a crystal structure of BiFeO ₃ used as a material for forming a ferroelectric film 17 of the nonvolatile memory 1 according to the first embodiment of the present invention. FIG. 1 is a diagram showing a cross-sectional structure perpendicular to a substrate surface of a memory cell of a nonvolatile memory 1 according to a first embodiment of the present invention. It is process sectional drawing (the 1) which shows the manufacturing method of the non-volatile memory 1 by the 1st Embodiment of this invention. FIG. 6 is a process cross-sectional view (No. 2) illustrating the method for manufacturing the nonvolatile memory 1 according to the first embodiment of the invention. FIG. 6 is a process cross-sectional view (part 3) illustrating the method for manufacturing the nonvolatile memory 1 according to the first embodiment of the present invention. FIG. 6 is a process cross-sectional view (part 4) illustrating the method for manufacturing the nonvolatile memory 1 according to the first embodiment of the present invention. FIG. 6 is a diagram for explaining the principle of suppressing leakage current of the ferroelectric film 17 in the nonvolatile memory 1 according to the second embodiment of the present invention, and showing leakage current of the BiFeO ₃ epitaxial film with respect to temperature and magnetic field. It is. It is a figure which shows the cross-sectional structure perpendicular | vertical to the substrate surface of the memory cell of the non-volatile memory 1 by Example 2-1 of the 2nd Embodiment of this invention. It is a figure which shows the cross-sectional structure perpendicular | vertical to the substrate surface of the memory cell of the non-volatile memory 1 by Example 2-2 of the 2nd Embodiment of this invention. It is a figure which shows the cross-sectional structure perpendicular | vertical to the substrate surface of the memory cell array of the non-volatile memory 1 by Example 2-3 of the 2nd Embodiment of this invention. It is a figure which shows the cross-sectional structure perpendicular | vertical to the substrate surface of the memory cell of the non-volatile memory 10 by the 3rd Embodiment of this invention. It is process sectional drawing (the 1) which shows the manufacturing method of the non-volatile memory 10 by the 3rd Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the non-volatile memory 10 by the 3rd Embodiment of this invention. It is a figure which shows the cross-sectional structure perpendicular | vertical to the substrate surface of the memory cell of the non-volatile memory 10 by Example 4-1 of the 4th Embodiment of this invention. It is a figure which shows the cross-sectional structure perpendicular | vertical to the substrate surface of the memory cell of the non-volatile memory 10 by Example 4-2 of the 4th Embodiment of this invention. It is a figure which shows the cross-sectional structure perpendicular | vertical to the substrate surface of the memory cell array of the non-volatile memory 10 by Example 4-3 of the 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 10 Nonvolatile memory 2 Ferroelectric capacitor 3 N-type silicon semiconductor substrate 4, 30 Gate insulating film 5 Cell selection transistor 7 Element isolation insulating film 9 Interlayer insulating films 11, 41, 43, 45 Tungsten plugs 13, 71, 63 Silicon oxide film 15 Lower electrode 17, 35 Ferroelectric film 19 Upper electrode 21 Insulating film 23 Wiring 25, 47 Ferromagnetic layers 27a, 27b, 49a, 49b Permanent magnet 31 YSZ film 33 STO film 37 Channel region 39 Gate part 60 , 62, 64, 80 Resist layers 65, 69, 87 Platinum layer 67 BiFeO ₃ layer 81 YSZ layer 83 STO layer 85 Ferroelectric layer 91, 93 p-type impurity region CH Contact hole D Drain region G Gate electrode S Source region H Magnetic field BL Bit line PL Plate line WL Word line

Claims (5)

A first electrode formed on a semiconductor substrate; a ferroelectric film formed on the first electrode and including a magnetic element; and a second electrode formed on the ferroelectric film. Ferroelectric capacitors,
A non-volatile memory comprising: a magnetic field applying unit that applies a magnetic field to the ferroelectric film. A ferroelectric film formed on a semiconductor substrate and containing a magnetic element;
A gate electrode formed on the ferroelectric film;
Source / drain regions formed on both sides of the channel region below the ferroelectric film;
A non-volatile memory comprising: a magnetic field applying unit that applies a magnetic field to the ferroelectric film. The nonvolatile memory according to claim 1 or 2,
The nonvolatile memory according to claim 1, wherein the magnetic field application unit is arranged so that a magnetic field can be applied in a film thickness direction or a film surface direction of the ferroelectric film. A first electrode is formed on a substrate, a ferroelectric film containing a magnetic element is formed on the first electrode, and a second electrode is formed on the ferroelectric film to form a ferroelectric capacitor. Forming,
Applying a magnetic field or a magnetic field and an electric field to the ferroelectric film and heating the ferroelectric film;
A method for manufacturing a nonvolatile memory, comprising cooling the ferroelectric film. Forming a ferroelectric film containing a magnetic element on a semiconductor substrate;
Forming a gate electrode on the ferroelectric film;
Forming source / drain regions on both sides of the channel region below the ferroelectric film;
Applying a magnetic field or a magnetic field and an electric field to the ferroelectric film and heating the ferroelectric film;
A method for manufacturing a nonvolatile memory, comprising cooling the ferroelectric film.

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