JP2007259588A - Power consumption reduction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power consumption reduction circuit capable of reducing power consumption by reducing an off leakage current of a circuit with the addition of a simple circuit and capable of drastically extending the life of a battery, in a circuit which requires a stand-by state and a resumption function. <P>SOLUTION: The power consumption reduction circuit comprises a target circuit 10 that requires an operation stand-by state or the resumption function holding internal data and that is subjected to the reduction of the off leakage current, a power supply terminal 11 that supplies electric power to the target circuit, a resistance element R for the reduction of the off leakage current inserted in series to a power line between the power supply terminal and a power supply note of the target circuit, and a resistor-bypassing switching element SW connected in parallel to the resistance element and whose on/off is controlled according to the normal operation mode/operation stand-by mode of the target circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power consumption reduction circuit, and more particularly to an off-leakage current reduction circuit, and particularly relates to a logic circuit that requires a standby state, a memory circuit that requires a resume function, or a semiconductor integrated circuit (LSI that incorporates such a circuit). ) Is used.

  In designing LSI logic circuits, static current leakage (off-leakage current) that flows between the power supply and ground occurs despite the circuit operation being stopped, not the dynamic current consumption due to the normal operation of the circuit. . This off-leakage current increases more and more as the manufacturing process progresses, and the problem becomes significant. In particular, when a device that supplies power to a circuit has a finite charge capacity, such as a battery or battery, consumption due to off-leakage current leads to a decrease in the life of the power supply and is ignored in discussing the service life of the device. become unable. In this case, the power source is intended to have a life in terms of capacity, but for convenience of explanation, it will be expressed as “battery” hereinafter.

  On the other hand, when the operation of the electronic device is stopped, the supply of power may not be stopped completely, but the internal state may be maintained and the operation may be in a standby state (standby state). In this case, since the system is on standby while the internal state is maintained, a general usage may be an operation such as an operation (resume operation) for resuming from the same state as when the operation was stopped next time. Alternatively, it can be used for applications in which the user is not directly operating, but is waiting for the user's operation. In any of these cases, power must be continuously supplied in order to maintain the internal state, but since it is a standby state where no operation is actually performed, it is desired to suppress power consumption at this time as much as possible.

  Here, the circuit that is the target of power consumption reduction may include not only a normal logic circuit but also a storage circuit that holds internal data. In this case, when the battery is consumed and the power supply voltage is lowered, there arises a problem that the internal data of the memory circuit cannot be held. When the data cannot be retained, the resume operation is impossible for the device, and the battery reaches the end of its life. In other words, the lifetime is not when the charge stored in the battery is completely exhausted, but when the data retention function cannot be used.

  In order to solve these problems, the conventional method reduces leakage current by taking measures in terms of the manufacturing process such as devising the threshold voltage of the transistor, or devising the circuit structure at the cell level of the logic circuit. Although measures have been taken, the method is large for any method.

In Patent Document 1, in an LSI incorporating an internal data latch circuit that uses two power supply voltages, at the time of sleep, one of the power supply voltages supplied to the internal data latch circuit is a diode from the power supply voltage during normal operation. The point of supplying a lowered voltage is disclosed. As a result, even if the power supply voltage used in the internal data latch circuit is lowered during sleep, the internal data latch circuit can reduce the leakage current while holding the data. However, if the amount of power supply voltage drop is specified by a diode, the power supply voltage of the internal data latch circuit is lower than the power supply voltage during normal operation by the forward voltage of the diode. If it is not high, the required power supply voltage of the internal data latch circuit during sleep cannot be secured. Further, since the power supply voltage of the internal data latch circuit at the time of sleep is fixed to a low value, the leakage current cannot be reduced appropriately.
Japanese Patent Laid-Open No. 2003-110022

  The present invention has been made to solve the above-described conventional problems, and in a circuit that requires a standby state or a resume function, it is possible to reduce power consumption by reducing circuit off-leakage current by adding a simple circuit. An object of the present invention is to provide a power consumption reduction circuit capable of greatly extending the life of the battery as compared with the above method.

  A power consumption reduction circuit according to the present invention includes a target circuit having a resume function for holding an operation standby state or internal data, a power supply terminal for supplying power to the target circuit, the power supply terminal, and a power supply node of the target circuit. And a switching element connected in parallel to the resistance element and controlled to be turned on / off in accordance with the normal operation mode / standby mode of the target circuit. .

  According to the present invention, in a circuit that requires a standby state or a resume function, the off-leak current of the circuit can be reduced and power consumption can be reduced by adding a simple circuit, and the battery life can be greatly extended compared to the conventional method. A power consumption reduction circuit can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

  First, the outline of the power consumption reduction circuit of the present invention will be described. As described above, when the circuit operation is completely stopped, the off-leakage current flowing between the power source and the ground is not a dynamic current consumption due to a normal operation but a completely static current consumption. In the present invention, in order to reduce the power supply voltage of the target circuit that is the target of off-leakage current reduction and to reduce the overall current consumption, a resistance element is inserted into the power supply line of the target circuit in the standby state of the target circuit, and the resistance element is turned on. Off-leakage is reduced by switching / off and controlling the resistance value.

<First Embodiment>
FIG. 1 is a circuit diagram showing a first embodiment of a power consumption reduction circuit of the present invention. In FIG. 1, reference numeral 10 denotes a target circuit that is a target for reducing off-leakage current. Specifically, it is a logic circuit that requires a standby state, a storage circuit that requires a resume function for holding internal data, or the like. Reference numeral 11 denotes a power supply terminal for supplying power to the target circuit 10. For example, a battery power supply 12 is connected to the power supply terminal 11. In a power supply line 13 between the power supply terminal 11 and the power supply node of the target circuit 10, a resistance element R for reducing leakage current is inserted in series. A resistance bypass switch element SW is connected in parallel with the resistance element R, and this switch element SW is on / off controlled in accordance with the normal operation mode / standby mode (standby state) of the target circuit 10. . When the power consumption reduction circuit is applied to an LSI, each component is formed on the same semiconductor chip, and a battery power supply 12 outside the chip is connected to the power supply terminal 11.

  In the power consumption reduction circuit having the above configuration, the switch element SW is controlled to be in an on state during normal operation. In this case, there is no voltage drop due to the resistance element R, and the voltage of the battery power supply 12 (power supply voltage VDD) is supplied to the target circuit 10 almost as it is. At this time, the resistance element R does not affect the actual operation of the target circuit 10.

  On the other hand, when the target circuit 10 is in the standby state, the switch element SW is controlled to be in the OFF state, and the resistance element R is inserted in series with the power supply line of the target circuit 10. Thereby, a voltage drop occurs between both ends of the resistance element R due to the leakage current of the target circuit 10 flowing in the power supply line 13, and the leakage current flowing in the power supply line 13 can be reduced. That is, the resistance value between the power source and the ground is the sum of the off-resistance of the target circuit 10 and the resistance element R, and the power consumption due to the leakage current can be reduced according to the increase in the resistance value due to the resistance element R. . In this case, the power supply voltage applied to the target circuit 10 is lower than the power supply voltage VDD by the voltage drop caused by the resistance element R.

  2 replaces the battery power supply 12 in FIG. 1 with a capacitor model, and simulates the discharge characteristics of the battery power supply in the standby state of the target circuit 10 (relationship between relative time and battery voltage, off-leakage of the target circuit). A discharge curve A is shown in comparison with a conventional discharge curve B in which the resistance element R and the switch element SW are not inserted in the power supply line.

  As can be seen from FIG. 2, in the discharge curve A of the power consumption reduction circuit of the present embodiment, the initial value 1.50 V of the battery power supply 12 in the standby state of the target circuit 10 decreases from 1.50 V over time. is doing. That is, the voltage drop amount is about 0.35V. This is about 30% compared to the voltage drop amount (about 1.20 V) from 1.50 V to 0.30 V in the discharge curve B of the conventional example, and the discharge characteristics are greatly improved. In other words, it can be seen that the off-leakage current in the standby state of the target circuit 10 is greatly reduced.

  According to the power consumption reduction circuit described above, by adding a simple circuit, the power consumption can be reduced by reducing the off-leak current in a logic circuit that requires a standby state, a memory circuit that requires a resume function, or an LSI incorporating them. It becomes possible to do. For example, when a battery power source is used as the power source, the life of the battery is greatly extended compared to the conventional circuit, and the battery can be used for a long time.

<Second Embodiment>
In a target circuit that needs to hold an internal state, for example, a static semiconductor memory (SRAM), it is necessary to always apply a power supply voltage in order to hold internal data. Further, the minimum power supply voltage at this time is also determined, and there is a limit value of the power supply voltage that can hold data. When the battery power is consumed due to the off-leakage current flowing in the SRAM, the power supply voltage gradually decreases and is applied to the SRAM when the switch element SW is turned off in the standby state as in the first embodiment described above. The power supply voltage is lower than the power supply voltage by the voltage drop in the resistance element R. That is, the power supply voltage applied to the SRAM by this voltage drop approaches the voltage that can be held internally, so the margin for the lowest power supply voltage that can be held internally is reduced, and internal data can no longer be held. Note that if the switch element SW is kept on when the SRAM is in the standby state, the margin for the minimum power supply voltage is large, but the original leakage current flows into the SRAM, and if the off-leakage current is large, the power consumption speed of the battery power supply Will be faster.

  In order to solve the above-described problem, in the second embodiment, as a leakage current reduction method for a target circuit that needs to maintain an internal state, a switching element SW for bypassing a resistance element R for reducing leakage current is provided. Control to dynamically switch on / off.

  FIG. 3 is a circuit diagram showing a second embodiment of the power consumption reduction circuit according to the present invention. The target circuit 10a is a storage circuit such as an SRAM, and is used with a battery power supply 12 connected to the power supply terminal 11, for example. The

  FIG. 4 is a flowchart showing an example of sequence control in the power consumption reduction circuit of FIG. The circuit shown in FIG. 3 is different from the circuit described above with reference to FIG. 1 in that the voltage monitor circuit 31 that monitors the voltage of the power supply terminal 11 and the monitoring result of the voltage monitor circuit 31 in the standby state of the target circuit 10a. Based on this, a control circuit 32 for controlling on / off of the switch element SW is added. For example, the control circuit 32 is configured by an analog circuit, for example, a resume function control microcomputer (not shown) mounted in the same LSI so that the sequence control shown in FIG. 4 is possible. Or the like. If a microcomputer is used as the control circuit 32, complicated control can be easily realized. However, it is necessary to always supply a required power supply voltage to the microcomputer so that it can always operate.

  Next, the operation of the power consumption reduction circuit of FIG. 3 will be described with reference to FIG. This power consumption reduction circuit is configured so that the power supply voltage of the power supply terminal 11 can be monitored by the voltage monitor circuit 31 when the target circuit 10a enters the standby state. When the monitor value is higher than the threshold value VREF, the control circuit 32 compares the monitored value monitored by the voltage monitor circuit 31 with a preset threshold value (a value about the data retention limit voltage) VREF in an analog manner. In this case, it is determined that data can be retained even if there is a voltage drop due to the resistance element R, and the switch element SW is turned off to further reduce the off-leakage current.

  On the other hand, when the monitor value is lower than the threshold value VREF, the control circuit 32 determines that data cannot be held due to a voltage drop caused by the resistance element R, turns on the switch element SW, and turns on the resistance element R. To bypass. That is, the determination of switching on / off of the switch element SW in the first embodiment is performed based on the monitor value of the power supply voltage at that time, and by properly using them, the power consumption due to the off-leak current is further reduced. It becomes possible.

<Modification Example 1 of Second Embodiment>
In the second embodiment described above, the case where the on / off state of the switch element SW is determined when the standby state request is received and the standby state is entered is described. However, the present invention is not limited to this, and the power supply voltage is monitored during the standby state. However, the sequence control of the control circuit 32 can be arbitrarily changed as long as the switch element SW is configured to switch accordingly.

  For example, in the sequence control shown in the flowchart of FIG. 5, the power supply voltage is always monitored during the standby state, and the switch element SW is dynamically changed when an operation resumption request is received, compared with the sequence control shown in the flowchart of FIG. Is switched.

<Third Embodiment>
In the second embodiment described above, the value of the resistance element R for reducing the leakage current is a fixed value determined at the time of manufacture, and only controls whether the switch element SW for resistance bypass is turned on / off. That is, a voltage monitor circuit is prepared, and if the power supply voltage is close to the data retention limit voltage of the target circuit 10a, the switch element SW is controlled to be in the ON state, and the value of the resistance element R for reducing the leakage current is This is equivalent to the case where only two types of a certain value and zero are prepared. In the third embodiment, the leakage current countermeasure according to the second embodiment is further advanced, and the resistance value for reducing the leakage current is dynamically associated with the limit voltage value of the data holding function by the monitor value of the power supply voltage in the standby state. The case where it is made to change finely is demonstrated.

  FIG. 6A is a circuit diagram showing a third embodiment of the power consumption reduction circuit of the present invention, and FIG. 6B is a leakage current reduction resistor in the power consumption reduction circuit of FIG. A relationship between a plurality of threshold values prepared as a reference for switching values and a data retention limit voltage of the target circuit is shown. FIG. 7 shows a flowchart of sequence control in the power consumption reduction circuit of FIG.

  In the circuit of FIG. 6A, the power source line 13 of the target circuit 10a is connected to several resistance elements R for reducing leakage currents having different resistance values, in this example, six resistance elements R1, R2, R3, R4, R5 and R6 are inserted in series, and switch elements for selecting and controlling them, in this example, six switch elements SW1 to SW6 are connected in parallel, and a leakage current according to the monitor value of the power supply voltage by the voltage monitor circuit The switch elements SW1 to SW6 are switched and controlled by a control circuit (not shown) so as to select a desired resistance value as the reduction resistance. In this case, as shown in FIG. 7, when the monitor value of the power supply voltage is higher than the threshold value 1, all the switch elements SW1 to SW6 are turned off so that the leakage current is reduced. In this state, if the monitor value of the power supply voltage decreases and becomes lower than the threshold value 1 and it becomes difficult to hold data in the target circuit 10a with the current resistance value, the monitor value is the threshold value 2 (<threshold value 1). If it is higher than that, for example, the switch element SW1 is turned on, and the resistance value is made slightly smaller than before so that data can be retained. In this state, if the monitor value of the power supply voltage further decreases and becomes lower than the threshold value 2 and it becomes difficult to hold data in the target circuit 10a with the current resistance value, the monitor value becomes the threshold value 3 (<threshold value 2). ), For example, the switch element SW2 is turned on, and the resistance value is made slightly smaller than before to enable data retention. Hereinafter, in the same manner, the resistance value for reducing the leakage current is dynamically reduced in detail in association with the limit voltage value of the data holding function according to the monitor value.

  Unlike the second embodiment described above, such control does not simply control the resistance value for reducing the leakage current to zero in the standby state, so that the battery life is the same as that of the second embodiment described above. Even longer. By repeating this operation as the power supply voltage is lowered and switching the resistance value of the power supply line little by little, it is possible to further reduce the power consumption while continuing the data holding function. As a result, it becomes possible to use the battery for a longer time than in the past, and the life of the battery can be greatly extended. The power consumption reduction circuit according to the present embodiment does not require a large measure related to the manufacturing process, and can be realized with little cost increase.

  Note that the switching of the resistance value of the leakage current reducing resistor may be performed only at the time of transition to the standby state. Further, for example, as in the sequence control shown in FIG. It may be monitored and dynamically executed when an operation resumption request is received in the process.

<Modification of Third Embodiment>
In the above-described second embodiment, several resistance elements for reducing leakage current having different resistance values are provided in series, and switch elements for selecting and controlling them are connected in parallel, and according to the monitor value of the power supply voltage. However, the present invention is not limited to this, and a variable resistance element is used as the resistance element, and the resistance value of the variable resistance element is used as a monitor value of the power supply voltage. You may deform | transform so that it may change according to it.

  FIG. 8 is a circuit diagram showing a modification of the third embodiment. The target circuit 10a is a storage circuit such as an SRAM, and is used with a battery power supply 12 connected to the power supply terminal 11, for example. In this circuit, for example, an NMOS transistor 81 is inserted in series as a variable resistance element in the power supply line of the target circuit 10a with respect to the circuit described above with reference to FIG. 6, and the voltage of the battery power supply 12 is applied to the gate thereof. Thus, the variable resistance element is changed to a desired resistance value according to the monitor value of the power supply voltage.

  9 shows a discharge curve A3 showing the result of simulating the discharge characteristics of the battery power supply in the standby state by replacing the battery power supply 12 with a capacitor model in the power consumption reduction circuit of FIG. 8, and the first embodiment shown in FIG. The discharge curve A1 is shown in comparison with the discharge curve A2 of the second embodiment shown in FIG. According to FIG. 9, in the power consumption reduction circuit according to the present embodiment, the time required from the initial value 1.50V of the battery power supply 12 in the standby state of the target circuit 10a to 0.85V as time elapses. It becomes longer and the discharge characteristics become gradual. In other words, it can be seen that the life of the battery power source is prolonged.

The circuit diagram of 1st Embodiment of the power consumption reduction circuit of this invention. The characteristic view which shows the discharge curve A which shows the result of having simulated the discharge characteristic of the battery in the standby state of the target circuit in FIG. 1 with the discharge curve B of a prior art example. The circuit diagram of 2nd Embodiment of the power consumption reduction circuit of this invention. 4 is a flowchart showing an example of sequence control in the power consumption reduction circuit of FIG. 3. 4 is a flowchart showing another example of sequence control in the power consumption reduction circuit of FIG. 3. The circuit diagram of the third embodiment of the power consumption reduction circuit of the present invention and the relationship between the threshold value prepared as a reference for switching the leakage current reduction resistance value in the power consumption reduction circuit and the data retention limit voltage of the target circuit. FIG. The flowchart which shows an example of the sequence control in the power consumption reduction circuit of FIG. The circuit diagram of the modification of 3rd Embodiment. 8 is compared with the discharge curve A1 of the power consumption reduction circuit of FIG. 1 and the discharge curve A2 of the power consumption reduction circuit of FIG. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10a ... Target circuit, 11 ... Power supply terminal, 12 ... Battery power supply, 31 ... Voltage monitor circuit, 32 ... Control circuit, R ... Resistance element, SW ... Switch element.

Claims (5)

A target circuit having a resume function for holding an operation standby state or internal data;
A power supply terminal for supplying power to the target circuit;
A resistance element inserted in series in a power supply line between the power supply terminal and a power supply node of the target circuit;
A power consumption reduction circuit comprising: a switching element connected in parallel to the resistance element and controlled to be turned on / off in accordance with a normal operation mode / operation standby mode of the target circuit. A voltage monitor circuit for monitoring the voltage of the power supply terminal;
2. The power consumption reduction circuit according to claim 1, further comprising: a control circuit that turns on the switching element based on a monitoring result of the voltage monitoring circuit in an operation standby mode of the target circuit. As the resistance element, a resistance element capable of selecting a plurality of resistance values or a resistance element capable of changing the resistance value is used.
A voltage monitor circuit for monitoring the voltage of the power supply terminal;
The power consumption reduction circuit according to claim 1, further comprising: a control circuit that changes a resistance value of the resistance element based on a voltage of the power supply terminal in an operation standby mode of the target circuit.   4. The power consumption reduction circuit according to claim 1, wherein the power consumption terminal is formed on a semiconductor chip, and the power supply terminal is connected to a power supply outside the chip. 5.   The power consumption reduction circuit according to claim 1, wherein the power source is a battery power source.

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