JP2007259505A - Digital broadcast signal transmitter, and receiving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform stable reproduction by improving resistance against a transmission path error for a control signal concerning transmission, e.g. TMCC (Transmission Multiplexing Configuration Control) signal. <P>SOLUTION: A digital broadcast signal receiver receives a digital broadcast signal in which a control signal (TMCC signal) concerning a transmission system is transmitted together with a main signal. In the receiver, a signal received is demodulated in a demapping circuit 43, and the TMCC signal and the main signal are decoded in a viterbi decoding circuit 44. A TMCC decoder 47 decodes the TMCC signal from a signal output from the viterbi decoding circuit 44 and input via a deinterleaving circuit 45 and a reed solomon decoding circuit 46, extracts transmission control information such as a modulation system or a coding rate of the main signal, and outputs the information to the demapping circuit 43 and the viterbi decoding circuit 44. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a digital broadcast signal receiving apparatus and method, and more particularly to a digital broadcast that receives a control signal related to a transmission system, for example, a digital broadcast signal in which a so-called TMCC (Transmission Multiplexing Configuration Control) signal and a main signal are transmitted together. The present invention relates to a signal receiving apparatus and method.

  Digital multi-channel broadcasting using a communication satellite (hereinafter abbreviated as CS) has begun in earnest and various services have been started. In the future, it is also being considered to provide digital broadcasting services for broadcasting satellites (hereinafter abbreviated as BS).

  Since BS has higher power than CS, it has been studied to use a modulation scheme having higher transmission efficiency than the QPSK modulation scheme conventionally used in CS. The bit stream to be transmitted is based on a so-called transport stream (hereinafter abbreviated as TS) defined by MPEG2 Systems from the viewpoint of compatibility with other media such as CS, terrestrial waves, and cables. Has been proposed. This TS is composed of 188-byte TS packets including 1-byte synchronization byte. In CS digital multi-channel broadcasting, terrestrial digital broadcasting, cable digital broadcasting, etc., this TS has 16 bytes for error correction. Since the Reed-Solomon code (hereinafter abbreviated as RS code) with the parity of 1 is used, it is proposed that the RS (204, 188) is encoded in the TS even in BS digital broadcasting.

  In this BS digital broadcasting, a convolutionally encoded BPSK (Binary Phase Shift Keying) signal or QPSK is transmitted to a main signal portion that transmits payload information excluding a synchronization portion of an RS (204, 188) encoded TS packet. (Quadrature Phase Shift Keying) signal, or trellis-coded 8PSK (Phase Shift Keying) (hereinafter abbreviated as TC (Trellis-Coded) 8PSK), and transmission information such as modulation scheme and coding rate is transmitted in TS packets. A method of transmitting by BPSK using a synchronization unit has been proposed.

  In particular, if so-called pragmatic TC8PSK is used as TC8PSK, an encoding circuit and a decoding circuit similar to the conventional convolutional code can be used, so that signals such as BPSK, QPSK, and 8PSK that transmit payload information are received by the receiving device. In the case of demodulation, the same Viterbi decoder can be used when demodulating any signal, which is advantageous in terms of hardware configuration.

  FIG. 1 shows a configuration example of such a currently proposed BS digital broadcast transmitter. A 16-byte parity is added to the 188-byte TS packet by RS (204, 188) encoding. Forty-eight packets are collected into one frame.

  The first one synchronization byte of the 48 packets of each frame is sequentially read out and input to the frame synchronization and TMCC generation circuit 81. The frame synchronization and TMCC generation circuit 81 replaces the synchronization bytes of the first two TS packets with frame synchronization signals. Also, the frame synchronization and TMCC generation circuit 81 replaces the synchronization bytes of the third and subsequent TS packets with TMCC (Transmission Multiplexing Configuration Control) signals. This TMCC signal includes transmission control information such as a modulation method and a coding rate of a main signal described later. As a result, two synchronization bytes of the first two packets out of 48 packets constituting one frame are replaced with frame synchronization signals, and synchronization bytes of the third and subsequent packets are replaced with TMCC signals. Will be. The frame synchronization signal and TMCC signal generated by the frame synchronization and TMCC generation circuit 81 are input to the BPSK mapping circuit 82 and mapped to predetermined signal points.

  The main signal of the first two TS packets in one frame is an image signal LQ for a low hierarchy, and this signal is interleaved by an interleave circuit 83 within the range of the two TS packets. The signal is input to the convolutional coding circuit 84 and subjected to convolutional coding at a coding rate of 1/2. The convolutionally encoded signal is punctured to have a coding rate of 3/4 and supplied to the QPSK mapping circuit 85. The QPSK mapping circuit 85 maps to a predetermined signal point using the QPSK method.

  On the other hand, the main signal of the remaining 46 TS packets among the 48 packets constituting one frame is an image signal HQ for a high layer, and this signal is input to the interleave circuit 86 and interleaved. Thereafter, the signal is encoded by the 2/3 trellis encoding circuit 87 and further mapped to the signal point by the 8PSK mapping circuit 88. If so-called pragmatic trellis encoding is performed in the 2/3 trellis encoding circuit 87, the convolutional encoding circuit 84 and the 2/3 trellis encoding circuit 87 can be a common circuit.

  The multiplexing circuit 89 multiplexes and outputs the outputs of the BPSK mapping circuit 82, the QPSK mapping circuit 85, and the 8PSK mapping circuit 88 in units of frames. Therefore, in each frame signal output from the multiplexing circuit 89, a BPSK-modulated frame synchronization signal and a TMCC signal are first arranged, and then a QPSK-modulated low-layer main signal LQ is arranged. Finally, a format in which a main signal HQ for a higher hierarchy that is finally 8PSK modulated is arranged.

  On the receiving side, after synchronizing the carrier wave and the clock, the received signal sequence is monitored to detect the BPSK-modulated frame synchronization signal and establish the frame synchronization. Since this frame synchronization signal is followed by BPSK-modulated TMCC, if frame synchronization is established, a signal next to the frame synchronization signal can be received and demodulated as a BPSK signal to obtain a TMCC signal. By interpreting the contents of this TMCC signal, it is possible to know the transmission control information such as the modulation method and coding rate of the symbol of the main signal part that transmits the payload information that is subsequently transmitted after the TMCC signal. The main signal can be received and the inner code can be decoded.

  After that, the frame synchronization signal and TMCC signal in the demodulated signal are replaced with the TS synchronization signal as before, and RS (204, 188) encoding consisting of a 1-byte synchronization signal and a 203-byte main signal is performed. It is possible to obtain the transmitted TS by returning to the received TS and further decoding this RS code.

  FIG. 2 shows an example of such synchronization processing. First, in step S1, the process waits until the first frame synchronization signal is detected, and when it is detected, in step S2, it is determined whether or not the second frame synchronization signal is detected. When the second frame synchronization signal is detected, the process proceeds to step S3, and it is determined whether or not the third frame synchronization signal is detected. When the third frame synchronization signal is detected, the process proceeds to step S4, and it is determined whether or not the fourth frame synchronization signal is detected. As described above, when the frame synchronization signal is continuously detected for the four frames, the frame synchronization establishment process is executed in step S5 assuming that the frame synchronization is established.

  If it is determined in step S2 that the second frame synchronization signal has not been detected after the first frame synchronization signal is detected, the process proceeds to step S6, and the third frame synchronization signal is detected. It is determined whether or not it has been done. If it is determined that the third frame synchronization signal has been detected, the process proceeds to step S7, where it is determined whether or not the fourth frame synchronization signal has been detected. If the fourth frame synchronization signal is detected, the process further proceeds to step S8 to determine whether or not the fifth frame synchronization signal is detected. As described above, even if the second frame synchronization signal is not detected after the first frame synchronization signal is detected, the frame synchronization signal is subsequently detected three times. Advances to step S5, and frame synchronization establishment processing is executed.

  When it is determined in step S6 that the frame synchronization signal has not been detected twice consecutively after the first frame synchronization signal is detected, the process returns to step S1 and the subsequent processing is repeatedly executed. .

  If the second frame synchronization signal cannot be detected after the first frame synchronization signal is detected, but the third frame synchronization signal can be detected, in step S7 If it is determined that the fourth frame synchronization signal has not been detected, the process proceeds to step S9, where it is determined whether or not the fifth frame synchronization signal has been detected. Therefore, when it is determined that the fifth frame synchronization signal has been detected, the process further proceeds to step S10 to determine whether or not the sixth frame synchronization signal has been detected. Here, when it is determined that the sixth frame synchronization signal has been detected, the process proceeds to step S5, and frame synchronization establishment processing is executed. If it is determined in step S9 or step S10 that no frame synchronization signal has been detected, the process returns to step S1 and the subsequent processing is repeatedly executed.

  If it is determined in step S3 that the third frame synchronization signal has not been detected after it has been determined that the frame synchronization signal has been detected twice consecutively, the process proceeds to step S7. Subsequent processing is executed. After the frame synchronization signal has been detected three times in succession, if it is determined in step S4 that the fourth frame synchronization signal has not been detected, the process proceeds to step S8, and thereafter The process is executed.

  If it is determined in step S8 that the fifth frame synchronization signal has not been detected, the process proceeds to step S10, and the subsequent processing is executed.

  As described above, in a state where frame synchronization is established, the TMCC signal and the main signal can be accurately demodulated with reference to the frame synchronization signal.

  Note that the processing up to the establishment of frame synchronization is referred to as backward protection.

  If it is determined that the frame synchronization is established by the above backward protection, it is confirmed in step S11 that the frame synchronization signal is continuously detected. In step S11, the frame synchronization is detected in a predetermined frame. If it is determined that the signal (assumed to be nth) could not be detected, the process proceeds to step S12, and it is determined whether or not the (n + 1) th frame synchronization signal has been detected. If it is determined in step S12 that the (n + 1) th frame synchronization signal cannot be detected, it is further determined in step S13 whether or not the (n + 2) th frame synchronization signal is detected. If not detected, it is further determined in step S14 whether or not the (n + 3) th frame synchronization signal has been detected. As described above, when it is determined that the frame synchronization signal cannot be detected continuously for four frames, the process proceeds to step S15, and the out-of-synchronization process is executed assuming that the frame synchronization is lost. Thereafter, the process returns to step S1, and the subsequent processing is executed.

  After determining that the nth frame synchronization signal has not been detected, if it is determined in step S12 that the (n + 1) th frame synchronization signal has been detected, the process proceeds to step S16, where the (n + 2) th frame is detected. It is determined whether or not a synchronization signal has been detected. When the (n + 2) -th frame synchronization signal is detected, it is only possible to detect the frame synchronization signal for one frame, so the process returns to step S11 and the subsequent processing is executed. .

  If it is determined in step S16 that the (n + 2) th frame synchronization signal cannot be detected, it is determined in step S17 whether or not the (n + 3) th frame synchronization signal has been detected. If it is determined that the (n + 3) th frame synchronization signal has not been detected, it is determined in step S18 whether or not the (n + 4) th frame synchronization signal has been detected. If it is determined that the (n + 4) th frame synchronization signal has not been detected, it means that the frame synchronization signal has not been detected three times in succession. Executed.

  If it is determined in step S17 that the (n + 3) th frame synchronization signal has been detected, it is determined in step S19 whether or not the (n + 4) th frame synchronization signal has been detected. If the (n + 4) th frame synchronization signal cannot be detected, the process proceeds to step S20, and it is determined whether or not the (n + 5) th frame synchronization signal has been detected. If it is determined that the (n + 5) th frame synchronization signal could not be detected, the process proceeds to step S15, and the synchronization loss process is executed.

  If it is determined in step S19 or step S20 that a frame synchronization signal has been detected, the process returns to step S11.

  If it is determined in step S13 that the (n + 2) -th frame synchronization signal has been detected after the frame synchronization signal cannot be detected twice in succession, the process proceeds to step S17. The subsequent processing is executed. After it is determined that the frame synchronization signal has not been detected three times in succession, if it is determined in step S14 that the (n + 3) th frame synchronization signal has been detected, the process proceeds to step S18. Proceed and subsequent processing is executed.

  If it is determined in step S18 that the (n + 4) th frame synchronization signal has been detected, the process proceeds to step S20, and the subsequent processing is executed.

It should be noted that the protection operation until frame synchronization is detected after frame synchronization is established is referred to as forward protection.

  As described above, RS (204, 188) encoding is performed on a 188-byte TS packet, and further, convolutional encoding and trellis encoding are performed as inner codes, and error correction for transmission path errors is performed. It has been made possible. On the other hand, the TMCC signal is required to be more resistant to transmission path errors than the main signal in order to transmit transmission control information to the receiving side. In the proposed scheme, this requirement is met by using BPSK, which is the most advantageous modulation scheme for transmission path errors among various modulation schemes.

  However, sufficient error tolerance cannot be obtained by BPSK modulation alone, and more powerful error correction processing is required for TMCC signals.

  The present invention has been made in view of such a situation, and further enhances resistance to transmission path errors, and stably and at high speed, a control signal related to a transmission system such as a TMCC signal. It is an object of the present invention to provide a digital broadcast signal receiving apparatus and method capable of reproducing the program.

  In the digital broadcast signal receiving apparatus and method according to the present invention, a main signal is transmitted in a payload portion of a transport packet, a frame is formed by a predetermined number of transport packets, and at least a synchronization portion of a transport packet in the frame A part is replaced with an m-bit frame synchronization signal, a control signal related to a transmission system, and a Reed-Solomon code generated for a control signal for a plurality of frames. In the first frame, the frame synchronization signal and the control signal In the second frame, in the second frame, a signal based on each signal in the order of the frame synchronization signal and the Reed-Solomon code is provided for the main signal. When receiving a digital broadcast signal transmitted with intra-correction encoding, decode the error-correction inner code for the output signal of the demodulation circuit. Performs management, decodes the Reed-Solomon code error correction in encoding processing is applied, based on a control signal outputted in processing the Reed-Solomon decoding to identify the modulation scheme and coding rate of the main signal.

  The main signal is modulated and transmitted by a modulation method selected from a plurality of modulation methods, and the control signal preferably includes information for specifying the modulation method applied to the main signal. .

  Another example is replacing received data corresponding to the synchronization unit of the received signal with a predetermined value.

  According to the digital broadcast signal receiving apparatus and method of the present invention, after demodulating a digital broadcast signal in which a control signal (for example, a TMCC signal) related to a transmission system is transmitted together with the main signal, the control signal and the main signal Since Viterbi decoding is performed, the control signal can be stably reproduced on the receiving side even if the C / N is low.

  Hereinafter, preferred embodiments of a digital broadcast signal receiving apparatus and method according to the present invention will be described with reference to the drawings.

  FIG. 3 shows a configuration example of a digital broadcast signal transmitting apparatus for sending a digital broadcast signal to the digital broadcast signal receiving side to which the present invention is applied. The memory 1 stores a TMCC signal including transmission control information. The synchronization register 2 stores a frame synchronization signal. The multiplexing circuit 3 reads out the frame synchronization signal or the TMCC signal from the synchronization register 2 and the memory 1 at a predetermined timing to be described later, multiplexes them, and outputs them to the Reed-Solomon encoding circuit 4.

  The Reed-Solomon encoding circuit 4 performs RS (48, 38) encoding on the frame synchronization signal and TMCC signal input from the multiplexing circuit 3 and outputs them to the interleave circuit 5. The interleave circuit 5 interleaves the signal input from the Reed-Solomon encoding circuit 4 and then outputs it to the multiplexing circuit 9. The interleave circuit 5 improves error correction capability by distributing errors in the subsequent convolutional encoding circuit 10 and performing RS decoding on the receiving side.

  On the other hand, TS including the main signals of the low hierarchy image signal LQ and the high hierarchy image signal HQ are input to the Reed-Solomon encoding circuits 6 and 13, respectively. In the Reed-Solomon encoding circuits 6 and 13, the TS is Reed-Solomon encoded and output to and stored in the memories 7 and 14, respectively. At this time, the TS synchronization bytes are not written in the memories 7 and 14. The TS read from the memories 7 and 14 are interleaved by the interleave circuits 8 and 15, respectively, and then input to the multiplexing circuit 9.

  The multiplexing circuit 9 multiplexes the frame synchronization signal and the TMCC signal input from the interleave circuit 5 with the main signal input from the interleave circuits 8 and 15 so as to form a frame, and outputs the multiplexed signal. . As in the above-described FIG. 1, the frame structure is such that the frame synchronization signal and the TMCC signal are arranged first, followed by the main signal LQ for the lower layer, and finally the main signal HQ for the higher layer. The

  The convolutional encoding circuit 10 performs a convolutional encoding process suitable for each signal in the frame supplied from the multiplexing circuit 9 and outputs the result to the mapping circuit 11 as will be described later. The mapping circuit 11 performs a process of mapping the multiplexed signal supplied from the convolutional encoding circuit 10 to a signal point of a modulation method such as BPSK modulation, QPSK modulation, or 8PSK modulation corresponding to each signal.

  4 to 6 show how signal points are mapped. 4 shows mapping signal points in the case of the BPSK modulation method, FIG. 5 shows the case of the QPSK modulation method, and FIG. 6 shows the mapping in the case of the 8PSK modulation method. As shown in FIG. 4, in the case of the BPSK modulation method, mapping is performed on two signal points having a phase difference of 180 degrees. In the case of the QPSK modulation method, as shown in FIG. 5, mapping is performed on four signal points each having a phase difference of 90 degrees. In the case of the 8PSK modulation system, as shown in FIG. 6, mapping is performed on 8 signal points each having a phase difference of 45 degrees.

  The controller 12 controls operations of the multiplexing circuit 3, the multiplexing circuit 9, the convolutional encoding circuit 10, and the mapping circuit 11.

  Next, the operation will be described. As shown in FIG. 7, the signals input to the Reed-Solomon encoding circuits 6 and 13 are TS packets in which the first byte is a synchronization signal and the subsequent 187 bytes are composed of image data. This image data is image data LQ for a low hierarchy or image data HQ for a high hierarchy. The image data LQ for the low hierarchy is image data necessary for reproducing a minimum low-quality image, and the image data HQ for the high hierarchy is necessary for reproducing an image with a higher resolution. Image data. The Reed-Solomon encoding circuit 6 is supplied with image data LQ for two frames of low packets for one frame, and the Reed-Solomon encoding circuit 13 is supplied with image data for high layers of 46 packets for one frame. HQ is supplied.

  The Reed-Solomon encoding circuits 6 and 13 perform RS (204, 188) encoding processing on each packet, add 16-byte parity, and supply and store them in the memories 7 and 14, respectively. At this time, the 1-byte synchronization signal of each packet is not written in the memories 7 and 14. The image signals written in the memories 7 and 14 are read by the interleave circuits 8 and 15, subjected to predetermined interleave processing, and then supplied to the multiplexing circuit 9.

  On the other hand, a TMCC signal including transmission control information is supplied to the memory 1 and stored therein. The multiplexing circuit 3 reads, multiplexes and reads the frame synchronization signal stored in the synchronization register 2 and the TMCC signal stored in the memory 1 at a predetermined timing under the control of the controller 12. Output to the Solomon encoding circuit 4. The frame synchronization signal is composed of 2 bytes, and the multiplexing circuit 3 reads the 2-byte frame synchronization signal, reads the 10-byte TMCC signal from the memory 1, and outputs it to the Reed-Solomon encoding circuit 4. The process is repeatedly executed for each frame. That is, in this configuration example, a 2-byte frame synchronization signal and a 10-byte TMCC signal are transmitted in one frame. The Reed-Solomon encoding circuit 4 performs RS (48, 38) encoding processing, and adds one frame of parity to the three frames of data supplied from the multiplexing circuit 3.

  In the case of the configuration example of FIG. 1 described above, 192 BP symbols (192 bits) per frame are assigned to the frame synchronization signal and the TMCC signal. That is, the number of symbols per frame at the output stage of the BPSK mapping circuit 82 in FIG. 1 is 192 symbols. The number of symbols per frame assigned to the frame synchronization signal and the TMCC signal does not change even when the present invention is implemented. That is, the convolutional encoding circuit 10 performs convolutional encoding processing with a coding rate of ½ on both the frame synchronization signal and the TMCC signal, so in the stage before performing the convolutional encoding processing, one frame per frame. The amount of information that can be allocated to the synchronization signal and the TMCC signal is 96 (= 192/2) bits, that is, 12 bytes (the breakdown is that the frame synchronization signal is 2 bytes and the TMCC signal is 10 bytes as described above). Become. The Reed-Solomon encoding circuit 4 adds parity for one frame to the data for three frames supplied from the multiplexing circuit 3, and uses a total of four frames of data (48 bytes of data) to generate a Reed-Solomon code. The process which comprises is performed.

  That is, 3 frames (36 bytes) of signals consisting of a 2-byte frame synchronization signal and a 10-byte TMCC signal are collected per frame, and a 2-byte frame synchronization signal of the fourth frame is added thereto. 10 bytes of parity is added to 38 (= 36 + 2) bytes of information, and RS (48, 38) is encoded. As a result, the output of the Reed-Solomon encoding circuit 4 is as shown in FIG. As a result, a TMCC signal of 30 bytes (240 bits) can be transmitted in 4 frames.

  In this configuration example, Reed-Solomon encoding is performed on both the frame synchronization signal and the TMCC signal. However, Reed-Solomon encoding may be performed only on the TMCC signal. In this case, RS (40, 30) encoding is performed.

  The interleaving circuit 5 performs a predetermined interleaving process on the signal ((A) in FIG. 8) supplied from the Reed-Solomon encoding circuit 4 and outputs the result to the multiplexing circuit 9. As shown in FIG. 8B, this signal is a signal in which the position of the 2-byte synchronization signal is not changed, but the TMCC signal and parity are interleaved at a predetermined position.

  FIG. 9 shows a configuration example of the interleave circuit 5. The interleave circuit 5 is a convolution type, and in this configuration example, an input signal is input to any one of the contacts 31-1 to 31-6 by the switch 31, and from the contacts 32-1 to 32-6. The signal is output via the switch 32. The contacts 31-1 and 32-1 are directly connected, and a delay unit 33-1 is inserted between the contacts 31-2 and 32-2. Delay units 33-2 and 33-3 are inserted between the contact 31-3 and the contact 32-3, and delay units 33-4 to 33-6 are inserted between the contact 31-4 and the contact 32-4. Is inserted between the contact 31-5 and the contact 32-5, and the delay unit 33-11 is inserted between the contact 31-6 and the contact 32-6. Thru 33-15 are inserted. Each delay unit is configured to give a delay of 8 bytes.

  The switch 31 and the switch 32 are configured to be switched to the corresponding contact every two bytes in synchronization.

  At the timing when a 2-byte frame synchronization signal is input from the Reed-Solomon encoding circuit 4, the switches 31 and 32 are switched to the uppermost contacts 31-1 and 32-1 in FIG. Therefore, the frame synchronization signal is output as it is without being delayed (interleaved).

  On the other hand, when a 10-byte TMCC signal following the frame synchronization signal is input, the switches 31 and 32 are sequentially switched every 2 bytes from the top to the bottom contact in FIG. It is done. As a result, of the 10-byte TMCC signal, the first 2-byte signal is delayed by one delay unit (8 bytes), and the second 2-byte TMCC signal is by two delay units. Receive a delay of (16 bytes). Similarly, the third to fifth 2-byte TMCC signals are delayed by three delay units (24 bytes), four (32 bytes), or five (40 bytes), respectively. Is output.

  The position of the frame synchronization signal needs to be prevented from changing by the interleaving process of the interleave circuit 5. When the interleave circuit 5 is a convolutional interleave circuit, not only is it easy to store the position of the synchronization signal, but the circuit scale can be reduced as compared with a block type interleave circuit.

  When the switches 31 and 32 of the interleave circuit 5 are switched in units of bytes, burst errors can be more efficiently distributed. However, doing so increases the hardware. Therefore, in order to perform interleaving with smaller hardware without changing the position of the synchronization signal, it is preferable to perform interleaving in units of 2 bytes.

  The multiplexing circuit 9 adds the frame synchronization signal and TMCC signal for one frame supplied from the interleave circuit 5 to the head of the main signal for one frame (48 packets) supplied from the interleave circuits 8 and 15. Multiplexed as shown in FIG. 10 and output to the convolutional coding circuit 10.

  Under the control of the controller 12, the convolutional encoding circuit 10 receives a frame synchronization signal or a TMCC signal from the multiplexing circuit 9, and transmits the frame synchronization signal or TMCC signal with a BPSK with an encoding rate of 1/2. A 1/2 convolutional encoding process is performed. When the main signal supplied from the multiplexing circuit 9 is a high-layer image signal HQ, the convolutional coding circuit 10 performs trellis coding on the main signal at a coding rate of 2/3. In this case, when transmitting by pragmatic TC8PSK, the input from the multiplexing circuit 9 is converted into 2 bits in parallel, 1 bit is left as it is, and the other 1 bit is a convolutional code with a coding rate of 1/2. To obtain a 2-bit code. Then, the outputs of a total of 3 bits are output in parallel to the mapping circuit 11.

  When the main signal is a low-layer image signal LQ, the convolutional coding circuit 10 performs convolutional coding processing at a coding rate of 1/2 in order to transmit at a coding rate of 3/4 QPSK. In the puncturing process, the coding rate is changed to 3/4 and the data is output to the mapping circuit 11.

  FIG. 11 shows a configuration example when the frame synchronization signal and the TMCC signal of the convolutional encoding circuit 10 are convolutionally encoded. In this configuration example, the shift registers 61 to 66 sequentially output data input from the multiplexing circuit 9 to the subsequent stage. The exclusive OR circuit 67 calculates the exclusive OR of the input and output to the shift register 61, and the exclusive OR circuit 68 excludes the output of the exclusive OR circuit 67 and the output of the shift register 62. The exclusive OR circuit 69 calculates the exclusive OR of the output of the exclusive OR circuit 68 and the output of the shift register 63. The exclusive OR circuit 70 is configured to calculate and output an exclusive OR of the output of the exclusive OR circuit 69 and the output of the shift register 66.

  The exclusive OR circuit 71 calculates the exclusive OR of the input to the shift register 61 and the output of the shift register 62, and the exclusive OR circuit 72 outputs the output of the exclusive OR circuit 71 and the shift register 63, the exclusive OR circuit 73 calculates the exclusive OR of the output of the exclusive OR circuit 72 and the output of the shift register 65, and further performs the exclusive OR operation. The circuit 74 calculates the exclusive OR of the output of the exclusive OR circuit 73 and the output of the shift register 66.

  In the convolutional encoding circuit 10, when the input data is sequentially transferred to the subsequent stage by the shift registers 61 to 66 bit by bit, the exclusive OR circuit 67 to 74 generates an exclusive OR at each timing. Calculated. As a result, 2-bit data is output from the exclusive OR circuit 70 and the exclusive OR circuit 74 for one input bit (coding rate 1/2).

  Assuming that the frame synchronization signal is composed of 16 bits, when the first 6 bits of the 16 bits are held in the shift registers 61 to 66, the exclusive OR circuits 67 and 71 receive the data. Since the data of the seventh bit is input, the frame synchronization signal is unique data and is not arbitrarily changed data. At this time, the data output from the exclusive OR circuits 70 and 74 Is uniquely determined. The data output from the exclusive OR circuits 70 and 74 is uniquely determined by the shift registers 61 to 66 in the seventh bit from the last to the second bit from the end of the 16-bit frame synchronization signal. Until the last bit is input to the exclusive OR circuits 67 and 71.

  In the mapping circuit 11, when BPSK modulation is performed under the control of the controller 12 (when the input is a frame synchronization signal and a TMCC signal), signal points are mapped as shown in FIG. 4 and QPSK modulation is performed. (When the input is an image signal LQ for a low hierarchy) When signal points are mapped as shown in FIG. 5 and when 8PSK modulation is performed (the input is an image signal HQ for a high hierarchy) The signal points are mapped as shown in FIG.

  As a result of the convolutional encoding process of the convolutional encoding circuit 10, a 2-byte frame synchronization signal and a 10-byte TMCC signal are, as shown in FIG. 8C, a 32-bit (4-byte) frame synchronization signal, This is a 160-bit (20-byte) TMCC signal. FIG. 8C shows a case where the constraint length is 7 and the coding rate is 1/2 as a convolutional code.

As described above, the interleaving circuit 5 sufficiently disperses the error and modulates the TMCC signal subjected to the concatenated coding of the convolutional code and the RS code by the modulation method called BPSK, thereby preventing the transmission error. This makes it possible to have stronger resistance.

  By the way, the content of the transmission control signal of the main signal included in the TMCC signal is not frequently changed. However, since the receiving apparatus can know the modulation method and coding rate of the main signal from the transmission control signal obtained by decoding the TMCC signal, the TMCC signal is promptly transmitted when the power is turned on or at the time of channel selection. It is necessary to receive and demodulate. That is, on the transmitting device side, the TMCC signal does not need to be transmitted so frequently, but on the receiving device side, the main signal cannot be received until the TMCC signal is received. It is preferable to be able to receive relatively frequently so that it can be as short as possible. Therefore, it is preferable to reduce the transmission frequency of the TMCC signal within a range in which the waiting time of the receiving apparatus does not become long.

  FIG. 12 illustrates a configuration example of a receiving apparatus according to an embodiment of the present invention.

  In FIG. 12, a modulated signal transmitted via a predetermined transmission path is input to a frame synchronization detection circuit 41 and a demapping circuit 43. The frame synchronization detection circuit 41 detects a frame synchronization signal from the input signal and outputs the detection result to the demapping circuit 43 and the Viterbi decoding circuit 44. The phase detection circuit 42 detects signal point phase information from the output of the frame synchronization detection circuit 41 and outputs the detection result to the demapping circuit 43. The demapping circuit 43 detects a signal point based on the output of the TMCC decoder 47 or the frame synchronization detection circuit 41, generates a metric corresponding to the signal point, and outputs the metric to the Viterbi decoding circuit 44. The TMCC decoder 47 demodulates (decodes) the input TMCC signal and outputs the demodulated results (modulation scheme and coding rate) to the demapping circuit 43 and the Viterbi decoding circuit 44.

  The Viterbi decoding circuit 44 performs Viterbi decoding on the signal from the demapping circuit 43 based on the output of the TMCC decoder 47 or the frame synchronization detection circuit 41. The Viterbi decoding circuit 44 performs a convolutional decoding process on the demodulated signal of the BPSK signal (frame synchronization signal and TMCC signal) following the frame synchronization signal, and outputs the result to the deinterleave circuit 45. The deinterleave circuit 45 is a circuit that performs deinterleave processing corresponding to the convolutional interleave of the interleave circuit 5 in FIG. The Reed-Solomon decoding circuit 46 decodes the RS (48, 38) code input from the deinterleave circuit 45, and outputs the decoding result to the TMCC decoder 47 and the frame synchronization determination circuit 54.

  The deinterleave circuit 48 and the deinterleave circuit 51 use the low-hierarchy image signal LQ or the high-hierarchy image signal HQ supplied from the Viterbi decoding circuit 44 for interleaving processing of the interleave circuits 8 and 15 shown in FIG. Deinterleave correspondingly. Reed-Solomon decoding circuits 49 and 52 perform RS (204, 188) code decoding processing corresponding to the Reed-Solomon encoding circuits 6 and 13 of FIG. The TS synchronization byte register 53 stores a synchronization byte added to each TS packet. The multiplexing circuit 50 adds the TS packet output from the Reed-Solomon decoding circuit 49 or 52 to the TS packet from the TS synchronization byte register 53. Append the read sync byte.

  In the receiving apparatus of FIG. 12, the frame synchronization detection circuit 41 receives not only the frame synchronization signal but also the main signal. As described above, if the frame synchronization signal is 16 bits, the frame synchronization signal is converted into 32-bit data by the convolutional encoding circuit 10 of the transmission apparatus. The length (number of bits) of the frame synchronization signal is a bit longer than the constrained length of the convolutional coding circuit 10 (the number of bits necessary for the convolution operation, which is 7 in the example of FIG. 11). Therefore, the bits of the unique frame synchronization signal are held in all of the registers 61 to 66 of the convolutional coding circuit 10, and the inputs to the exclusive OR circuits 67 and 71 are also synchronized with the frame synchronization. A state occurs that is the bits that make up the signal. In this state, all the data used for the convolutional coding is composed of the bits of the frame synchronization signal, so the data obtained as a result of the convolution operation is also unique data.

  That is, as shown in FIG. 13, even if the first bit of the frame synchronization signal is input to the shift register 61 of the convolutional coding circuit 10 of FIG. 11 (timing t1), in this state, Since the previous data (data A to E other than the frame synchronization signal) are held in 62 to 66, the data output from the exclusive OR circuits 70 and 74 is not uniquely determined. The first bit of the frame synchronization signal is held in the shift register 66, the sixth bit is held in the shift register 61, and the seventh bit is supplied to the exclusive OR circuits 67 and 71 (timing t6). For the first time, the data output from the exclusive OR circuits 70 and 74 has a unique value corresponding to the frame synchronization signal.

  Similarly, the outputs of the exclusive OR circuits 70 and 74 are the 10th bit of the frame synchronization signal held in the shift register 66, the 15th bit held in the shift register 61, and the exclusive OR circuits 67, 74. The value becomes a unique value until the 16th bit of the frame synchronization signal is input to 71 (timing t15). When the 16th bit of the frame synchronization signal is held in the shift register 61 (timing t16), the next data a following the frame synchronization signal is input to the exclusive OR circuits 67 and 71. The data output from the logical OR circuits 70 and 74 is not uniquely determined.

  In the frame synchronization detection circuit 41, the sixth bit of the frame synchronization signal is input to the exclusive OR circuits 67 and 71 from the state in which the seventh bit of the frame synchronization signal is input to the exclusive OR circuits 67 and 71. The frame synchronization signal is detected by detecting the unique pattern generated by the exclusive OR circuits 70 and 74 during the period until the state is reached.

  If the position of the frame synchronization signal is known, the absolute phase of the signal point can be detected. Therefore, the phase detection circuit 42 detects the absolute phase of the signal point from the detection result output from the frame synchronization detection circuit 41. This removes the uncertainty of the phase of the recovered carrier.

  The demapping circuit 43 performs demapping processing according to the principle shown in FIG. 4 by using the detection signal input from the frame synchronization detection circuit 41 as a reference and using the signal following the frame synchronization signal as a BPSK-modulated signal. The metric is output to the Viterbi decoding circuit 44. The Viterbi decoding circuit 44 performs Viterbi decoding on the basis of the detection signal input from the frame synchronization detection circuit 41, assuming that the signal following the frame synchronization signal is 1/2 convolutionally encoded.

  The convolutionally decoded signal including the frame synchronization signal output from the Viterbi decoding circuit 44 and the TMCC signal is input to the deinterleave circuit 45 and deinterleaved. The output of the deinterleave circuit 45 is input to the Reed-Solomon decoding circuit 46, where Reed-Solomon decoding is performed, and transmission errors are corrected. The output of the Reed-Solomon decoding circuit 46 is supplied to the TMCC decoder 47 and the frame synchronization determination circuit 54.

  The TMCC decoder 47 decodes the TMCC signal from the input signal, and extracts transmission control information such as the modulation scheme and coding rate of the subsequent main signal. The extracted result is output to the demapping circuit 43 and the Viterbi decoding circuit 44. Thereafter, the demapping circuit 43 and the Viterbi decoding circuit 44 process the input main signal in accordance with the transmission control information from the TMCC decoder 47.

  The demapping circuit 43 performs demapping processing on the main signal supplied next to the TMCC signal in accordance with the transmission control information from the TMCC decoder 47. That is, when the input main signal is QPSK modulated, the demapping process is performed according to the principle shown in FIG. 5, and when it is TC8PSK modulated, the demapping process is performed according to the principle shown in FIG. Do.

  For example, the demapping circuit 43 performs demapping processing in the QPSK modulation scheme for the low-layer image signal LQ, and performs TC8PSK demapping processing for the high-layer image signal HQ.

  The metric output from the demapping circuit 43 is input to the Viterbi decoding circuit 44. The Viterbi decoding circuit 44 performs a convolution decoding process corresponding to the transmission control signal output from the TMCC decoder 47. For example, a decoding process for the de-puncturing process and a convolution process with a coding rate of 1/2 is performed on the image signal LQ for the low layer, and a coding rate of 2 is performed on the image signal HQ for the high layer. / 3 trellis decoding process is performed.

  The demodulated signal of the main signal output from the Viterbi decoding circuit 44 is input to the deinterleave circuits 48 and 51 and deinterleaved. The outputs of the deinterleave circuits 48 and 51 are input to the Reed-Solomon decoding circuits 49 and 52. Reed-Solomon decoding circuits 49 and 52 perform RS (204, 188) code decoding processing. The multiplexing circuit 50 reads the synchronization byte held in the TS synchronization byte register 53 at the position where the leading TMCC signal of each packet of each frame read out from the Reed-Solomon decoding circuit 49 or 52 is placed. Multiplex. As a result, the original TS packet as shown in FIG. 7 is obtained.

  Next, protection processing for the frame synchronization signal will be described. The frame synchronization detection circuit 41 detects the frame synchronization signal and performs a backward protection process on the frame synchronization signal as shown in steps S31 to S40 in FIG. Since the processing from step S31 to step S40 is the same as the processing from step S1 to step S10 in FIG. 2, the description thereof is omitted.

  Then, after the synchronization establishment process is performed in step S35, the frame synchronization determination circuit 54 detects the frame synchronization signal from the output of the Reed-Solomon decoding circuit 46 in step S41, and performs the frame synchronization determination process. Since the signal output by the Reed-Solomon decoding circuit 46 is a signal after the frame synchronization signal is convolutionally decoded by the Viterbi decoding circuit 44, the error on the transmission path has already been corrected. Therefore, the forward protection operation as shown in steps S11 to S15 in FIG. 2 is not necessary in the embodiment of the present invention, and the frame synchronization determination circuit 54 can be used once from the output of the Reed-Solomon decoding circuit 46. If the frame synchronization signal cannot be detected, it is immediately determined that the frame synchronization has been lost.

  Next, a second embodiment will be described. In BS digital broadcasting, it is possible to transmit two programs of high-definition television signals represented by so-called high-definition with one channel, and reliable transmission even when electric field strength is attenuated. TC8PSK (r = 2/3) (r represents a coding rate), QPSK (r = 3/4), QPSK (r = 1) / 2), BPSK (r = 1/2) and other transmission methods can be selected by the operator. Therefore, it can be transmitted as a TMCC signal to the receiving apparatus side as to which method is adopted.

  As described above, the TMCC signal is transmitted with BPSK (r = 1/2), but the main signal is transmitted with TC8PSK (r = 2/3) assuming that a high-definition television signal is transmitted. There is a high possibility of being. Due to the nature of satellite broadcasting, weather conditions differ from region to region, so the received C / N may be extremely low in a given region. Even under such circumstances, it is necessary to reliably transmit and receive the TMCC signal.

  Generally, when the transmission method is switched, the branch metrics defined by the Viterbi decoding circuit 44 are different. In the Viterbi decoding circuit 44, path control is performed corresponding to the value of the state metric obtained by accumulating the branch metrics. When the transmission method is switched, the branch metric after switching is compared with the state metric accumulated until then. If the path control is performed according to the state metric, an error may be propagated. In particular, when the number of multi-value levels changes abruptly, such as a change from BPSK to 8PSK, such an effect appears remarkably.

  In order to cut off this error propagation, it is conceivable to perform so-called termination processing. This termination processing means inserting a specific (known) pattern into the transmission data. The specific pattern for termination processing does not carry information, so even if the part is wrong, no information is lost, and this is when switching from a given transmission method to another transmission method. Can be regarded as a bit sequence for buffering.

  Therefore, as shown in FIGS. 15A to 15B, not only the frame synchronization signal (TAB1) is inserted at the beginning of the TMCC signal (between the main signal (payload) and the TMCC signal). A signal (TAB2) having a predetermined pattern for termination processing is also inserted behind the TMCC signal (between the TMCC signal and the next main signal). In this case, the length of the rear signal TAB2 is, for example, 2 bytes corresponding to the frame synchronization signal (TAB1). This signal is stored in advance in the synchronization register 2 (FIG. 3) together with the frame synchronization signal, and is read from there appropriately.

  In FIG. 15A to FIG. 15C, the input bit sequence shown in FIG. 15A is input to the convolutional encoding circuit 10 shown in FIG. The output bit sequence shown in FIG. 15C is output from the convolution negative sign or the circuit 10.

  In order to terminate the convolutional code, a known bit sequence smaller by 1 than the constraint length may be inserted. That is, in the configuration example of FIG. 3, the convolutional encoding circuit 10 has a constraint length of 7, so that a known 6-bit code string may be inserted as a code for termination processing. When a longer known bit sequence is inserted, the encoded output longer than the constraint length becomes a specific pattern as described above. For example, if a 2-byte frame synchronization signal is inserted before the TMCC signal as shown in FIG. 15A, the output bit sequence of the convolutional encoding circuit 10 is shown in FIG. The 12 bits (12 symbols) are an indefinite pattern, but the subsequent 20 bits (20 symbols) pattern is a specific pattern. In the configuration example of FIG. 3, the frame synchronization detection circuit 41 detects this specific pattern as a frame synchronization signal.

  As shown in FIG. 15A, when a signal for termination processing of 2 bytes, for example, is added to the rear of the TMCC signal, the corresponding 4-byte signal output from the convolutional encoding circuit 10 is added. Of these, 12 bits (12 symbols) are indefinite patterns, and the following 20 bits (20 symbols) are specific patterns. As this specific pattern, the frame number of the super frame can be transmitted. A super frame is composed of 8 frames, and a frame number indicating the number of the 8 frames (representing the position) is a signal of a specific pattern behind the TMCC signal. Can be transmitted as

  In this case, in the frame synchronization detection circuit 41, the 4-byte signal on the front side of the TMCC signal may be detected as the frame synchronization signal as in the case described above. Both of them may be detected as frame synchronization signals.

  In this way, it is possible not only to perform termination processing for mitigating error propagation, but also to use these signals as frame synchronization signals or frame numbers.

  Further, in this example, the mapping circuit 11 performs BPSK modulation on both the 4-byte signal before the TMCC signal and the 4-byte signal after the TMCC signal. From the viewpoint of convolutional code termination processing, termination processing is generally performed by the same modulation method as the signal to be terminated. For example, as shown in FIGS. 15A to 15C, a 4-byte signal added before the TMCC signal terminates the convolutional code of the main signal (payload). For example, 8PSK modulation is generally performed similarly to the signal.

  However, when C / N is the same, the branch metric of BPSK (r = 1/2) is more reliable than the branch metric of 8PSK (r = 2/3). Further, from the viewpoint of improving the reliability of the TMCC signal transmitted by BPSK (r = 1/2), it is necessary to improve the reliability of the state metric for performing path control as little as possible. Even so, it is advantageous to perform the convolutional code termination processing with BPSK (r = 1/2). Therefore, in this embodiment, the termination process of the TMCC signal is performed by the rear 4-byte signal modulated by the same BPSK (r = 1/2) as the TMCC signal, and the termination of the main signal (payload). The processing is not the main signal modulation method 8PSK (r = 2/3) but the TMCC signal modulation method BPSK (r = 1/2) and the subsequent 4-byte signal (TMCC) 4 bytes of signal in front of the signal).

  Therefore, in the receiving apparatus, the demapping circuit 43 demodulates the TMCC signal and the front and rear 4-byte signals by BPSK demodulation.

  As shown in FIGS. 15A to 15C, an input sequence I1 is arranged in TAB1 in front of the TMCC signal, and input sequences I1, I2 or I3 are arranged in TAB2 behind the TMCC signal. Is placed.

  At this time, the convolutional coding circuit 10 outputs the specific pattern W1 in TAB1 in front of the TMCC signal and W1, W2 or W3 in TAB2 behind the TMCC signal.

  By the way, when the frame synchronization signal is detected in the frame synchronization detection circuit 41 of the receiving apparatus shown in FIG. 12, the autocorrelation function of the specific pattern (frame synchronization signal) is preferably an impulse. The autocorrelation function is defined by the following equation.

Please join the number 1.

  In the above equation, C (t) is a specific pattern of the code output sequence (specific pattern after convolutional encoding by the convolutional encoding circuit 10) W1, C (0) is the MSB of W1, and C (19) is W1. LSB. Further, t is any value from 0 to 19, and when t, t−τ exceeds the range of 0 to 19, (2 × C (t) −1) × (2 × C ( The value of t−τ) −1) is 0.

  0xD439B can be used as the specific pattern W1, 0x0B677 can be used as W2, and 0x578DB can be used as W3.

  When 0xD439B is used as the specific pattern W1, R (0) = 20 and | R (τ) | ≦ 3 (τ ≠ 0), and an impulse-like autocorrelation characteristic is realized. In the case where 0x0B677 or 0x578DB is used as the specific patterns W2 and W3, respectively, similarly, an impulse-like autocorrelation characteristic can be realized.

  When the specific patterns output from the convolutional encoding circuit 10 are W1, W2, and W3, it is preferable that the autocorrelation characteristics are also impulse-like with respect to the input sequence patterns I1, I2, and I3 input thereto. In this case, the autocorrelation function is defined by the following equation.

Please join the number 2.

  Here, I (t) is an input sequence corresponding to W1, I (0) is the MSB of I1, and I (15) is the LSB of I1. t takes a value from 0 to 15. When t and t−τ exceed the range of 0 to 15, the value of (2 × I (t) −1) × (2 × I (t−τ) −1) is 0.

  For the input sequence I1 corresponding to the specific pattern W1, R (0) = 16 and | R (τ) | ≦ 3 (τ ≠ 0), and an impulse-like autocorrelation characteristic is realized.

  For the input sequence I2 corresponding to the specific pattern W2, R (0) = 16 and | R (τ) | ≦ 5 (τ ≠ 0). Furthermore, with respect to the input sequence I3 corresponding to the specific pattern W3, R (0) = 16 and | R (τ) | ≦ 7 (τ ≠ 0), which also realizes a good autocorrelation characteristic. Can do.

  When the specific pattern W1 is 0xD439B, the frame synchronization detection circuit 41 of the receiving apparatus uses, for example, the specific pattern 0xD439B (= 101010100001110011011) as a detection window, and the value and the input 20-bit data for each bit. And exclusive OR operation. If the corresponding bits of 20 bits are the same, the operation value of the exclusive OR for each bit is 0, and 1 if it is different. The sum of the arithmetic values of 20-bit exclusive OR becomes the correlation value, and when the same data as the detection window is input, the correlation value is 0. When other data is input, it is more than 0 Large value. Thereby, the frame synchronization signal (specific pattern W1 (0xD439B)) can be detected.

  In the input sequence I1 (0x032E) (= 0000001100101110) corresponding to the specific pattern W1 (0xD439B), the leading 6 bits are 0, so that the convolutional coding circuit 10 can be initialized. That is, this 6-bit 0 is held in the shift registers 61 to 66 (FIG. 11), and the previous code sequence can be terminated. This also means that the input code sequence is terminated with 0. As a result, it is possible to simplify the configuration of the transmission device and the reception device.

  In addition, the last 6 bits of the input series 0xA340 (= 1010001101000000) corresponding to the specific pattern W2 (0x0B677) and the input series 0x78C0 (= 0111100011000000000) corresponding to the specific pattern W3 (0x578DB) are both 0. Even in this case, the convolutional encoding circuit 10 can terminate the previous code sequence. This also means that the TMCC signal is terminated and the next code is initialized. Therefore, also from this, the configuration of the transmission device and the reception device can be simplified.

  FIG. 16 shows an example in which the specific patterns W1 to W3 are periodically arranged with reference to the superframe. In this example, in frame 1, W1 is arranged in front of the TMCC signal and W2 is arranged behind, and in subsequent frames 2 to 8, W1 is arranged in front of the TMCC signal and W3 is arranged behind. Has been placed. With this arrangement, a super frame can be detected. The flowchart in FIG. 17 represents the processing in this case.

  That is, first, in step S61, using the correlation of the specific pattern W1 arranged in front of the TMCC signal of each frame, frequency adjustment for tuning of the receiving apparatus is performed. That is, control is performed so that the clock is generated and the frame synchronization is achieved so that the correlation value of the specific pattern W1 is the best.

  Next, in step S62, a signal located at a position behind the position where the specific pattern W1 is detected by the length of the TMCC signal is detected as the specific pattern W2. As shown in FIG. 16, the specific pattern W2 is arranged only in the top frame of the super frame, and the specific pattern W3 is arranged in the remaining seven frames. Therefore, the frame in which the specific pattern W2 is detected is detected as the head frame of the super frame.

  Next, in step S63, frame synchronization protection is performed. If the frame is synchronized, the frame synchronization protection process is repeatedly executed. If the frame synchronization protection is removed, the process returns to step S61, and the subsequent processes are performed. It is executed repeatedly.

  As described above, the last 6 bits of the input sequence I2 or I3 of the specific pattern W2 or W3 behind the TMCC signal are all zero. Therefore, as shown in FIG. 18A and FIG. 18B in which a part of FIG. 18A is enlarged, the convolutional encoding circuit 10 of the main signal (payload) is initialized to 000000 regardless of the contents of the TMCC signal. Thus, the main signal can be encoded. Further, after the encoding of the main signal (payload) is completed, a 6-bit 0 is arranged at the head of the input sequence I1 of the specific pattern W1 input prior to the TMCC signal, so that the convolutional encoding circuit 10 Can encode signals up to 000000 as codes of the main signal (payload).

  FIG. 19 illustrates another configuration example for convolutional encoding in the transmission device. In this configuration example, the multiplexing circuit 101 is supplied with the data after the seventh bit of the input sequence I1 corresponding to the specific pattern W1, the TMCC signal, or the input sequences I2 and I3 corresponding to the specific pattern W2 or W3. Yes. The multiplexing circuit 101 selects one of them and supplies it to the encoder 102 as the convolutional encoding circuit 10. The encoder 102 is initialized with 6 bits of 0 before the seventh bit of the input sequence I1 corresponding to the input specific pattern W1 is input.

  On the other hand, a main signal (payload) and 6-bit data 000000 are supplied to the multiplexing circuit 104, and the multiplexing circuit 104 selects one of the encoders 105 as the convolutional encoding circuit 10. To supply. The encoder 105 is initialized with 6 bits of 0 before the first data of the payload is input.

  The output of the encoder 102 and the output of the encoder 105 are supplied to the multiplexing circuit 103, multiplexed and output.

  As described above, in the configuration example of FIG. 19, the encoder 102 that encodes the TMCC signal can be configured independently of the encoder 105 that encodes the payload. A transmission apparatus to which the present invention can be applied can be realized simply by adding a new encoder 102 to the encoder 105.

  As shown in FIG. 19, the code sequence can be considered to be independent between the TMCC signal and the main signal (payload). Therefore, the receiving apparatus can also decode independently for each corresponding code sequence. FIG. 20 shows a configuration example in this case.

  That is, in this configuration example, the separation circuit 121 separates the input code into a code sequence corresponding to the TMCC signal and a code sequence corresponding to the payload, with the former as the decoder 122 and the latter as the decoder. 124, respectively. The decoder 122 decodes the code sequence corresponding to the input TMCC signal and supplies it to the separation circuit 123. The separation circuit 123 separates the decoding result from the decoder 122 into data after the seventh bit of the input sequence I1 corresponding to the specific pattern W1, TMCC signal, or input sequences I2 and I3 corresponding to the specific pattern W2 or W3. And output.

  The decoder 124 decodes the main signal (payload) from the separation circuit 121 and outputs it to the separation circuit 125. The separation circuit 125 separates the data supplied from the decoder 124 into a payload and a 6-bit 0 code, and outputs the result. Since the 6-bit 0 is not practically used, only the main signal (payload) needs to be extracted.

  Note that each of the decoder 122 and the decoder 124 corresponds to the Viterbi decoding circuit 44 of the receiving apparatus shown in FIG.

  Even in this case. Usually, it is possible to easily configure a receiving apparatus to which the present invention can be applied only by adding a new decoder 122 to the decoder 124 provided in the receiving apparatus.

  As shown in FIG. 21, the decoder 122 and the decoder 124 shown in FIG. 20 can be shared as a decoder 131. In this case, the separation circuit 132 determines from the output of the decoder 131 the data after the 7th bit of the input sequence I1 corresponding to the specific pattern W1, the TMCC signal, the input sequences I2 and I3 corresponding to the specific pattern W2 or W3, and Separate and output main signal (payload).

  Next, a third embodiment of the present invention will be described. If the tolerance of TMCC signals to transmission path errors becomes stronger, it is not necessary to transmit TMCC signals frequently from that point of view. Thus, when not transmitting the TMCC signal, it is conceivable to transmit other data instead of the TMCC signal. FIG. 22 shows a configuration example of the transmission apparatus in this case. In FIG. 22, the same reference numerals are given to the portions corresponding to those in FIG. In the configuration example of FIG. 22, data (sub-signal) transmitted instead of the TMCC signal is supplied to the memory 21 and stored therein. The multiplexing circuit 3 selects the TMCC signal stored in the memory 1 or the data stored in the memory 21, multiplexes it with the frame synchronization signal supplied from the synchronization register 2, and outputs it. Has been made. Other configurations are the same as those in FIG.

  However, in the case of this configuration example, the controller 12 controls the multiplexing circuit 9 to transmit to the header added to each frame in the frame whether it is a TMCC signal or other data. Include an identifier that represents

  Next, a fourth embodiment of the present invention will be described. The interleaving circuit 5 of the transmitting apparatus is roughly divided into a block type and a convolution type, but the circuit scale is small and corresponding parts of the preceding and following RS codes are stored at the same position. From the nature, as described above, a convolutional interleave circuit is used as the interleave circuit 5.

  23A to 23C show how TMCC signals are distributed in the convolutional interleave circuit 5 shown in FIG. 23B. As shown in the figure, the RS code of number N is composed of 48 bytes, with the first 38 bytes being data and the latter 10 bytes being parity. As described above, the first two bytes of the 38-byte data are used as a frame synchronization signal. The same applies to the RS codes with numbers N + 1 to N + 4. This RS code is generated by the Reed-Solomon encoding circuit 4.

  The convolutional interleave circuit 5 shown in (B) of FIG. 23, for the input data shown in (A) of FIG. 23, has the frame synchronization signal of the first two bytes as described with reference to FIG. Although the data is output as it is, the output is delayed by 1 to 5 delay units in units of 2 bytes. As a result, as shown in FIG. 23C, the RS codes are distributed in units of 2 bytes over the five RS codes. For example, in the RS code after the interleaving in which the first two bytes (frame synchronization signal) of the RS code of the number N + 4 are arranged at the head, the data of the third and fourth bytes of the number N + 3 are next. Next, the byte data of number 5 and number 6 of number N + 2 are arranged. Similarly, the position of each byte of the RS code before interleaving is arranged at the same position in the RS code after interleaving.

  Therefore, if the TMCC signals of number N to number N + 4 are equal, the RS codes of number N to number N + 4 are equal before and after interleaving. As described above, the TMCC signal changes very rarely due to the nature as a transmission control signal, and in most cases, is the same data. Therefore, in the receiving apparatus, an error in the TMCC signal can be corrected by so-called majority decision processing without RS decoding the Viterbi-decoded RS code.

  FIG. 24 and FIG. 25 show configuration examples of respective embodiments of the receiving device in this case. In the embodiment of FIG. 24, the output of the deinterleave circuit 45 is input to the majority decision circuit 71, and the output of the majority decision circuit 71 is supplied to the TMCC recorder 47 and the frame synchronization determination circuit 54. That is, the Reed-Solomon decoding circuit 46 in FIG. 12 is omitted. Other configurations are the same as those in FIG.

  In this configuration example, the majority decision determination circuit 71 performs error correction on the RS code deinterleaved by the deinterleave circuit 45 based on the principle of majority decision. That is, for example, when five RS codes are input, the data with the most content is set as correct data.

  With this configuration, as shown in FIG. 12, the configuration can be simplified and the apparatus can be downsized as compared with the case where the Reed-Solomon decoding circuit 46 is provided.

  In the embodiment of FIG. 25, the deinterleave circuit 45 and the Reed-Solomon decoding circuit 46 in FIG. 12 are omitted, and a majority decision circuit 71 is provided instead. That is, the output of the Viterbi decoding circuit 44 is directly input to the majority decision determination circuit 71, and the output of the majority decision determination circuit 71 is supplied to the TMCC decoder 47 and the frame synchronization determination circuit 54.

  As described above, if the TMCC signals are the same, the RS code after being interleaved by the interleave circuit 5 is the same as the RS code before being interleaved. That is, it is substantially the same as the case where interleaving is not performed. Therefore, the deinterleaving circuit 45 in FIG. 24 can be omitted, and the output of the Viterbi decoding circuit 44 can be directly decoded by the majority decision circuit 71. With this configuration, the configuration can be further simplified and the apparatus can be miniaturized as compared with the case shown in FIG.

  However, in the embodiment of FIG. 24, since the deinterleave circuit 45 is provided, the input of the majority decision circuit 71 (the output of the deinterleave circuit 45) is as shown in FIG. On the other hand, in the embodiment of FIG. 25, since the deinterleave circuit 45 is not provided, the input of the majority decision circuit 71 (the output of the deinterleave circuit 45) is as shown in FIG. In any case, if the TMCC signals are the same, the RS codes of the respective numbers are substantially the same, so that determination by majority vote is possible.

  That is, the majority decision is made on the Data portion in FIG. 26 when the receiving side performs deinterleaving and FIG. 27 when the receiving side does not perform deinterleaving.

  In the case of the embodiment shown in FIGS. 24 and 25, since it is necessary to repeatedly transmit the same TMCC signal, the amount of data other than the TMCC signal can be transmitted compared to the case of the embodiment of FIG. Decrease.

  Note that as a transmission medium for transmitting a program for performing the processing as described above to a user, a communication medium such as a network or a satellite can be used in addition to a recording medium such as a magnetic disk, a CD-ROM, or a solid-state memory.

It is a block diagram which shows the structural example of the conventional transmitter. It is a flowchart explaining the synchronization process of the conventional receiver. It is a block diagram which shows the structural example of the transmitter for sending a digital broadcast signal to the receiver which applied this invention. It is a figure explaining the mapping of the symbol of a BPSK modulation system. It is a figure explaining the mapping of the symbol of a QPSK modulation system. It is a figure explaining the mapping of the symbol of 8PSK modulation system. It is a figure explaining the packet of a transport stream. It is a figure for demonstrating the change of a TMCC signal. It is a figure which shows the more detailed structural example of the interleave circuit shown in FIG. It is a figure explaining the format of the signal obtained by the multiplexing process in the multiplexing circuit 9 shown in FIG. It is a block diagram which shows the structural example of the convolution decoding circuit 10 shown in FIG. It is a block diagram which shows the structural example of embodiment of the receiver which applied this invention. FIG. 12 is a diagram illustrating an operation of the frame synchronization detection circuit illustrated in FIG. 11. 12 is a flowchart for explaining synchronization processing in the receiving apparatus shown in FIG. 11. It is a figure for demonstrating operation | movement of a convolution encoding circuit. It is a figure explaining arrangement | positioning of the specific pattern in a super frame. It is a flowchart explaining the process of a specific pattern detection in the format shown in FIG. It is a figure which shows the format of a TMCC signal and a main signal (payload). It is a figure which shows the structural example in the case of encoding a TMCC signal and a main signal (payload) independently. It is a figure which shows the structural example in the case of decoding a TMCC signal and a main signal (payload) independently. It is a block diagram which shows the structural example in the case of decoding in common with a TMCC signal and a main signal (payload). It is a block diagram which shows the other structural example of the transmitter for transmitting a digital broadcast signal to the receiver which applied this invention. It is a figure for demonstrating the process of the interleave circuit. It is a block diagram which shows the structural example of other embodiment of the receiver which applied this invention. It is a block diagram which shows the structural example of other embodiment of the receiver which applied this invention. It is a figure explaining the input of the majority decision circuit shown in FIG. It is a figure explaining the input of the majority decision circuit shown in FIG.

Explanation of symbols

  1,7,14 memory, 2 synchronization register, 3,9 multiplexing circuit, 4,6,13 Reed-Solomon encoding circuit, 5,8,15 interleave circuit, 10 convolutional encoding circuit, 11 mapping circuit, 12 controller, 41 frame synchronization detection circuit, 42 phase detection circuit, 43 demapping circuit, 44 Viterbi decoding circuit, 45, 48, 51 deinterleave circuit, 46, 49, 52 Reed-Solomon decoding circuit, 50 multiplexing circuit, 53TS synchronization byte register, 54 Frame synchronization determination circuit

Claims (6)

The main signal is transmitted in the payload portion of the transport packet, a frame is formed by a predetermined number of transport packets, and at least a part of the synchronization portion of the transport packet in the frame is an m-bit frame synchronization signal, transmission system And the Reed-Solomon code generated for the control signals for a plurality of frames, the frame synchronization signal in the first frame, the order of the control signals, the frame synchronization signal in the second frame, A digital broadcast signal that is transmitted after being subjected to intra-error correction encoding by an intra-error correction encoding circuit of constraint length n (n <m) provided for the main signal, based on signals in the order of Reed-Solomon codes A digital broadcast signal receiving device for receiving
A demodulation circuit for demodulating the received signal;
An error correction inner encoding circuit which is supplied with an output signal of the demodulation circuit and performs decoding processing of the error correction inner code;
A Reed-Solomon decoding circuit that decodes the Reed-Solomon code output from the error correction intra-encoding circuit;
A digital broadcast signal receiving apparatus comprising: means for specifying a modulation method and a coding rate of the main signal based on the control signal output from the Reed-Solomon decoding circuit.   The main signal is modulated and transmitted by a modulation method selected from a plurality of modulation methods, and the control signal includes information for specifying a modulation method applied to the main signal. The digital broadcast signal receiver according to claim 1.   2. The digital broadcast signal receiving apparatus according to claim 1, further comprising replacement means for replacing received data corresponding to the synchronization unit of the received signal with a predetermined value. The main signal is transmitted in the payload portion of the transport packet, a frame is formed by a predetermined number of transport packets, and at least a part of the synchronization portion of the transport packet in the frame is an m-bit frame synchronization signal, transmission system And the Reed-Solomon code generated for the control signals for a plurality of frames, the frame synchronization signal in the first frame, the order of the control signals, the frame synchronization signal in the second frame, A digital broadcast signal transmitted after being subjected to intra-error correction encoding by an intra-error correction encoding circuit having a constraint length n (n <m) provided for the main signal with a signal based on each signal in the order of Reed-Solomon codes. A digital broadcast signal receiving method for receiving,
A demodulation step of demodulating the received signal;
An error correction inner encoding step in which an output signal of the demodulation circuit is supplied and the error correction inner code is decoded; and
A Reed-Solomon decoding step of decoding the Reed-Solomon code output in the error correction intra-encoding step;
A method of receiving a digital broadcast signal, comprising: a step of specifying a modulation method and a coding rate of the main signal based on the control signal output in the Reed-Solomon decoding step.   The main signal is modulated and transmitted by a modulation method selected from a plurality of modulation methods, and the control signal includes information for specifying a modulation method applied to the main signal. The digital broadcast signal receiving method according to claim 4.   5. The digital broadcast signal receiving method according to claim 4, wherein received data corresponding to the synchronization unit of the received signal is replaced with a predetermined value.

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