JP2007259102A - Regulator circuit, power supply circuit, and imaging module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To drive a vertical transfer electrode of a CCD solid-state imaging device at a specified amplitude level by means of a power supply circuit having a charge pump circuit combined with a regulator circuit. <P>SOLUTION: The regulator circuit has voltage control means (21, 22, 23, 24, 25 and 26) each controlling an output voltage of an output end 28 at a constant value by controlling a potential descending amount to an input voltage. There are provided current decision means (51 and 52) for monitoring each output current of the voltage control means, and deciding whether or not the output current exceeds a predetermined current; and a current booster means (53, 54, 55 and 56) connected to the output end 28 of the voltage control means for making a compensation current flow to the output end 28 according to the decision result of the current decision means. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a regulator circuit used in a solid-state imaging module or the like, and more specifically, a regulator circuit that outputs a driving voltage to a vertical transfer electrode of a CCD (Charge Coupled Devices) type image sensor (area sensor), and a power source The present invention relates to a circuit and an imaging module.

  FIG. 6 is a block diagram of a general CCD type solid-state imaging module. The CCD solid-state imaging module includes a photographic lens 1, a CCD solid-state imaging device 2 that receives an optical image formed by the photographic lens 1 at a light receiving surface and converts it into an electrical signal, and the photographic lens 1 and the imaging device 2. And light shielding means 3 such as a mechanical shutter provided therebetween.

  The CCD solid-state imaging module further includes an analog front-end processor (AFE) 4 connected to the output of the solid-state imaging device 2, a digital signal processing (DSP) unit 5 connected to the output of the AFE 4, and an imaging device drive. A circuit (drive circuit: DRV) 6, a timing generator (TG) 7 for outputting a timing signal thereto, and a power supply (PWR) 8 for supplying power supply voltages (VH, VL, VDD) to the DRV 6 are provided.

  The photographing lens 1 forms an image of the subject light beam on the light receiving surface of the image sensor 2, and the light shielding means 3 controls whether the subject light beam from the lens 1 is allowed to pass through or is blocked from the light receiving surface. The imaging device 2 includes a photoelectric conversion element that generates charges according to the amount of incident light, and a vertical transfer electrode and a horizontal transfer electrode for transferring signal charges generated in the photoelectric conversion element.

  The AFE 4 performs correlated double sampling of the analog image signal output from the image sensor 2 at two locations of the reference potential portion and the signal potential portion, and applies an appropriate gain to the difference to perform A / D (analog / digital) conversion. And output as a digital image signal. The DSP 5 performs various signal processing on the digital image signal output from the AFE 4.

  The timing generator (TG) 7 outputs a timing signal H for driving the horizontal transfer electrode to the image sensor 2, outputs a timing pulse to the AFE 4, and also synchronizes with the DSP 5. The timing pulse is output. The TG 7 also outputs a timing pulse to a driving circuit (DRV) 6 that supplies a driving voltage to the vertical transfer electrode of the image sensor 2.

  Since the applied voltage (timing signal H) to the horizontal transfer electrode of the image sensor 2 is a low voltage of about 3 V, the timing signal H for driving the horizontal transfer electrode is directly output from the TG 7 to the horizontal transfer electrode. Since the applied voltage to the vertical transfer electrode is a high voltage, the DRV 6 receives a timing signal from the TG 7 and applies a high drive voltage to the vertical transfer electrode.

  The DRV 6 is an integrated circuit (IC) for driving the vertical transfer electrode of the image sensor 2 and generally transfers three voltages including a negative voltage, for example, “+15 V”, “0 V”, and “−8 V”. Output to electrode. The power supply voltage necessary for the operation of the AFE4, DSP5, TG7 is a low voltage such as 3V, but the output voltage of the DRV6 is a high voltage of “+ 15V” and “−8V”, so the power supply (PWR) 8 is the DRV6. Is designed to supply high voltage.

  FIG. 7 is a detailed configuration diagram of the power supply (PWR) shown in FIG. When the electronic device requires a high voltage, the high voltage can be generated by a switching regulator using a coil. However, the cellular phone uses a radio wave and does not use a switching regulator in which magnetic flux leaks around and disperses electromagnetic noise. Instead, a charge pump circuit capable of generating high voltage with a capacitor is used.

  A power supply (PWR) 8 having a charge pump circuit shown in FIG. 7 includes a battery 11, a VDD regulator 12 that generates a voltage VDD from the battery voltage VBAT, a 6-fold boost charge pump circuit 13 that increases the voltage VDD by 6 times, and a voltage A VH regulator 14 that generates a predetermined high voltage VH from a voltage VH0 that is six times VDD, a three-fold negative boost charge pump circuit 15 that triples the voltage VDD, and a predetermined voltage VL0 that is three times the voltage VDD And a VL regulator 16 that generates a negative high voltage VL. The voltage VH is output from the VH regulator 14 to the DRV6, the voltage VDD is output from the VDD regulator 12 to the DRV6, the regulators 14 and 16, and the voltage VL is output from the VL regulator 16. Is output to DRV6.

  The battery 11 is a rechargeable battery such as a lithium ion battery, for example, and supplies the battery voltage VBAT to the VDD regulator 12. The battery voltage VBAT is a voltage in the range of +3.2 V to +5.5 V, for example, and changes depending on the state of charge and the state of load current. The VDD regulator 12 is a series regulator, and is supplied with the battery voltage VBAT, and VDD (for example, +3 V) controlled so as to become a constant voltage regardless of the voltage level of the VBAT and the state of the output load current, This is supplied to each charge pump circuit 13, 15, DRV6 and the like.

  The 6-times boosting charge pump circuit 13 is a boosting charge pump circuit using a switched capacitor. Upon receiving the supply of the voltage VDD, the 6-fold boosting charge pump circuit 13 supplies a voltage VH0 (about +18 V) obtained by multiplying the voltage VDD to the VH regulator 14. .

  The triple negative charge pump circuit 15 is a boost charge pump circuit using a switched capacitor, and receives the supply of the voltage VDD and supplies VL0 (about −9 V) obtained by multiplying the voltage VDD by −3 to the VL regulator 16. To do.

  The voltage values of the output voltages VH0 and VL0 of the charge pump pump circuits 13 and 15 are slightly reduced by the output resistance and load current of the charge pump circuits 13 and 15.

  The VH regulator 14 receives the supply of the voltage VH0, and supplies the voltage VH (for example, + 15V) controlled to a constant voltage DRV6 regardless of the voltage level of the voltage VH0 and the state of the output load current. The VL regulator 16 receives the supply of the voltage VL0 and supplies the voltage VL (for example, −8V) controlled to a constant voltage to the DRV 6 regardless of the voltage level of the voltage VL0 and the state of the output load current.

  FIG. 8 is a circuit diagram of a conventional VH regulator 14. A conventional VH regulator includes an error amplifier (Amp) 21, a V / I (voltage / current) conversion transistor 22, a diode-connected transistor 23, an output transistor 24, and resistors 25 and 26 for dividing an output voltage. And a power supply bypass capacitor 27.

  As the error amplifier 21, an operational amplifier is used, and its DC gain is about 40 dB to 80 dB. Further, the resistors 25 and 26 are set so that the ratio thereof divides the output voltage VH by resistance and applies the same voltage as the reference voltage (Vref) to the negative input of the error amplifier 21. The output of the error amplifier 21 is connected to the gate of the V / I conversion transistor 22 and increases or decreases the error current value according to the output voltage of the error amplifier 21.

  The error current value flows through the diode-connected transistor 23 whose source is connected to the voltage VH0. The output transistor 24 constitutes a current mirror with the diode-connected transistor 23, a current value of the error current value is amplified by the size ratio of the diode-connected transistor 23 and the output transistor 24, and the current V is output from the power source of the voltage VH0. Pour to 28.

  For example, when the output voltage VH is lowered, the voltage divided by the resistor 25 and the resistor 26 is also lowered, and the negative input is lower than the positive input of the error amplifier 21. Then, the error amplifier output voltage rises, and the error current increases by the V / I conversion transistor 22. The current is amplified by a current mirror, and the output voltage VH is increased by increasing the current flowing through the output transistor 24, and is controlled to restore the output voltage VH. The output voltage VH is controlled to be constant by such a negative feedback loop.

  Since the error amplifier 21 can operate between VDD and GND, it can be configured with a low-breakdown-voltage fine transistor. Further, since the V / I conversion transistor 22, the diode connection transistor 23, and the output transistor 24 operate between VH0 and GND, it is necessary to use high voltage transistors.

  The power supply bypass capacitor 27 is connected to a terminal 28 that outputs a voltage VH, and suppresses high frequency noise. Further, the first pole (1st Pole) is set by the output resistance of the output transistor 24 and the capacitance value of the power supply bypass capacitor 27 to perform phase compensation, and the VH regulator 14 operates stably.

  FIG. 9 is a circuit diagram of a conventional VL regulator 16 (FIG. 7). The VL regulator includes an error amplifier 31, a V / I conversion transistor 32, a diode-connected transistor 33, an output transistor 34, resistors 35 and 36 for dividing the output voltage, and a power supply bypass capacitor 37. The

  As the error amplifier 31, an operational amplifier is used, and its DC gain is about 40 dB to 80 dB. Further, the ratio of the resistors 35 and 36 is set so that the ratio of the output voltage VL is divided and the same voltage as the reference voltage (Vref) is applied to the negative input of the error amplifier 31.

  The output of the error amplifier 31 is connected to the gate of the V / I conversion transistor 32, and the error current value is increased or decreased according to the output voltage of the error amplifier 31. The error current value flows through the diode-connected transistor 33 whose source is connected to the voltage VL0. The output transistor 34 forms a current mirror with the diode-connected transistor 33, amplifies the error current value by the size ratio of the diode-connected transistor 33 and the output transistor 34, and flows the current from the voltage VL side to the voltage VL0 side. .

  For example, when the output voltage VL increases, the voltage divided by the resistors 35 and 36 also increases, and the negative input becomes higher than the positive input of the error amplifier 31. Then, the error amplifier output voltage decreases, and the error current increases by the V / I conversion transistor 32. The current is amplified by a current mirror, and the output voltage VL is lowered by increasing the current flowing through the output transistor 34, and the output voltage VL is controlled to be restored. The output voltage VL is controlled to be constant by such a negative feedback loop.

  Since the error amplifier 31 can operate between VDD and GND, it can be constituted by a low-breakdown-voltage fine transistor. Further, since the V / I conversion transistor 32, the diode connection transistor 33, and the output transistor 34 operate between VDD and VL0, it is necessary to use high voltage transistors.

  The power supply bypass capacitor 37 is connected to the output terminal 38 and suppresses high frequency noise. Further, the first pole is set by the output resistance of the output transistor 34 and the capacitance value of the power supply bypass capacitor 37 to perform phase compensation, and the regulator 16 operates stably.

  FIG. 10 is a detailed schematic diagram of the image sensor 2 and the DRV 6. The image sensor 2 is an interline type CCD area image sensor, and a large number of photoelectric conversion elements 2a are arranged in a matrix along a plurality of rows and columns. One vertical charge transfer element 2b is arranged for each photoelectric conversion element array, and each vertical charge transfer element 2b is electrically connected to the horizontal charge transfer element 2c.

  In charge reading from the photoelectric conversion element 2a to the vertical charge transfer element 2b and charge transfer in the direction of the horizontal charge transfer element 2c by the vertical charge transfer element 2b, a pulse voltage for transfer driving is applied to the vertical transfer electrode of the imaging element 2. Is done. Charge transfer in the direction of the output unit 2d by the horizontal charge transfer element 2c is performed by applying a pulse voltage for transfer driving to the horizontal transfer electrode of the image pickup element 2.

  The DRV 6 includes a control logic 6a, binary driver circuits 6b and 6c and ternary driver circuits 6d and 6e that output a pulse voltage to the vertical transfer electrodes. A timing pulse signal from the timing generator 7 is input to the control logic 6a as a control signal. The control logic 6a converts the control signal into a signal level capable of controlling the driver circuits 6b to 6e, and supplies a control signal for determining the outputs of the driver circuits 6b to 6e to the driver circuits 6b to 6e. .

  The vertical transfer electrodes of the image sensor 2 are driven by three-value driving (+15 V, 0 V, −8 V) for performing a read operation and a transfer operation and binary driving (0 V, −8 V) for performing only a transfer operation.

  In FIG. 10, the outputs TO1 and TO2 of the ternary driver circuits 6d and 6e for ternary driving are connected to the vertical transfer electrodes V2 and V4 which also serve as read gates, respectively. The outputs BO1 and BO2 of the binary driver circuits 6b and 6c for binary driving are respectively connected to vertical transfer electrodes V1 and V3 that perform only transfer. The number of driver circuits provided in the DRV 6 varies depending on the number of vertical transfer electrodes of the solid-state imaging device 2.

  The signal charge generated in the photoelectric conversion element 2a of the imaging element 2 is read to the vertical charge transfer element 2b by the vertical transfer electrode driven by the DRV 6, and then transferred to the horizontal charge transfer element 2c. The charge transferred to the horizontal charge transfer element 2c is transferred in the direction of the output unit 2d by a drive pulse applied from the timing generator 7 to the horizontal transfer electrode, and the output unit 2d converts the charge amount into a voltage value and outputs an output signal. Output as (OS).

  FIG. 11 is a functional configuration diagram of the ternary driver circuit. The ternary driver circuit includes a control logic 41 and an output circuit 42. The output circuit 42 has a switching function of selecting one of the power supply voltages VH (= + 15 V), VL (= −8 V), and VM (= GND0 V) by a transistor and connecting it to the output terminal TO. In order to select one of the ternary values VH, VL, and VM, a 2-bit signal is required. For this reason, the control logic 41 receives two signals TI and PG.

  The 3V level signals TI and PG inputted from the timing generator 7 to the control logic 41 are level-converted into signals having an amplitude of + 15V / −8V by a level shift circuit (not shown) in the control logic 41, and the output circuit 42 In response to a signal from the control logic 41, three types of voltages VH, VL, and VM for driving the image sensor 2 are output.

  FIG. 12 is a functional configuration diagram of the binary driver circuit. The binary driver circuit includes a control logic 43 and an output circuit 44. The output circuit 44 has a switching function for selecting either the power supply voltage VM (= 0 V) or VL (= −8 V) by a transistor and connecting it to the output terminal BO. Since the binary VL and VM are selected, a 1-bit signal is sufficient. For this reason, only one signal BI of, for example, 3V level is input from the timing generator 7 to the control logic 43.

  The control logic 43 converts the level of the 3V level signal BI into a high voltage amplitude signal by an internal level shift circuit (not shown), and the output circuit 44 outputs two kinds of voltages VM and VL for driving the image sensor 2. Output.

  FIG. 13 is a diagram showing an example of a timing chart at the time of charge transfer and charge read by the voltages VH, VL, VM output from the ternary driver circuit.

  At the time of charge transfer, the input signal PG is set to a high level, and the input signal TI is an alternating signal of a low level and a high level. Thereby, from the ternary driver circuit, an alternating signal of VM (= 0V) and VL (= −8V) is applied as an output TO to the vertical transfer electrode, and charge transfer is performed.

  At the time of charge reading, the input signal TI is set to a low level and the input signal PG is set to a low level. As a result, the output TO of the ternary driver circuit becomes the high voltage VH (= + 15 V), and the accumulated charge of the photoelectric conversion element is read out to the vertical transfer element.

  FIG. 14 is a diagram illustrating an example of a timing chart at the time of charge transfer and charge read by the voltages VL and VM output from the binary driver circuit.

  At the time of charge transfer, the input signal BI is changed to a low level and high level alternating signal. As a result, the output BO becomes an alternating signal between the voltage VM (= 0V) and the voltage VL (= −8V), and charge transfer is performed.

  At the time of charge reading, the input signal BI is set to a low level. As a result, the output BO of the binary driver circuit becomes the voltage VM (= 0V).

  FIG. 15 is an equivalent circuit diagram of the main part of the solid-state imaging device 2, DRV 6, and power source 8. In FIG. 15, a transistor circuit for selecting the intermediate voltage VM is illustrated with a simplified symbol.

  The VH regulator 14 of DRV6 can be represented by a voltage source 14a and an output resistor 14b, and a power supply bypass capacitor 27 is connected to the output VH. The VL regulator 16 can also be represented by a voltage source 16a and an output resistor 16b, and a power supply bypass capacitor 37 is connected to the output VL. Only the ternary driver circuit is shown in DRV 6 in FIG. 15, and the output TO drives the capacitor Cvccd of the vertical transfer electrode provided in the image sensor 2.

  The power source VH0 of the VH regulator 14 is supplied from the charge pump circuit 13 as described with reference to FIG. The current supply capability of the charge pump circuit is small, and the current supply capability of the VH regulator 14 cannot be increased. Therefore, the output resistance of the VH regulator 14 is increased. Similarly, since the power supply VL0 of the VL regulator 16 is supplied by the charge pump circuit 15, the current supply capability of the VL regulator 16 cannot be increased, and the output resistance of the VL regulator 16 also increases.

  When the vertical transfer electrode is driven using such a power supply configuration, the following problems occur.

  FIG. 16 is a waveform diagram when the vertical transfer electrode is subjected to charge reading operation by the equivalent circuit of FIG. The output TO of the DRV 6 is switched from the voltage VM (= 0V) to the voltage VH (= + 15V). When the transistor Ml is turned on, the output VH and Cvccd are connected with a low resistance, and the Cvccd is charged to the VH level. However, the output resistance of the VH regulator 14 is much larger than the ON resistance of the transistor M1 of the DRV6. In the current supply from the VH regulator 14, Cvccd cannot be charged immediately, but is charged from the power supply bypass capacitor 27 of the output VH to Cvccd. Accordingly, the potential level of the output VH is lowered by the amount charged to Cvccd.

  The potential level of the output VH is restored (charged) to the original level by the VH regulator 14 until the next read operation. Therefore, although the amplitude of the output TO does not gradually decrease, there arises a problem that it becomes smaller than the amplitude level of the output TO that is originally required.

  FIG. 17 is a waveform diagram when the vertical transfer electrode is transferred by the equivalent circuit of FIG. The output TO of the DRV 6 is switched from the voltage VM to the voltage VL (= −8 V). When the transistor M2 is turned on, the output VL and Cvccd are connected with a low resistance, and the Cvccd is charged to the VL level. However, the output resistance of the VL regulator 16 is much larger than the ON resistance of the transistor M2 of the DRV6. The current supply from the VL regulator 16 cannot immediately charge Cvccd. For this reason, Cvccd is charged from the power supply bypass capacitor 37 of the output VL. Therefore, the potential level of the output VL rises by the amount charged to Cvccd.

  The potential level of the output VL is restored (charged) to the original level by the VL regulator 16 before the next transfer operation. Therefore, although the amplitude of the output TO does not gradually decrease, there arises a problem that it becomes smaller than the amplitude level of the output TO that is originally required.

  Furthermore, a problem also occurs when performing high-speed smear charge sweeping described below. When the light shielding means 3 is provided on the front surface of the image sensor 2 as shown in FIG. 6, the DVR 6 performs the original signal charge transfer when the vertical transfer electrode of the image sensor 2 is charge transfer driven (binary drive). Prior to this, the vertical transfer electrode is driven to transfer charges at high speed so as to sweep out smear charges from the vertical transfer element (see, for example, Patent Document 1 below).

  18 and 19 are diagrams illustrating an example of a timing chart when the ternary driver circuit and the binary driver circuit sweep out smear charges at high speed. In both timing charts, smear charges are quickly swept out at a higher drive frequency (more than 10 times that in normal transfer) before the read transfer of the vertical transfer electrode.

  FIG. 20 is a waveform diagram when the vertical transfer electrode is subjected to a smear charge high-speed sweep operation by the equivalent circuit of FIG. The output TO of the DRV 6 is switched from the voltage VM to the voltage VL. When the transistor M2 is turned on, the output VL and Cvccd are connected with a low resistance, and the Cvccd is charged to the VL level. However, the output resistance of the VL regulator 16 is much larger than the ON resistance of the transistor M2 of the DRV6. With the current supply from the VL regulator 16, Cvccd cannot be charged immediately, but is charged from the power supply bypass capacitor 37 of the output VL to Cvccd. Therefore, the output VL level rises by the amount charged to Cvccd.

  Up to this point, the transfer operation described in FIG. 17 is the same. However, since high-speed sweeping of smear charges has a high driving frequency, the VL regulator 16 cannot recover (charge) the output VL to the original level until the next output TO changes from the voltage VM to the voltage VL. Accordingly, the amplitude of the output TO is gradually reduced, and there arises a problem that the amplitude level of the output TO is originally required.

  As described above, when the vertical transfer electrode is driven using a power source in which a charge pump circuit and a regulator circuit are combined, it cannot be driven at an originally required amplitude level. There is a problem that the characteristics are adversely affected and the image obtained from the imaging module is deteriorated.

  A conventional example of the ternary driver circuit is described in Patent Document 2 below, and a conventional example of the charge pump circuit is described in Patent Document 3 below.

JP 2003-197895 A JP 2001-128073 A JP 2000-105611 A

  An object of the present invention is to provide a regulator circuit capable of outputting a voltage having a specified amplitude level even when combined with a power supply having a low current supply capability such as a charge pump circuit, a power supply circuit using this regulator circuit, An object of the present invention is to provide an imaging module using this power supply circuit.

  The regulator circuit according to the present invention includes a voltage control unit that controls the output voltage at the output terminal to be constant by controlling the amount of potential drop with respect to the input voltage, and monitors the output current of the voltage control unit. A current determination means for determining whether or not the output current is greater than a predetermined current; and a current that is connected to the output terminal of the voltage control means and causes a compensation current to flow through the output terminal in accordance with the determination result of the current determination means And a booster means.

  The current determination means of the regulator circuit of the present invention outputs a detection signal when the output current becomes larger than the predetermined current.

  The current booster means of the regulator circuit of the present invention selects and outputs either the first voltage source having a predetermined output impedance or the second voltage source having a lower output impedance than the first voltage source. And a voltage element that connects the output terminal of the voltage control unit and the output terminal of the voltage selection unit.

  The voltage selection means of the regulator circuit of the present invention selects the output of the first voltage source when the output current is smaller than the predetermined current, and when the output current is larger than the predetermined current, The output of the second voltage source is selected.

  The voltage selection means of the regulator circuit according to the present invention is configured such that the current that flows when the voltage control means flows when the second voltage source is changed to the state where the first voltage source is selected can flow. The output impedance of the first voltage source is set to be smaller than the current value.

  The regulator circuit according to the present invention is characterized in that the absolute value of the output voltage of the voltage selection means is set relatively low with respect to the absolute value of the output voltage of the voltage control means.

  The power supply circuit of the present invention includes a charge pump circuit that boosts an input voltage to a voltage higher than the input voltage in a power supply circuit that generates a predetermined voltage to be applied to a vertical transfer electrode of a CCD solid-state imaging device, The regulator circuit according to any one of the above, which controls an output voltage to the predetermined voltage.

  An imaging module of the present invention includes a CCD solid-state imaging device and the above-described power supply circuit that outputs a predetermined voltage to a vertical transfer electrode of the CCD solid-state imaging device.

  According to the present invention, it is possible to drive the vertical transfer electrode of the CCD solid-state imaging device at a specified amplitude level even in combination with a charge pump circuit having a low current supply capability.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  The regulator circuit according to the embodiment of the present invention is used in place of, for example, the VH regulator 14 and the VL regulator 16 shown in FIG. 7 provided in the power supply 8 of the imaging module shown in FIG. Since the configuration and operation of FIGS. 6, 7, and 8 according to the present embodiment are as described above, the description thereof is omitted.

  FIG. 1 is a circuit diagram in which a VH regulator 114 according to an embodiment of the present invention is connected to a DRV 6 and an image sensor 2. The VH regulator 114 of this embodiment has a configuration in which an additional circuit is added to the configuration of the conventional VH regulator 14 (voltage control means) shown in FIG. For this reason, the same circuit elements as those of FIG. 8 (error amplifier 21, V / I conversion transistor 22, diode-connected transistor 23, output transistor 24, resistors 25 and 26 for dividing the output voltage, and power supply bypass capacitor 27 The output terminal 28) will be described with the same reference numerals.

  The VH regulator 114 of this embodiment includes a current determination unit including a monitor transistor 51, a constant current source (IlimH) 52, an output transistor 53, and a switch transistor in addition to the conventional configuration of FIG. 54, a voltage selection means including a constant current source (Isink) 55, and a coupling capacitor 56 as a capacitive element are added. The voltage selection means and the coupling capacitor 56 constitute voltage booster means.

  As the error amplifier 21, an operational amplifier is used, and its DC gain is about 40 dB to 80 dB. Further, the resistors 25 and 26 are set so that the ratio thereof divides the output voltage VH by resistance and applies the same voltage as the reference value (Vref) to the negative input of the error amplifier 21.

  The output of the error amplifier 21 is connected to the gates of the V / I conversion transistor 22 and the monitor transistor 51. The V / I conversion transistor 22 and the monitor transistor 51 increase or decrease the error current value according to the output voltage of the error amplifier 21. To do.

  The error current value due to the V / I conversion transistor 22 flows to the diode-connected transistor 23 whose source is connected to the output voltage VH0 of the charge pump circuit 13 (see FIG. 7) of the preceding stage. The output transistor 24 forms a current mirror with the diode-connected transistor 23, amplifies the error current value by the size ratio of the diode-connected transistor 23 and the output transistor 24, and outputs the current from the power source VH0 to the output VH (output terminal 28). ).

  The current flowing through the V / I conversion transistor 22 is an error current value, but is proportional to the output current of the output VH, and the current flowing through the monitor transistor 51 having the same gate / source voltage as the V / I conversion transistor 22. Can monitor the increase or decrease of the output current from the output VH.

  The current determination means composed of the monitor transistor 51 and the constant current source (IlimH) 52 connected to the drain (connection node XBTH) of the monitor transistor 51 and the current of the constant current source (IlimH) 52 The comparison is performed, and the current determination result is output as the potential change of the node XBTH.

  When the current that can be passed through the monitor transistor 51 is smaller than the current of the constant current source (I1imH) 52, the potential of the node XBTH rises to about 3V (VDD level), and conversely the monitor of the current of the constant current source (IlimH) 52 When the current that can be passed through the transistor 51 is large, the potential of the node XBTH drops to the GND level. The current value of the constant current source (IlimH) 52 is set so that the potential of the node XBTH changes from the VDD level to the GND level when the output VH is equal to or higher than the rated current value.

  The node XBTH is commonly connected to the gates of the output transistor 53 and the switch transistor 54 constituting the voltage selection unit. The source of the output transistor 53 is connected to the output of the VDD regulator 12 shown in FIG. 7, and the output transistor 53 is cut off when the potential of the node XBTH is at the VDD level. However, when the potential of the node XBTH falls from the VDD level, the output transistor 53 causes a current to flow from the power supply VDD to its drain output BTH and the transistor 54.

  The current that can be passed through the output transistor 53 is controlled by the potential level of the node XBTH. The output transistor 53 is set to a large size in order to increase the current supply capability. However, the output transistor 53 can be constituted by a low-breakdown-voltage fine transistor by operating between VDD and GND, and the chip size does not increase. Further, since the output of the VDD regulator 12 having a high current supply capability is used as the power supply VDD, a current much larger than the output VH can be passed.

  A constant current source (Isink) 55 is connected to the source of the switch transistor 54. When the node XBTH is at the VDD level, the switch transistor 54 is turned on, and the current of the constant current source 55 is supplied from the output BTH to the GND. When the potential of the node XBTH is at the GND level, the switch transistor 54 is cut off, and no current flows from the output BTH to the GND. The current value of the constant current source (Isink) 55 is set smaller than the current value of the constant current source (IlimH) 52. The coupling capacitor 56 connects between the output VH and the output BTH.

  FIG. 2 is a waveform diagram during the read operation of the vertical transfer electrode when the VH regulator 114 of FIG. 1 is used. First, the DRV 6 sets its output TO to the voltage VM (= 0 V), and Cvccd of the image sensor 2 is set to the VM level. At this time, since the transistor M1 of the DRV6 shown in FIG. 1 is OFF, no current flows from the output VH to Cvccd. The output VH is at a specified VH level by the negative feedback loop. Since there is almost no load current of the output VH, the current that the monitor transistor 51 can flow is smaller than the current value of the constant current source (IlimH) 52, and the node XBTH is at the VDD level.

  Since the potential of the node XBTH is at the VDD level, the output transistor 53 is cut off. Further, the switch transistor 54 is turned ON, and the current of the constant current source 55 is supplied from the output BTH to GND (first voltage source). When the potential of the output BTH is higher than the GND level, the potential of the output BTH is gradually lowered by the constant current source 55, and when the potential reaches the GND level, no current flows. At this time, the output VH becomes VH level (= + 15 V), the output BTH becomes GND level (= 0 V), and the coupling capacitor 56 is initialized.

  Next, the output TO is switched from the voltage VM to the voltage VH. The transistor Ml of the DRV6 is turned on, the outputs VH and Cvccd are connected with a low resistance, and Cvccd is to be charged to the VH level. Since the VH regulator 114 charges Cvccd, the current output from the output terminal 28 increases. As a result, the current that can be passed through the monitor transistor 51 also increases, becomes larger than the current value of the constant current source 52, and the potential of the node XBTH decreases from the VDD level to the GND level.

  When the potential level of the node XBTH decreases in the direction of the GND level, the output transistor 53 is turned on, and the current flowing from the power supply VDD (second voltage source) to the output BTH increases. This current rapidly charges Cvccd through the coupling capacitor 56.

  When Cvccd is charged and the output VH becomes close to the VH level, the output current from the output VH decreases, the current that the monitor transistor 51 can flow also decreases, and the current value of the constant current source (IlimH) 52 becomes smaller. XBTH rises from the GND level to the VDD level. Then, the current flowing from the power supply VDD to the output BTH by the output transistor 53 decreases. When the output VH becomes the VH level, the node XBTH becomes the VDD level, and the output transistor 53 is cut off and the current flowing from the power supply VDD to the output VH. Will disappear.

  Therefore, the output VH is controlled so as to rise at a high speed to the prescribed VH level, and the output TO of the DRV 6 becomes the prescribed VH level. The output BTH level increases in the direction from the GND level to the VDD level as much as Cvccd is charged. However, since the node XBTH becomes the VDD level, the switch transistor 54 is turned on and the output BTH is switched from the output BTH to the GND. Isink) 55 causes a constant current to flow and gradually sets the output BTH level to the GND level.

  Although this current is supplied from the output VH, the current value of the constant current source (Isink) 55 is set smaller than the current value of the constant current source (IlimH) 52. It is smaller than the current value of the constant current source (IlimH) 52, and the node XBTH is at the VDD level. Therefore, the output transistor 53 is not turned ON.

  Since the output BTH may be set to the GND level before the next charge reading operation, there is no problem even if the current supply capability of Isink is low. The capacitance value of the coupling capacitor 56 is set to such a value that the output BTH does not reach the VDD level when Cvccd is charged.

  Even if the VH regulator circuit 114 of this embodiment is used together with the charge pump circuit 13 with the power supply 8, it is possible to drive the vertical transfer electrode of the image sensor 2 with a prescribed amplitude level.

  In addition, the VH regulator circuit 114 of the present embodiment changes when the voltage selection means including the transistors 53 and 54 changes from the state in which the VDD power source (second voltage source) is selected to the state in which the GND (first voltage source) is selected. The output impedance of the first voltage source is set so that the current flowing through the first voltage source is smaller than the maximum current value that can be passed by the voltage control means (that is, the current that can be passed through the constant current source 55 is set low), and Since the absolute value of the output voltage of the voltage selection means (VDD = 3V in the above example) is set relatively low with respect to the absolute value of the output voltage of the voltage control means (VH = + 15V in the above example), the specified amplitude level Can be kept more stable.

  FIG. 3 is a circuit diagram in which the VL regulator 116 according to one embodiment of the present invention is connected to the DRV 6 and the image sensor 2. The VL regulator 116 of this embodiment has a configuration in which an additional circuit is added to the configuration of the conventional VL regulator 16 (voltage control means) shown in FIG. For this reason, the same circuit elements as those of FIG. 9 (error amplifier 31, V / I conversion transistor 32, diode-connected transistor 33, output transistor 34, resistors 35 and 36 for dividing the output voltage, and power supply bypass capacitor 37 are provided. The output end 38) will be described with the same reference numerals.

  The VL regulator 116 of the present embodiment includes a monitor transistor 61 and a constant current source (IlimL) 62 that constitute a current determination means, and an output that constitutes a voltage selection means, in addition to the conventional configuration of FIG. 9 that constitutes a voltage control means. A transistor 63, a switch transistor 64, a constant current source (Isource) 65, and a coupling capacitor 66 as a capacitive element are added. The voltage selection means and the coupling capacitor 66 constitute a voltage booster means.

  As the error amplifier 31, an operational amplifier is used, and its DC gain is about 40 dB to 80 dB. Further, the ratio of the resistors 35 and 36 is set so that the output voltage VL is voltage-divided and the same voltage as the reference voltage (Vref) is applied to the negative input of the error amplifier 31.

  The output of the error amplifier 31 is connected to the gates of the V / I conversion transistor 32 and the monitor transistor 61. The V / I conversion transistor 32 and the monitor transistor 61 increase or decrease the error current value according to the output voltage of the error amplifier 31. To do.

  The error current value by the V / I conversion transistor 32 flows to the diode-connected transistor 33 whose source is connected to the voltage VL0 output from the charge pump circuit 15 of FIG. The output transistor 34 constitutes a current mirror with the diode-connected transistor 33, amplifies the error current value by the size ratio of the diode-connected transistor 33 and the output transistor 34, and flows the current from the output VL to the power supply VL0. .

  The current flowing through the V / I conversion transistor 32 is an error current value, but is proportional to the output current of the output VL, and the monitor transistor 61 having the same gate / source voltage as the V / I conversion transistor 32 outputs Increase / decrease in output current from VL can be monitored.

  A constant current source (IlimL) 62 is connected to the node XBTL connected to the drain of the monitor transistor 61. A comparison is made between the current flowing through the monitor transistor 61 and the current of the constant current source 62. When the current that can be passed through the monitor transistor 61 is smaller than the current of the constant current source 62, the node XBTL is in the direction from the VDD level to the GND level. To descend.

  Conversely, when the current that can be passed through the monitor transistor 61 is larger than the current of the constant current source 62, the node XBTL rises from the GND level to the VDD level. The current value of the constant current source 62 is set so that the node XBTL changes from the GND level to the VDD level when the output VL is equal to or higher than the rated current value.

  Node XBTL is connected to the gates of output transistor 63 and switch transistor 64. The source of the output transistor 63 is connected to GND, and the output transistor 63 is cut off when the potential of the node XBTL is at the GND level. When the potential of the node XBTL rises from the GND level, a current flows from the output BTL connected to the drain of the output transistor 63 to the GND.

  The current that can flow through the output transistor 63 can be controlled by the potential level of the node XBTL. The output transistor 63 is set to a large size in order to increase the current supply capability. However, the output transistor 63 can be constituted by a low-breakdown-voltage fine transistor by operating between VDD and GND, and the chip size does not increase.

  Further, since the output transistor 63 allows a current to flow through the GND, a current much larger than the output VL can be passed. A current source 65 is connected to the source of the switch transistor 64, and when the potential of the node XBTL is at the GND level, the switch transistor 64 is turned on to pass a current from the power supply VDD to the output BTL. When the potential of the node XBTL is at the VDD level, the switch transistor 64 is cut off and no current flows from the power supply VDD to the output BTL.

  The current value of the constant current source 65 is set smaller than the current value of the constant current source 62. The coupling capacitor 66 connects between the output VL and the output BTL.

  FIG. 4 is a waveform diagram during the transfer operation of the vertical transfer electrode when the VL regulator 116 of FIG. 3 is used. First, the DRV 6 sets the output TO to the voltage VM and sets Cvccd of the image sensor 2 to the VM level. At this time, since the transistor M2 of the DRV6 shown in FIG. 3 is OFF, no current flows from Cvccd to the output VL (output terminal 38).

  The output VL is at a specified VL level by a negative feedback loop. Since there is almost no load current of the output VL, the current that the monitor transistor 61 can flow is smaller than the current value of the constant current source 62, and the potential of the node XBTL becomes the GND level. Since the potential of the node XBTL is at the GND level, the output transistor 63 is cut off. Further, the switch transistor 64 is turned on, and the current source 65 allows a current to flow from the power supply VDD to the output BTL.

  When the potential of the output BTL is lower than the VDD level, the output BTL gradually rises by the constant current source 65, and when the potential eventually becomes the VDD level, no current flows. At this time, the output VL becomes the VL level (= −8 V), the output BTL becomes the VDD level (= 3 V), and the coupling capacitor 66 is initialized.

  Next, the output TO is switched from the voltage VM (= 0V) to the voltage VL (= −8V). The transistor M2 of the DRV6 is turned on, the outputs VL and Cvccd are connected with a low resistance, and an attempt is made to charge Cvccd to the VL level. Since the VL regulator 116 charges Cvccd, the current flowing from the output VL to the power supply VL0 increases.

  As a result, the current that can be passed through the monitor transistor 61 also increases and becomes larger than the current value of the constant current source 62, and the potential of the node XBTL rises from the GND level to the VDD level. Then, the output transistor 63 is turned on, and the current flowing from the output BTL to GND increases. This current rapidly charges Cvccd through the coupling capacitor 66.

  When Cvccd is charged and the output VL becomes close to the VL level, the current flowing from the output VL to the power supply VL0 decreases, the current that the monitor transistor 61 can flow also decreases, and becomes smaller than the current value of the constant current source 62, and the node XBTL The potential decreases from the VDD level to the GND level. Then, the current flowing from the output BTL to the GND by the output transistor 63 decreases.

  When the output VL becomes VL level, the potential of the node XBTL becomes GND level, the output transistor 63 is cut off, and no current flows from the output BTL to GND. Accordingly, the output VL is controlled so as to rapidly decrease to the prescribed VL level, and the output TO of the DVR 6 becomes the prescribed VL level.

  Although the potential level of the output BTL has decreased from the VDD level to the GND level as much as Cvccd is charged, the potential of the node XBTL becomes the GND level, so that the switch transistor 64 is turned on and the constant current source 65 A current flows from the power supply VDD to the output BTL, and the potential level of the output BTL gradually becomes the VDD level.

  This current flows from the output VL to the power supply VL0. However, since the current value of the constant current source 65 is set smaller than the current value of the constant current source 62, the current that can be passed through the monitor transistor 61 is constant current source 62. The potential of the node XBTL is at the GND level.

  Therefore, the output transistor 63 is not turned ON. Since the potential of the output BTL may be set to the VDD level before the next transfer operation, there is no problem even if the current supply capability of Isource is low. The capacitance value of the coupling capacitor 66 is set to such a value that the potential of the output BTL does not reach the GND level when Cvccd is charged.

  As described above, the regulator circuit 116 according to the present embodiment can drive the vertical transfer electrode of the imaging device 2 at a specified amplitude level even when the regulator circuit 116 is used with the power supply 8 together with the charge pump circuit 15. Become.

  FIG. 5 is a waveform diagram when the regulator circuit according to the above-described embodiment is used and the vertical transfer electrode of the solid-state imaging device 2 is driven at high speed for smear charge sweeping. In this case, the capacitance value of the coupling capacitor 66 should be set large.

  First, the DRV 6 sets the output TO to the voltage VM and sets the Cvccd of the image sensor 2 to the VM level (= 0V). At this time, since the transistor M2 of the DRV6 is OFF, no current flows from Cvccd to the output VL. The output VL is at a specified VL level (= −8 V) by the negative feedback loop. Since there is almost no load current of the output VL, the current that the monitor transistor 61 can flow is smaller than the current value of the constant current source 62, and the potential of the node XBTL becomes the GND level (= 0V).

  Since the potential of the node XBTL is at the GND level, the output transistor 63 is cut off. Further, the switch transistor 64 is turned ON, and a current flows from the power supply VDD to the output BTL by the constant current source 65. When the potential of the output BTL is lower than the VDD level, the constant current source 65 gradually increases the potential of the output BTL, and when the potential eventually reaches the VDD level, no current flows. At this time, the potential of the output VL becomes VL level (= −8V), the potential of the output BTL becomes VDD level (about 3V), and the coupling capacitor 66 is initialized.

  Next, the output TO of the DRV 6 is switched from the voltage VM to the voltage VL. The transistor M2 of the DRV6 is turned on, the outputs VL and Cvccd are connected with a low resistance, and an attempt is made to charge Cvccd to the VL level.

  Since the VL regulator 116 charges Cvccd, the current flowing from the output VL to the power supply VL0 increases. Then, the current that can be passed through the monitor transistor 61 also increases and becomes larger than the current value of the constant current source 62, and the potential of the node XBTL rises from the GND level to the VDD level. As a result, the output transistor 63 is turned on, and the current flowing from the output BTL to GND increases.

  This current rapidly charges Cvccd through the coupling capacitor 66. When Cvccd is charged and the output VL becomes close to the VL level, the current flowing from the output VL to the power supply VL0 decreases, the current that the monitor transistor 61 can flow also decreases, and becomes smaller than the current value of the constant current source 62, and the node XBTL The potential decreases from the VDD level to the GND level. Then, the output transistor 63 reduces the current flowing from the output BTL to GND. When the output VL becomes the VL level, the potential of the node XBTL becomes the GND level, the output transistor 63 is cut off, and no current flows from the output BTL to the GND.

  Accordingly, the output VL is controlled so as to rapidly decrease to the prescribed VL level, and the output TO of the DVR 6 becomes the prescribed VL level. The potential level of the output BTL decreases in the direction from the VDD level to the GND level as much as Cvccd is charged. In this case, if the capacitance value of the coupling capacitor 66 is large, the decrease in the potential level of the output BTL is slight. It does not drop significantly like the BTL waveform shown in FIG.

  Further, since the potential of the node XBTL becomes the GND level, the switch transistor 64 is turned on, a constant current flows from the power source VDD to the output BTL by the constant current source 65, and the potential of the output BTL is set in the direction of the VDD level. . This current flows from the output VL to the power supply VL0. However, since the current value of the constant current source 65 is set smaller than the current value of the constant current source 62, the current that can be passed through the monitor transistor 61 is constant current source 62. And the potential of the node XBTL becomes the GND level.

  Therefore, the output transistor 63 is not turned ON. However, since the drive frequency for performing high-speed sweeping is high, the next output TO change immediately occurs, and since the capacitance value of the coupling capacitor 66 is increased, the potential of the output BTL can hardly be increased. Accordingly, since the potential level of the output BTL approaches the GND level during the high-speed sweep period, the capacitance value of the coupling capacitor 66 is increased so that the potential of the output BTL does not reach the GND level until the high-speed sweep is completed. Keep it.

  When high-speed sweeping is completed and normal charge transfer is performed, the driving frequency is lowered. The output BTL increases with the current from the constant current source 65, rather than the decrease due to charging of Cvccd. Since the charge transfer period is much longer than the high-speed sweep period, the potential of the output BTL finally becomes the VDD level. Therefore, since the output BTL may be set to the VDD level before the next high-speed sweep, there is no problem even if the current supply capability of Isource is low.

  As described above, even when a power source combining a charge pump circuit and a regulator circuit is used, if the VL regulator 116 according to the above-described embodiment is used, the vertical transfer electrode can be driven to be swept out at a specified amplitude level. Is possible.

  Since the regulator circuit according to the present invention can maintain the output voltage at a specified amplitude level, the regulator circuit is useful, for example, for a drive circuit for a vertical transfer electrode of a CCD type solid-state imaging device.

1 is a circuit diagram of a high voltage regulator circuit according to an embodiment of the present invention. FIG. 2 is an operation waveform diagram of the regulator circuit shown in FIG. 1. 1 is a circuit diagram of a low voltage regulator circuit according to an embodiment of the present invention. FIG. 4 is an operation waveform diagram of the regulator circuit shown in FIG. 3. FIG. 4 is an operation waveform diagram when the solid-state imaging device is driven to sweep out unnecessary charges using the regulator circuit shown in FIG. 3. It is a block diagram of the general imaging module mounted in small electronic devices, such as a mobile telephone. It is a detailed block diagram of the power supply shown in FIG. FIG. 8 is a conventional circuit diagram of the high voltage regulator circuit shown in FIG. 7. FIG. 8 is a conventional circuit diagram of the low voltage regulator circuit shown in FIG. 7. FIG. 7 is a schematic diagram of a CCD image pickup device and a drive circuit shown in FIG. 6. FIG. 11 is a circuit diagram of the ternary selection driver shown in FIG. 10. FIG. 11 is a circuit diagram of the binary selection driver shown in FIG. 10. 12 is a timing chart when the image sensor is driven using the ternary selection driver shown in FIG. 11. 12 is a timing chart when the image sensor is driven using the binary selection driver shown in FIG. 11. FIG. 7 is an equivalent circuit diagram of essential parts of the image sensor, the drive circuit, and the power source shown in FIG. 6. FIG. 10 is a waveform diagram when the image sensor is read and driven using the conventional regulator circuit shown in FIGS. 8 and 9. FIG. 10 is a waveform diagram when the image pickup device is driven to transfer charges using the conventional regulator circuit shown in FIGS. 8 and 9. FIG. 12 is a timing chart when driving the image pickup device at high speed using the ternary selection driver shown in FIG. 11. FIG. FIG. 13 is a timing chart when driving the image pickup device at a high speed by using the binary selection driver shown in FIG. 12. FIG. It is a waveform diagram of a drive circuit output voltage when an image pickup device is driven at a high speed by using a conventional regulator circuit.

Explanation of symbols

2 CCD type solid-state imaging device (CCD)
6 Drive circuit (DRV)
8 Power supply (PWR)
13, 15 Charge pump circuit 14, 114 High voltage (VH) regulator circuit 16, 116 Low voltage (VL) regulator circuit 21, 31 Error amplifier 22, 32 V / I conversion transistor 23, 33 Diode-connected transistors 24, 34, 53 , 63 Output transistor 25, 26, 35, 36 Voltage dividing resistor 28 Output terminal 51, 61 Monitor transistor 52, 55, 62, 65 Constant current source 54, 64 Switch transistor 56, 66 Coupling capacitor (capacitance element)

Claims (8)

  In a regulator circuit comprising voltage control means for controlling the output voltage at the output end to be constant by controlling the amount of potential drop with respect to the input voltage, the output current of the voltage control means is monitored and the output current is greater than a predetermined current. Current determining means for determining whether or not the current has increased, and current booster means connected to the output terminal of the voltage control means and for supplying a compensation current to the output terminal according to the determination result of the current determining means. Regulator circuit characterized by.   The regulator circuit according to claim 1, wherein the current determination unit outputs a detection signal when the output current becomes larger than the predetermined current.   The current booster means selects and outputs either one of a first voltage source having a predetermined output impedance and a second voltage source having an output impedance lower than the first voltage source; 3. The regulator circuit according to claim 1, further comprising: a capacitive element that connects the output terminal of the voltage control unit and the output terminal of the voltage selection unit.   The voltage selection means selects the output of the first voltage source when the output current is smaller than the predetermined current, and outputs the second voltage source when the output current is larger than the predetermined current. The regulator circuit according to claim 3, wherein the regulator circuit is selected.   In the voltage selection unit, a current that flows when the second voltage source is selected to change to a state in which the first voltage source is selected is smaller than a maximum current value that the voltage control unit can flow. The regulator circuit according to claim 4, wherein an output impedance of the first voltage source is set as described above.   6. The regulator circuit according to claim 3, wherein the absolute value of the output voltage of the voltage selection means is set relatively lower than the absolute value of the output voltage of the voltage control means. .   In a power supply circuit that generates a predetermined voltage to be applied to a vertical transfer electrode of a CCD type solid-state imaging device, a charge pump circuit that boosts an input voltage to a voltage higher than the input voltage, and an output voltage of the charge pump circuit to the predetermined voltage A power supply circuit comprising: the regulator circuit according to claim 1 to be controlled.   An imaging module comprising: a CCD solid-state imaging device; and a power supply circuit according to claim 7 for outputting a predetermined voltage to a vertical transfer electrode of the CCD solid-state imaging device.

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